KR100311523B1 - Frame Synchronization Establishment Method - Google Patents

Abstract

In the next generation mobile communication system, especially in the next-generation mobile communication system of the wideband code division multiple access method (hereinafter, abbreviated as W-CDMA), frame synchronization can be obtained more effectively even in a handover area by using an optimal pilot bit pattern. It is about how to make one.

Accordingly, the present invention uses a new pilot bit pattern provided to perform optimal frame synchronization in the uplink of the next generation mobile communication system, and according to the correlation processing result of the proposed pilot bit pattern, An accurate frame synchronization acquisition method is provided.

Description

Frame Synchronization Establishment Method

The present invention relates to a next generation mobile communication system, and more particularly, to a method for more effectively obtaining frame synchronization in a handover area using an optimal pilot bit pattern in a W-CDMA next generation mobile communication system.

Recently, ARIB in Japan, ETSI in Europe, T1 in the US, TTA in Korea, and TTC in Japan are the core networks of the existing Global System for Mobile Communications (GSM), which provides multimedia services such as voice, video and data. The next generation of mobile communication system based on wireless access technology was envisioned.

In order to present technical specifications for the next generation evolved mobile communication system, they agreed to joint research, and the project for this was called Third Generation Partnership Project (hereinafter abbreviated as 3GPP).

3GPP includes three major technical research areas.

The first is the 3GPP system and service sector, which is a study of the structure and service capabilities of the system based on the 3GPP specification.

Second, it is a research area for Universal Terrestrial Radio Access Network (UTRAN), where the Universal Terrestrial Radio Access Network (UTRAN) is based on W-CDMA according to Frequency Division Duplex (FDD) mode. Radio Access Network (RAN) using TD-CDMA according to Time Division Duplex (TDD) mode.

Third, it is a research section for core network that has evolved from the second generation mobile communication globalization system (GSM) and has third generation networking capability such as mobility management and global roaming.

In the above-described technical research divisions of 3GPP, a research section for a global radio access network (UTRAN) describes definitions and descriptions of a transport channel and a physical channel.

Dedicated Physical Channels (DPCHs) are used for uplinks and downlinks for physical channels, which are typically Superframes, Radio frames, and Timeslots. ) Consists of three hierarchical structures.

Currently, the 3GPP radio access network (RAN) standard defines a superframe as a maximum frame unit having a 720 ms period. In terms of the number of system frames, one superframe includes 72 radio frames.

In addition, in the current 3GPP radio access network (RAN) standard, a radio frame consists of 15 time slots, and each time slot is composed of fields having corresponding information bits according to a dedicated physical channel (DPCH).

1 is a diagram illustrating a structure of an uplink dedicated physical channel (DPCH) according to a 3GPP radio access network (RAN) standard.

In FIG. 1, there are two types of uplink dedicated physical channels (DPCHs), a dedicated physical data channel (DPDCH) and a dedicated physical control channel (DPCCH).

Of these uplink dedicated physical channels (DPCH), a dedicated physical data channel (DPDCH) is for carrying dedicated data, and the other dedicated physical control channel (DPCCH) is for carrying control information.

Dedicated Physical Control Channels (DPCCHs) that carry control information include pilot fields (1), transport format combination indicator fields (TFCI) (2), feedback information fields (FBI) (3) and transmit power control fields. It consists of several fields such as (TPC) (4).

Here, the transport format combined indicator field (TFCI) (2) supports the provision of multiple services at the same time, and if this transport format combined indicator field (TFCI) (2) is not included, fixed-rate service (Fixed-rate) service).

In addition, the pilot field 1 includes pilot bits that support channel estimation for coherent detection. In the current 3GPP radio access network (RAN) standard, 5 bits, 6 Use pilot bits of bits, 7 bits and 8 bits.

Table 1 below shows various channel information for the uplink dedicated physical control channel (DPCCH), where the channel bit rate and the channel symbol rate are just before spreading.

Channel bit rate (Kbps) Channel symbol rate (Ksps) Spreading Factor Bits per frame Bits per slot (bits / slots) Number of pilot bits (N _pilot ) Number of transmit power control bits (N _TPC ) Transmission Format Combined Indicator Bit Count (N _TFCI ) Number of feedback information bits (N _FBI ) 15 15 256 150 10 6 2 2 0 15 15 256 150 10 8 2 0 0 15 15 256 150 10 5 2 2 One 15 15 256 150 10 7 2 0 One 15 15 256 150 10 6 2 0 2 15 15 256 150 10 5 One 2 2

Table 2 below shows various channel information for the uplink dedicated physical data channel (DPDCH), where the channel bit rate and the channel symbol rate are just before spreading.

Channel Bit Rate (Kbps) Channel symbol rate (Ksps) Spreading Factor Bits per frame Bits per slot (bits / slots) Number of data bits (N _data ) 15 15 256 150 10 10 30 30 128 300 20 20 60 60 64 600 40 40 120 120 32 1200 80 80 240 240 16 2400 160 160 480 480 8 4800 320 320 960 960 4 9600 640 640

Currently, the 3GPP radio access network (RAN) standard proposes an optimal frame synchronization confirmation procedure and an acquisition procedure for the uplink dedicated physical channel (DPCH).

However, when the handover is performed in the 3GPP system using an asynchronous method between cells, accurate frame synchronization is not guaranteed when the frame synchronization acquisition procedure is used.

Therefore, there is a need for a faster and more accurate frame synchronization procedure in the handover region.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and uses a new pilot bit pattern provided to perform optimal frame synchronization in the uplink of a next-generation mobile communication system, and performs correlation processing of the proposed pilot bit pattern. According to the result, a method for acquiring a faster and more accurate frame synchronization in the handover region is provided.

A feature of the frame synchronization acquisition method according to the present invention for achieving the above object is, when a handover is performed between a serving cell and a neighboring cell for an arbitrary user (UE), the neighboring cell In acquiring frame synchronization for an uplink channel in the step of acquiring chip synchronization for the uplink channel, and as the chip synchronization is obtained, predetermined offset is obtained using various offset group information for the user side (UE). Acquiring similar frame synchronization having a frame error of?, And acquiring the final frame synchronization using the pilot bit pattern input as the chip synchronization and the similar frame synchronization are obtained.

Preferably, a positive maximum autocorrelation value is detected at a start delay time of a correlation period for each frame in which a pilot bit pattern used in acquiring the last frame synchronization is received, and each received frame is detected. A negative maximum cross-correlation value is detected at an intermediate delay time point for the correlation period.

1 is a diagram illustrating a structure of an uplink dedicated physical channel (DPCH) according to a 3GPP radio access network (RAN) standard.

FIG. 2 is a diagram showing a correlation result using a pilot bit pattern of an uplink according to the 3GPP radio access network (RAN) standard. FIG.

3 illustrates another correlation result using an uplink pilot bit pattern according to a 3GPP radio access network (RAN) standard.

4 is a diagram illustrating an uplink frame synchronization acquisition procedure in a handover area according to the present invention.

5 is a diagram illustrating a configuration of a correlation processing apparatus for obtaining uplink frame synchronization according to a first embodiment of the present invention.

6 is a diagram illustrating a configuration of a correlation processing apparatus for acquiring uplink frame synchronization according to a second embodiment of the present invention.

Hereinafter, a preferred embodiment of a method for obtaining frame synchronization according to the present invention will be described with reference to the accompanying drawings.

In order to achieve frame synchronization for an uplink dedicated physical channel (DPCH), the present invention uses the frame synchronization words of Table 3 according to the current 3GPP radio access network (RAN) standard.

Frame sync word C1 = (1 0 0 0 1 1 1 1 0 1 0 1 1 0 0) C2 = (1 0 1 0 0 1 1 0 1 1 1 0 0 0 0) C3 = (1 1 0 0 0 1 0 0 1 1 0 1 0 1 1) C4 = (0 0 1 0 1 0 0 0 0 1 1 1 0 1 1) C5 = (1 1 1 0 1 0 1 1 0 0 1 0 0 0 1) C6 = (1 1 0 1 1 1 0 0 0 0 1 0 1 1 1) C7 = (1 0 0 1 1 0 1 0 1 1 1 1 0 0 0) C8 = (0 0 0 0 1 1 1 0 1 1 0 0 1 0 1)

The frame sync word of Table 3 is used for frame sync detection for the uplink physical channel when the chip rate (15 slot) is 3.84 Mcps instead of 4.096 Mcps (16 slots) in the uplink physical channel.

Table 4 below shows a 15-bit pilot bit pattern using the frame sync words shown in Table 3. Uplink dedicated physical control channel (DPCCH) when the number of pilot bits constituting one slot is 5 bits or 6 bits. The pilot pattern is shown.

N _Pilot = 5 N _Pilot = 6 beat# 0 One 2 3 4 0 One 2 3 4 5 Slot # 1 Slot # 2 Slot # 3 Slot # 4 Slot # 5 Slot # 6 Slot # 7 Slot # 8 Slot # 9 Slot # 10 Slot # 11 Slot # 12 Slot # 13 Slot # 14 Slot # 15 One 0 0 0 One One One One 0 One 0 One One 0 0 One 0 One 0 0 One One 0 One One One 0 0 0 0 One One One One One One One One One One One One One One One One One 0 0 0 One 0 0 One One 0 One 0 One One 0 0 One 0 One 0 0 0 0 One One One 0 One One One One One One One One One One One One One One One One One One 0 0 0 One One One One 0 One 0 One One 0 0 One 0 One 0 0 One One 0 One One One 0 0 0 0 One One One One One One One One One One One One One One One One One 0 0 0 One 0 0 One One 0 One 0 One One 0 0 One 0 One 0 0 0 0 One One One 0 One One C1 C2 C3 C4 C1 C2 C3 C4

Table 5 below shows another 15-bit long pilot bit pattern using the frame sync words shown in Table 3, when the number of pilot bits constituting one slot is 7 bits or 8 bits. DPCCH) pilot pattern.

N _Pilot = 7 N _Pilot = 8 beat# 0 One 2 3 4 5 6 0 One 2 3 4 5 6 7 Slot # 1 Slot # 2 Slot # 3 Slot # 4 Slot # 5 Slot # 6 Slot # 7 Slot # 8 Slot # 9 Slot # 10 Slot # 11 Slot # 12 Slot # 13 Slot # 14 Slot # 15 One One One One One One One One One One One One One One One One 0 0 0 One One One One 0 One 0 One One 0 0 One 0 One 0 0 One One 0 One One One 0 0 0 0 One One One One One One One One One One One One One One One One One 0 0 0 One 0 0 One One 0 One 0 One One 0 0 One 0 One 0 0 0 0 One One One 0 One One One One One One One One One One One One One One One One One One One One One One One One One One One One One One One One One 0 0 0 One One One One 0 One 0 One One 0 0 One One One One One One One One One One One One One One One One 0 One 0 0 One One 0 One One One 0 0 0 0 One One One One One One One One One One One One One One One One One 0 0 0 One 0 0 One One 0 One 0 One One One One One One One One One One One One One One One One One 0 0 One 0 One 0 0 0 0 One One One 0 One One C1 C2 C3 C4 C1 C2 C3 C4

In the above Tables 4 and 5, four column sequences having a length of 15 slots are called C1, C2, C3, and C4 when the pilot bits are 5 bits, 6 bits, 7 bits, or 8 bits. Table 6 shows the arrangement according to the position of each pilot bit.

N _Pilot Pilot bit position number (bit #) Vertical sequence (15 slots long) 5 0 C1 One C2 3 C3 4 C4 6 One C1 2 C2 4 C3 5 C4 7 One C1 2 C2 4 C3 5 C4 8 One C1 3 C2 5 C3 7 C4

In this manner, four parallel sequences of 15 slot lengths allocated to each pilot bit, that is, code sequences having a total length of 60, are used for frame synchronization.

In Table 4 and Table 5, the shaded portion of all pilot bits is used for correlation processing for frame synchronization, and the pilot bits of other portions except this have a value of '1', and all of the pilot bits of '1' are used. The vertical sequence having is used for channel estimation for coherent detection.

In other words, when the pilot bit of each slot is 5 bits, bit # 0 (C1), bit # 1 (C2), bit # 3 (C3), and bit # 4 (C4) are 6 bits, and the pilot bit of each slot is 6 bits. Or bit # 1 (C1), bit # 2 (C2), bit # 4 (C3), and bit # 5 (C4) if 7 bits, and bit # 1 if the pilot bit of each slot is 8 bits. (C1), bits # 3 (C2), bits # 5 (C3), and bits # 7 (C4) are used for correlation processing for frame synchronization. Therefore, the pilot bits used for frame synchronization per slot are all 4 bits as pilot bits of each slot, and the total number of pilot bits used for radio frame synchronization is '60'.

In order to use the frame synchronization word of Table 3 according to the present invention for frame synchronization confirmation and acquisition, it is designed according to the following arrangement characteristics.

In each code sequence (C1, C2, C3, C4, C5, C6, C7, C8), the number of bit values '0' and '1' should be one more bit value '0' or a bit value '1'. It is designed to be one more. This means that when a sequence of non-shaded portions having a bit value of '1' is inserted between the code sequences of the shaded portion as shown in Table 4 or Table 5 above, the cross-correlation value between them is minimal at all delay points. It is to make it possible. At this time, even when a sequence having a bit value of '0' is inserted between the above code sequences C1, C2, C3, C4, C5, C6, C7, and C8 at all delay points, the minimum The code sequence is designed to be.

Further, each code sequence C1, C2, C3, C4, C5, C6, C7, C8 is mutually contiguous between adjacent code sequences (e.g., C1 and C2, C2 and C3, ...) at the point where the delay is zero. The correlation value is designed to be minimal.

Here, the code sequences C5, C6, C7 and C8 are shifts of the code sequences C1, C2, C3 and C4, and the code sequences C5, C6, C7 and C8 are cross-correlation values between adjacent code sequences when the delay is zero. The code sequences C1, C2, C3, and C4 are properly shifted to minimize this.

In addition, each code sequence C1, C2, C3, C4, C5, C6, C7, C8 is designed to have a minimum autocorrelation value at the delay time except for the delay time zero.

In addition, the cross-correlation value of the code sequence C1 and C2 is a maximum value having a negative polarity at the intermediate delay time point, and the cross-correlation value of C2 and C1 is the minimum value at the delay time except for the above intermediate delay time point. It is designed to be such that the cross-correlation value of the code sequences C3 and C4 becomes the maximum value having a negative polarity at the intermediate delay time point, and the cross-correlation of C4 and C3 at the other delay points except the above-described intermediate delay time point. The value is designed to be minimum.

Subsequently, the cross-correlation value of the code sequences C5 and C6 becomes a maximum value having a negative polarity at the intermediate delay time point, and the cross-correlation value of C6 and C5 is the minimum value at the delay time except for the above intermediate delay time point. It is designed to be such that the cross-correlation value of the code sequences C7 and C8 becomes the maximum value having a negative polarity at the intermediate delay point, and the cross-correlation of C8 and C7 at the other delay points except the above-described intermediate delay point. The value is designed to be minimum.

In particular, code sequence C2 is a sequence in which code sequence C1 is shifted and inverted at the same time, code sequence C4 is a sequence in which code sequence C3 is shifted and inverted at the same time, and code sequence C6 is shifted in code sequence C5. It is a sequence inverted at the same time, and the last code sequence C8 is also a sequence in which the code sequence C7 is shifted and inverted at the same time.

In the present invention, since the frame sync words are designed with the arrangement characteristics listed above, they can be used to confirm frame synchronization for the uplink dedicated physical channel (DPCH), and in particular, double check is possible in confirming frame synchronization.

As can be seen from the arrangement characteristics listed above, each code sequence of the frame sync word proposed in the present invention specifically exhibits an autocorrelation characteristic as shown in Equation 1 below.

Where i` = `1,2,3,... ,8

Here, R_C_i` (τ) are autocorrelation functions of each code sequence C1 to C8.

Equation 2 below classifies the frame sync words shown in Table 3 by class.

In Equation 2, code sequence pairs [C_i`, C_j] of the same class, that is, [C1, C2], [C3, C4], [C5, C6] and [C7, C8] are represented by the following Equations 3 and 4 Cross-correlation characteristics such as

However, (i = 1` & `j = 2) or (i = 3` &` j = 4) or (i = 5` & `j = 6) or (i = 7` &` j = 8).

However, (j = 2` & `i = 1), or (j = 4` &` i = 3), or (j = 6` & `i = 5), or (j = 8` &` i = 7). In Equation 3, R_ {C_i`, C_j} `(τ) is a cross-correlation function of code sequence pairs in each class represented by Equation 2, and in Equation 4, R_ {C_j`, C_i}` (τ + 1) is a code. A function that has correlated the sequence C_i with the code sequence C_j shifted by one bit in length.

Here, by combining the autocorrelation properties of Equation 1 and the cross-correlation properties of Equations 3 and 4 above, the generalized equations such as Equations 5 and 6 can be summarized.

, With α = 1,2,3,... ,8

,

Here, α = 2,4,6,8.

FIG. 2 illustrates a correlation result using an uplink pilot bit pattern according to a 3GPP radio access network (RAN) standard, and FIG. 3 illustrates an uplink pilot bit pattern according to a 3GPP radio access network (RAN) standard. It is a figure which shows another correlation result.

The correlation results of FIGS. 2 and 3 are obtained from Equations 5 and 6, wherein FIG. 2 is when α = 2 in Equations 5 and 6, and FIG. 3 is α = 4 in Equations 5 and 6. Correlation results used for frame synchronization detection.

More specifically, FIG. 2A illustrates the sum of the autocorrelation functions when α = 2 in Equation 5, and FIG. 2B illustrates the sum of the cross correlation function when α = 2 in Equation 6. 3A shows the sum of the autocorrelation functions when α = 4 in Equation 5, and FIG. 3B shows the sum of the cross correlation function when α = 4 in Equation 6.

By observing each of the correlation results of FIGS. 2 and 3, a single check is possible when detecting frame synchronization, and frame synchronization is detected by simultaneously observing the autocorrelation result and the cross correlation result in FIGS. 2 and 3. Double check is possible.

Next, a procedure of confirming chip synchronization and frame synchronization of an uplink channel using the pilot bit pattern described above and obtaining a final frame synchronization will be described.

However, when a long scrambling code is used in complex scrambling for an uplink dedicated physical channel (DPCH), if the frame synchronization is out of order, the long scramble code of the frame unit is observed and the frame is reconstructed. Synchronization can be confirmed, and frame synchronization can be confirmed by observing the correlation function characteristic in the present invention.

On the other hand, if short scrambling code is used, it is impossible to check frame synchronization by observing a long scrambling code used for complex scramble if the frame synchronization is out of order. The frame synchronization can be confirmed by observing the correlation function characteristic in the present invention.

As described above, when the scramble code is used in the uplink channel, a frame synchronization checking procedure of the uplink dedicated physical channel (DPCH) will be described below.

Long scrambling code or short scrambling code may be used in the uplink dedicated physical channel (DPCH).

Here, the length of the long scrambling code is the length corresponding to one frame period, and the length of the short scrambling code is the length corresponding to the symbol period constituting one frame.

However, when slot synchronization or frame synchronization is shifted in an uplink DPCH using a short scrambling code, the chip synchronization is not always shifted.

However, if chip synchronization is out of order, it is out of slot synchronization as well as frame synchronization.

On the other hand, when long scrambling code is used in an uplink DPCH, it is always chip-synchronized that the frame synchronization is out of order because the long scrambling code is repeated every frame. It implies that it is out of order.

The short scramble code is used for multi-user detection in the uplink channel. Therefore, in the uplink, the network side (UTRAN: UTMS Terrestrial Mobile Radio Access Network) uses the frame offset group information and the slot offset group information to provide chip synchronization for the uplink channel and Frame synchronization can be achieved. Subsequently, when acquiring frame synchronization, a pilot bit pattern designed according to the above-described arrangement characteristic of the frame synchronization word proposed in the present invention is used.

The frame synchronization check and acquisition is a case in which a user equipment (UE) excludes a handover moving to an adjacent cell. When the handover is performed in a 3GPP system using an asynchronous method between cells, the frame synchronization check and acquisition is performed. Accurate frame synchronization is not guaranteed according to the procedure.

The following is a procedure for confirming chip synchronization and frame synchronization of an uplink channel and obtaining final frame synchronization. FIG. 4 is a diagram illustrating an uplink frame synchronization acquisition procedure in a handover area according to the present invention.

Assume that a short scrambling code is used in an uplink channel for detecting a large number of users, and a user UE is currently moving from a serving cell to a neighboring cell. .

In this case, handover is performed, and the user side (UE) needs to be connected to a dedicated channel of a neighbor cell. To this end, the serving cell provides the frame offset group information and the slot offset group information to the neighbor cell, and the neighbor cell sets the user side (UE) and a dedicated channel using the provided information.

However, since the current 3GPP system uses an asynchronous method between cells, the synchronization information provided from the serving cell does not achieve accurate frame synchronization.

As a result, accurate frame synchronization must be achieved through an uplink frame synchronization acquisition procedure in a handover region according to the present invention.

In the uplink frame synchronization acquisition procedure according to the present invention, a neighbor cell first performs chip synchronization of a short scramble code with a UE on which handover is performed.

Subsequently, the neighbor cell tries to achieve frame synchronization using the frame offset group information and the slot offset group information provided from the serving cell. In this case, in order to obtain accurate frame synchronization, the frame synchronization word of the uplink pilot bit pattern proposed in the present invention is used.

In FIG. 4, the first network side UTRAN acquires chip synchronization of a short scrambling code by using frame offset group information and slot offset group information on a user side (UE), and performs coarse frame synchronization. ). The pseudo-frame synchronization referred to herein is a state in which frame synchronization is achieved within a specific frame error range, which is a state in which accurate frame synchronization is not achieved.

As such, the network side UTRAN is not in a state of accurate frame synchronization between adjacent cells in a chip synchronization and a coarse frame synchronization mode.

For this reason, the network side UTRAN acquires the chip synchronization and the similar frame synchronization of the uplink channel based on the frame offset group information and the slot offset group information, and then designates the pilot bits arranged in the frame synchronization words of Table 3 proposed by the present invention. Use patterns to verify correct frame sync.

That is, the network side UTRAN continuously acquires frame synchronization when frame synchronization is misaligned using the proposed pilot bit pattern in the frame synchronization mode, and then, if correct frame synchronization is obtained in the frame synchronization mode, The frame synchronization confirmation mode (frame synchronization confirmation mode) continues to check whether the frame synchronization is finally off.

However, if the chip synchronization is in the frame synchronization check mode, the chip synchronization and pseudo-frame synchronization mode are operated to match the chip synchronization, and the chip synchronization may be acquired but the frame synchronization may be misaligned. Accurate frame synchronization must be obtained.

In this case, the correlation processing apparatus for uplink frame synchronization acquisition shown in FIG. 5 is used. The correlation processing apparatus of FIG. 5 illustrates a case in which the pilot bits of the uplink channel are 8 bits.

It is assumed that the correlation processing apparatus of FIG. 5 stores demodulated symbols of at least one frame, and loads the demodulated input 15-bit length (L = 15) column sequences.

The loaded sequence is then correlated with the pilot bit pattern of the corresponding bit position number (bit #). On the receiving side equipped with the correlation processing apparatus, the bit position number (bit #) and slot number (slot #) are obtained from the correlation result. To obtain frame synchronization.

In more detail, the output of the first correlator 100 and the output of the second correlator 110 are summed (point A), and also the output of the fifth correlator 140 and the output of the sixth correlator 150. Is summed (point C). The first correlator 100, the second correlator 110, the fifth correlator 140, and the sixth correlator 150 output auto-correlation results for the demodulated column sequence, and the four correlators 100, 110, 140, and 150 are output. Each sum is summed again (point E).

Separately, the output of the third correlator 120 and the output of the fourth correlator 130 are summed (point B), and the output of the seventh correlator 160 and the output of the eighth correlator 170 are summed (point D). ). The third correlator 120, the fourth correlator 130, the seventh correlator 160, and the eighth correlator 170 output a result of performing cross correlation with the neighboring column sequence with respect to the demodulated column sequence. Each sum of these four correlators 120, 130, 160, 170 is summed again (point F). In particular, the weight assigned to the fourth correlator 130 is a cyclic shift of the code sequence C2 to the left by one, and the weight assigned to the eighth correlator 170 is to cyclically shift the code sequence C4 to the left by one. .

Then, the sum value of the autocorrelation results of the four correlators 100, 110, 140, and 150 is used to determine whether the maximum correlation result is detected, and the opposite polarity is used using the sum of the cross correlation results of the other four correlators 120, 130, 160, and 170. Check if the maximum correlation result is detected.

However, if the maximum correlation result value is not detected at the point E or the maximum correlation result value of the opposite polarity is not detected at the point F, the cyclic shift of the loaded 15-bit column sequence by one bit is performed. Repeat the process to check for frame synchronization.

If the maximum correlation result is not detected even if the 15-bit sequence is cyclically shifted 15 times by one bit, the maximum correlation result value is increased while increasing the bit # to correspond to the number of pilot bits (N _Pilot ) of the pilot bit pattern. Check if it is detected.

Finally, by repeating this series of processes, frame synchronization is obtained when the maximum correlation result is detected.

The following lists four ways to check whether frame synchronization is correct from the sum of each correlator output (at point E and point F).

The first method compares the sum of the autocorrelation results of the outputs of the four correlators (100, 110, 140, and 150) to a predetermined positive correlation threshold and then adds the positive value of the E point in the comparison result. It is regarded as the frame synchronization detection time point when it is more than the threshold.

The second method compares the sum of all four correlator outputs of the four correlators (120, 130, 160, 170) to the pre-designated negative correlation threshold, and then adds the point F to the negative result. When it is less than or equal to the correlation threshold, it is regarded as the frame synchronization detection time.

As another method, both the sum value at the point E and the sum value at the point F are used.

In other words, the third method compares the sum of all autocorrelation results with a predetermined positive correlation threshold and compares the sum of all cross correlation results with a pre-specified negative correlation threshold. In the comparison result, when the sum of points E is greater than or equal to the positive correlation threshold and the sum of points F is less than or equal to the negative correlation threshold, the frame synchronization detection time is considered.

The fourth method compares the sum of all autocorrelation results with a pre-specified positive correlation threshold, and also compares the sum of all cross-correlation results with a pre-specified negative correlation threshold. As a result of the comparison, when the sum value of the point E is equal to or greater than the positive correlation threshold or the sum of the point F is less than or equal to the negative correlation threshold, it is regarded as the frame synchronization detection time.

6 is a diagram illustrating a configuration of a correlation processing apparatus for obtaining uplink frame synchronization according to a second embodiment of the present invention.

6 is implemented using a matched filter instead of a correlator.

The first matched filter 200 performs autocorrelation with the demodulated 15-bit length (L = 15) column sequence C1 as an input and outputs the result.

The second matched filter 210 also performs the autocorrelation with the demodulated column sequence C2 as an input and outputs the result.

If there is no channel distortion, the respective outputs of the first matched filter 200 and the second matched filter 210 are summed to give the result as shown in FIG. 2A (point A).

When the output of the fifth matched filter 240 performing autocorrelation with the demodulated column sequence C3 as an input and the output of the sixth matched filter 250 performing autocorrelation with the column sequence C4 as inputs are summed ( Point C) and the same results as in FIG. 2A.

The third matched filter 220 receives the demodulated column sequence C2 as an input and cross-correlates the weight with respect to the column sequence C1 designated thereto, and outputs the result.

The fourth matched filter 230 receives the demodulated column sequence C1 as an input and cross-correlates the weight with respect to the column sequence C2 designated therein, and outputs the result. At this time, the weight specified in the fourth matching filter 230 is a cyclic shift of the column sequence C2 to the left by one.

If there is no channel distortion, the outputs of the third and fourth matched filters 220 and 230 are summed to give the result as shown in FIG. 2B (point B).

The output of the seventh matching filter 260 which performs cross correlation with the weight of the column sequence C3 with the demodulated column sequence C4 as an input, and the column sequence C4 is cyclically shifted left by 1 with the column sequence C3 as an input. The sum of the outputs of the eighth matched filter 270 that performs cross correlation with the weights (point D) also shows a result as shown in FIG. 2B.

The sum of the autocorrelation results by the first matched filter 200 and the second matched filter 210 at the point A, and the fifth matched filter 240 and the sixth matched filter 250 at the point C The sum of the autocorrelation results is used for frame synchronization acquisition and confirmation by adding up again and comparing it to a predetermined positive correlation threshold.

In addition, the sum value of the cross-correlation result by the third matching filter 220 and the fourth matching filter 230 at the point B, and the seventh matching filter 260 and the eighth matching filter 270 at the point D The sum of the cross correlation results is then summed again and compared with a previously specified negative correlation threshold to be used for frame synchronization acquisition and confirmation.

Separately, by summing all the correlation results of the matched filter so far (points E and F) and using the result, it is also possible to double check during frame synchronization acquisition and confirmation.

As described above, according to the frame synchronization acquisition method of the present invention, a 3GPP system using an asynchronous method between cells ensures accurate frame synchronization for a UE (UE) in which handover is in progress.

That is, according to the correlation result using the pilot bit pattern of the present invention in the uplink channel, fast and accurate frame synchronization acquisition is guaranteed even in the handover region.

Claims (2)

In acquiring frame synchronization for an uplink channel in the neighbor cell when handover is performed between a serving cell and a neighboring cell for an arbitrary user UE, Obtaining chip synchronization for the uplink channel; Acquiring a similar frame synchronization having a predetermined frame error using various offset group information on the UE as the chip synchronization is obtained; And obtaining final frame synchronization using the input pilot bit pattern as the chip synchronization and the similar frame synchronization are obtained. The method according to claim 1, wherein the pilot bit pattern used in acquiring the final frame synchronization has a positive maximum autocorrelation value detected at a start delay time of a correlation period for each received frame. A negative maximum cross-correlation value is detected at an intermediate delay time of a correlation period for a frame.