KR100310417B1 - Bit-Reverse Address Generators in Fast Fourier Transforms - Google Patents

Abstract

The present invention relates to a bit-reversal address generator of a fast Fourier transform apparatus, wherein only a portion of the data output from the auxiliary register and the index register whose input result changes is inputted to the reverse carry forward adder so that the operation is performed in the reverse carry low adder. The purpose is to greatly speed up. The bit-reverse address generator of the fast Fourier transform apparatus according to the present invention comprises an auxiliary register, an index register, a pointer detector, first and second bypass portions, and a reverse carry transfer adder. The auxiliary register stores the first address of the data block needed to perform fast Fourier transforms. The index register stores an index value including the point information of the fast Fourier transform. The point detector detects point information of an index value stored in an index register and generates a bypass control signal. The first bypass unit receives the address stored in the auxiliary register and the bypass control signal, and outputs only an address having a size determined by the value of the bypass control signal among the addresses. The second bypass unit receives the index value and the bypass control signal stored in the index register, and outputs only an index value having a size determined by the value of the bypass control signal among the index values. The reverse carry transfer adder performs a reverse carry transfer addition on an address of a predetermined size output from the first bypass unit and an index value of a predetermined size output from the second bypass unit to feed back to the auxiliary register.

Description

Bit-Reverse Address Generators in Fast Fourier Inverters

The present invention relates to a bit-reverse address generator, and more particularly to a bit-reverse address generator of a fast Fourier transform device.

Fourier Transform is a very important tool often used in digital signal processing devices. The purpose of the Fourier transform is to transform the information from the time domain to the frequency domain. The Inverse Fourier Transform, on the other hand, is a transformation from the frequency domain to the time domain. A fast Fourier transform is a well-known computer for efficient computation.

One way to reduce the computational speed of fast Fourier transforms is the bit-reversed addressing mode. This bit-reverse addressing mode reverses the arrangement order of the bit strings of addresses for retrieving data necessary for the operation. That is, the order of going from the upper bit to the lower bit is changed from the lower bit to the upper bit.

The bit-reverse addressing mode is part of the indirect addressing performed through the auxiliary registers and the computing device. In this mode, the index value stored in the index register is added to or subtracted from the auxiliary register. In addition, the carry bits are not forwarded and go in the opposite direction, resulting in a mix of addresses.

This bit-reverse addressing mode is summarized in FIG.

As can be seen in Figure 1, converting a bit pattern specified by a series of indexes into a bit-reversal pattern, the original indexes are inverted from one another to become the order represented by the bit-reverse indexes in the above table. Since the order of the bit-reverse index is the order of fetching data in the fast Fourier transform, the bit-reverse addressing mode is used to reduce the operation speed in the fast Fourier transform.

2 is a block diagram of a bit-reverse address generator for performing such a bit-reverse addressing mode.

In the initial state, the auxiliary register 21, denoted AR, stores the first address of the data block needed to perform fast Fourier transform. The index register 22 denoted by INDX stores information on a point value of a fast Fourier transform to be performed. In the case of an 8-point fast Fourier transform, a value of "0000 0000 0000 1000" is stored in the index register 22, and the address of the auxiliary register 21 is also 16 bits.

The values stored in the auxiliary register 21 and the index register 22 are inputted to the reverse carry propagation adder 23 and added. The reverse carry transfer adder 23 adds two input values, but does not transfer the carry resulting from the addition to the front normally but in the opposite direction.

FIG. 3 illustrates the results of the operation of the bit-reverse address generator of FIG. 2. This operation is an example in which an address of "0000 0010 0000 0000" is stored in the auxiliary register 21, and a value (8 points) of "0000 0000 0000 1000" is stored in the index register 22. As shown in FIG. .

In each of the addition results shown in Figure 3 it can be seen that the carry in the reverse direction. In particular, it can be seen that the range of values changing at each addition step is limited to the lower 4 bits. This is because the first address value of the address from which data is to be fetched is fixed, and the value of the index added to this address is also fixed to eight points. If it is 128 points, the addition result will change in the lower 8 bits.

From this point of view, the backward carry transfer adder 23 does not need to add both the value of the auxiliary register 21 and the value of the index register 22, receives and adds only the portion where the addition result changes, and adds the result again. Transfer to the auxiliary register 21 can increase the addition speed.

Therefore, an object of the present invention is to improve the operation speed in the reverse carry transfer adder by allowing only the portion of the data output from the auxiliary register and the index register to be changed to be input to the reverse carry transfer adder.

The present invention for this purpose comprises an auxiliary register, an index register, a point detector, first and second bypass sections, and a reverse carry transfer adder.

The auxiliary register stores the first address of the data block needed to perform fast Fourier transforms.

The index register stores an index value including the point information of the fast Fourier transform.

The point detector detects point information of an index value stored in an index register and generates a bypass control signal.

The first bypass unit receives the address stored in the auxiliary register and the bypass control signal, and outputs only an address having a size determined by the value of the bypass control signal among the addresses.

The second bypass unit receives the index value and the bypass control signal stored in the index register, and outputs only an index value having a size determined by the value of the bypass control signal among the index values.

The reverse carry transfer adder adds the reverse size of the address of the predetermined size output from the first bypass unit and the index value of the predetermined size output from the second bypass unit to feed back to the auxiliary register.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows the bit-reverse addressing mode of fast Fourier transform.

2 is a block diagram of a bit-reverse address generator for performing a bit-reverse addressing mode.

FIG. 3 is a diagram illustrating a result of an operation of the bit-reverse address generator of FIG. 2. FIG.

4 is a block diagram illustrating a bit-reverse address generator in accordance with the present invention.

Explanation of symbols on the main parts of the drawings

21, 41: auxiliary register 22, 43: index register

23, 46: reverse carry transfer adder 42, 44: bypass portion

45: point detector 47: bypass control signal

A preferred embodiment of the bit-reverse address generator according to the present invention will be described with reference to FIG. 4 is a block diagram illustrating a bit-reverse address generator according to the present invention.

As shown in Fig. 4, in the initial state, the auxiliary register 41 stores the first address of the data block necessary to perform fast Fourier transform. The index register 43 stores information of point values of fast Fourier transforms to be performed. Taking the data of FIG. 3 as an example, a value of "0000 0000 0000 1000" is stored in the index register 43, and the address stored in the auxiliary register 41 is "0000 0010 0000 0000".

The address of the auxiliary register 41 is input to the reverse carry transfer adder 46 through the first bypass section 42, and the value of the index register 43 is also passed through the second bypass section 44 through the reverse carry section. It is input to the adder 46.

The first and second bypass units 42 and 44 transmit only a part of the values output from the auxiliary register 41 and the index register 43 to the reverse carry transfer adder 46, respectively. In this case, a value transmitted from each bypass unit 42 or 44 to the reverse carry transfer adder 46 is determined by the bypass control signal 47 output from the point detector 45.

The point detector 45 receives a point value output from the index register 43, detects a point value currently output from the index register 43, and controls the bypass unit 42 and 44 according to the detected point value. To control. In the case of 8 points, only the lower 4 bits are output from each of the bypass sections 42 and 44. This is because, as shown in Fig. 3, in the case of 8 points, the size of the addition result is limited to the lower 4 bits.

In this way, the reverse carry transfer adder 46 that receives the address and index value of the lower four bits from each of the bypass units 42 and 44 only needs to perform addition for four bits, and the addition result is supplemented again. Feedback to the register 41 allows the addition of the next step to be performed. At this time, a plurality of arithmetic units constituting the reverse carry transfer adder are only partially enabled by the bypass control signal to perform only arithmetic operations for 4 bits. If the number of bits to be operated is increased, the number of enabled calculation units is also increased, which is controlled by the bypass control signal as described above.

The backward carry transfer adder 46 adds the two input values, and transfers the carry generated according to the addition result in the backward direction instead of normally forwarding.

This reverse carry transfer adder 46 also requires a bypass control signal 47 provided at the point detector 45, which is coupled to the auxiliary register 41 and the index register 43. Since the maximum size of the stored address and the index value can be added, when only the lower 4 bits are added as in the case described above, only the operation part for adding the lower 4 bits is enabled, and the remaining operation parts are disabled. Because you have to.

As such, the present invention only needs to calculate a smaller amount of data by detecting a point value in the bit-reverse address generator required to perform the fast Fourier transform and adding only the address and index values of the portion where the addition result changes. The computation speed is greatly improved and faster Fourier transforms can be made.

Claims (3)

In the bit-reverse address generator of a fast Fourier transform, An auxiliary register for storing an initial address of a data block required to perform fast Fourier transform; An index register for storing an index value including point information of a fast Fourier transform; A point detector for detecting point information of an index value stored in the index register and generating a bypass control signal; A first bypass unit which receives the address stored in the auxiliary register and the bypass control signal, and outputs only an address having a size determined according to a value of the bypass control signal among the addresses; A second bypass unit configured to receive an index value stored in the index register and the bypass control signal, and output only an index value having a size determined by a value of the bypass control signal among the index values; A backward carry transfer addition is performed on the address of the predetermined size output from the first bypass unit and the index value of the predetermined size output from the second bypass unit, and the result is fed back to the auxiliary register. A bit-reverse address generator of a fast Fourier transform device comprising a carry transfer adder. The fast Fourier transform of claim 1, wherein the backward carry transfer adder comprises a plurality of calculation units capable of calculating a maximum size of the address stored in the auxiliary register and a maximum value of an index value stored in the index register. Bit-reverse address generator of the device. The bit-reverse address generator of the fast Fourier transform apparatus according to claim 2, wherein the plurality of operation units of the backward carry transfer adder are configured to perform arithmetic operations in whole or in part by the bypass control signal. .