KR100309469B1 - Y-address redundancy circuit for memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory address address circuit of a memory, wherein the column address is generated by controlling a column address generated in an external chipset for controlling the memory such that an upper wire address is not selected for mounting and using the memory as a conventional half product. Due to this, it is impossible to remedy defects of cells existing in the memory region fixedly selected, thereby reducing the manufacturing efficiency of the half article. Accordingly, the present invention has been devised to solve the above-mentioned conventional problems, and when a redundancy cell is not possible, the wye address of a memory area including only a bit line without a bad cell is determined by the w address fuse information having an X address. There is an effect of improving the production efficiency of the half product by using only to bail out the defective product into the half product.

Description

Y-ADDRESS REDUNDANCY CIRCUIT FOR MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a circuit for address relief of a memory of a memory. In particular, when a memory using a redundancy cell cannot be repaired in a memory of the memory of the address of a memory, a defective product is cut by using a portion of the wire address by cutting the fuse. Half Density Chip (hereinafter referred to as "half product") relates to a memory address addressing circuit of a memory made available.

FIG. 1 is a block diagram showing a structure of a memory to which a conventional Y address rescue circuit is applied. As shown in FIG. 1, a plurality of cells storing data by a plurality of word lines and bit line pairs is shown. A memory array unit (10) comprising a plurality of sense amplifiers for sensing data of the bit line pair; A WY address buffer 20 for receiving and buffering column addresses CA0 to CA8; A Y-predecoder 30 for pre-decoding the column addresses CA0hh to CA8h output from the Y-address buffer 20; Decoding the Wy addresses (AY0h <0: 7>, AY3h <0: 7>, AY6h <0: 7>) pre-decoded by the Wy-predecoder 30 to enable a sense amplifier connected to the corresponding bit line pair. A Y decoder 40; A comparison and fuse unit 50 for determining whether a bit line is defective and cutting a fuse corresponding to a bad address; The bit line corresponding to the bad address when the corresponding bad address is applied by the fuse in the comparison unit 50 and the fuse unit 50 is configured with a redundancy decoder 60 for disabling and enabling the redundancy bit line.

In addition, the Y-predecoder 30 includes a plurality of inverters I1, I2, and I3 for inverting the column addresses CA6h, CA7h, and CA8h, respectively, as shown in FIG. A plurality of inverters (I11) (I12) (I13) for respectively inverting output signals of the plurality of inverters (I1) (I2) (I3); A negative gate NAND1 that receives an output signal of the inverters I1, I2, and I3 and performs a multiplication operation; A negative gate NAND2 that receives an output signal of the inverters I11, I2, and I3 and performs a multiplication; A negative gate NAND3 that receives an output signal of the inverters I1, I12, and I3 and performs a multiplication operation; A negative gate NAND4 that receives an output signal of the inverters I11, I12, and I3 and performs a multiplication operation; A negative gate NAND5 that receives an output signal of the inverters I1, I2, and I13 and performs a multiplication operation; A negative gate NAND6 which receives an output signal of the inverters I11, I2, and I13 and performs a multiplication operation; A negative gate NAND7 that receives an output signal of the inverters I1, I12, and I13 and performs a multiplication operation; A negative gate NAND8 which receives an output signal of the inverters I11, I12, and I13 and performs a multiplication operation; A plurality of inverters I21 to I28 for inverting and outputting the output signals of the multiple gates NAND1 to NAND8, respectively, will be described in detail.

The WY address buffer 20 that receives the column addresses CA0 to CA8 buffers and outputs the W address buffer 20, and the WY predecoder 30 that receives the column addresses CA0hh to CA8h output from the W address buffer 20. Pre-decodes and outputs the column addresses CA0hh to CA2h (CAh3h to CA5h) (CAh6h to CA8h).

Here, in the case of predecoding the column addresses CAh6h to CA8h in the Y-predecoder 30, the inverters I1, I2 and I3 in the Y-predecoder 30 are each column addresses CA6h and CA7h. ) CA8h is inverted and outputted, and the plurality of inverters I11, I12, and I13 that have received the output signals of the plurality of inverters I1, I2, and I3 are inverted and outputted.

The output signals of the inverters I1, I2, and I3, the output signals of the inverters I11, I2, and I3, the inverters I1, I12, and I3, and the inverter I11, respectively. Output signal of (I12) (I3), output signal of the inverter (I1) (I2) (I13), output signal of the inverter (I11) (I2) (I13), the inverter (I1) (I12) (I13) ), And a plurality of negative gates NAND1 to NAND8 that have received the output signals of the inverters I11, I12, and I13 perform a multiplication operation on the output, and the plurality of negative gates NAND1 to NAND8. The output signals of are inverted by the plurality of inverters I21 to I28, respectively, and output to the Y address AY6h <0: 7>.

The Y predecoder 30 also pre-decodes the column addresses CA0hh to CA2h (CAh3h to CA5h) to output the Y addresses (AY0h <0: 7> and AY3h <0: 7>).

In addition, the Y decoder 40 receiving the pre-decoded Y addresses (AY0h <0: 7>, AY3h <0: 7>, AY6h <0: 7>) from the Y-free decoder 30 decodes them and stores the memory. The sense amplifier connected to the corresponding bit line pair in the array unit 10 is enabled to store or output data in the corresponding cell.

In this case, it is determined whether the bit line is defective and whether the fuse corresponding to the defective address is cut off or whether the fuse is disconnected from the fuse unit 50. After blocking the output of the signal corresponding to the bad address, the redundancy decoder 60 enables the sense amplifier connected to the relief bit line pair to store or output data through the rescue cell.

If there are more defective bit lines than the relief bit line due to the existence of the relief Y address and the bit line limited to the memory block, the memory product is classified as defective and finally cannot be used.

Therefore, as the memory becomes more integrated, the probability of the failure increases, and when a failure occurs beyond the limited relief Y address, the capacity of the defective memory is reduced to half and used as a half product.

As described above, by controlling a column address generated in an external chipset that controls the memory so that a high-order Y address is not selected for mounting and using the memory as a conventional half product, the memory device may exist in a memory area fixedly selected by the column address. There was a problem that the manufacturing efficiency of the half article is reduced because the relief of the defect of the cell is impossible.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and when the remedy using redundancy cells is impossible, only a memory area consisting of bit lines without defective cells is used to remedy defective products in half. The purpose is to provide a Y address remedy circuit.

1 is a block diagram showing a structure of a memory to which a conventional Y address rescue circuit is applied.

FIG. 2 is a block diagram showing the configuration of the Y-predecoder in FIG.

3 is a block diagram showing the structure of a memory to which the present invention is applied;

FIG. 4 is a block diagram showing the configuration of the Y-free decoder in FIG. 3. FIG.

FIG. 5 is a block diagram illustrating a configuration of a half product control unit in FIG. 3. FIG.

6 is an operation timing diagram of each part of FIG. 3.

FIG. 7 illustrates a region of a memory array when applying a half product in FIG. 3. FIG.

*** Description of the symbols for the main parts of the drawings ***

100: memory array unit 110: Y address buffer

120: half product control unit 130: Y predecoder

131: selection output unit 140: Y decoder

150: comparison and fuse 160: redundancy decoder

NAND1 to NAND10: negative gates PM1, PM11, PM12: PMOS transistor

S1: transfer gates NM11 to NM18, NM21 to NM28: NMOS transistors

FUSEH0 to FUSEH7, FUSEJ0 to FUSEJ7: Fuse

I1 to I3, I11 to I13, I21 to I28, I31 to I35: inverter

According to an aspect of the present invention, there is provided a memory array unit including a plurality of cells for storing data and a sense amplifier for sensing the data; A Y address buffer which receives the column address and buffers it; A half product control unit for outputting address information on whether the half product is to be rescued and the area to be used when the half product is to be repaired in a memory area corresponding to a signal obtained by decoding the upper 3 bit X address; A Y-predecoder for selectively pre-decoding h column addresses output from the Y-address buffer by memory area address information of the half product control unit; A W decoder to decode a W address pre-decoded by the W pre decoder and to enable a sense amplifier connected to a corresponding bit line pair; A comparison and fuse unit which determines whether a bit line is defective and cuts a fuse corresponding to a defective address; The bit line corresponding to the bad address when the corresponding bad address is applied by the comparison and fuse in the fuse unit may be configured as a wireless redundancy decoder for disabling and enabling the redundancy bit line.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

3 is a block diagram illustrating a structure of a memory to which the present invention is applied. As shown in FIG. 3, a plurality of cells storing data by a plurality of word lines and bit line pairs, and a plurality of cells sensing data of the bit line pairs are illustrated. A memory array unit 100 configured as a sense amplifier; A Y address buffer 110 for receiving and buffering the column addresses CA0 to CA8; and memory area address information selected according to whether or not a fuse is cut by the signals MS0 to MS7 decoded from the upper 3-bit X address. A half product control unit 120 for outputting a control signal YHIT YRUB; In pre-decoding the column addresses CA0hh to CA8h output from the Y address buffer 110, the most significant column address CA8h is selectively pre-set by the control signal YHIT YRUB of the half product control unit 120. A Wy predecoder 130 for decoding; Decoding the Wy addresses (AY0h <0: 7>, AY3h <0: 7>, AY6h <0: 7>) pre-decoded by the Y-free decoder 130 to enable a sense amplifier connected to the corresponding bit line pair. A Y decoder 140; A comparison and fuse unit 150 for determining whether a bit line is defective and cutting a fuse corresponding to a bad address; The redundancy decoder 160 disables the bit line corresponding to the bad address and enables the redundancy bit line when the corresponding bad address is applied by the fuse in the comparison and fuse unit 150.

In addition, the Y-free decoder 130 includes a plurality of inverters I1 and I2 for inverting the column addresses CA6h and CA7h, respectively, as shown in FIG. A selection output unit (131) for inverting and outputting the column address (CA8h) by a control signal (YHIT) YRUB; A plurality of inverters (I11) (I12) (I13) for respectively inverting output signals of the plurality of inverters (I1) (I2) and the selective output unit (131); A negative gate NAND1 that receives the output signals of the inverters I1 and I2 and the selection output unit 131 and performs arithmetic operations; A negative gate NAND2 that receives the output signals of the inverters I11 and I2 and the selection output unit 131 and performs arithmetic operation; A negative gate NAND3 that receives the output signals of the inverters I1 and 12 and the selection output unit 131 and performs arithmetic operations on the output signals; A negative gate NAND4 that receives the output signals of the inverters I11, I12 and the selection output unit 131, and performs arithmetic operations; A negative gate NAND5 that receives an output signal of the inverters I1, I2, and I13 and performs a multiplication operation; A negative gate NAND6 which receives an output signal of the inverters I11, I2, and I13 and performs a multiplication operation; A negative gate NAND7 that receives an output signal of the inverters I1, I12, and I13 and performs a multiplication operation; A negative gate NAND8 which receives an output signal of the inverters I11, I12, and I13 and performs a multiplication operation; A plurality of inverters I21 to I28 which invert and output the output signals of the plurality of gates NAND1 to NAND8, respectively.

The select output unit 131 includes: a negative gate NAND9 for receiving a control signal YHIT YRUB and performing a multiplication; An inverter I3 for inverting the control signal YHIT; A transmission gate S1 for transferring the highest column address CA8h of the input terminal to the output terminal by the control signal YHIT and the output signal of the inverter I3 applied to the inverting terminal and the non-inverting terminal; A PMOS transistor PM1 which is electrically controlled by an output signal of the inverter I3 and outputs a power supply voltage VCC to an output terminal of the transfer gate S1; It consists of an AND gate NAND10 that receives the output signals of the AND gate NAND9 and the transfer gate S1 and performs an AND operation.

In addition, the half product control unit 120 is electrically controlled by the pre-decoding bar signal PREB as shown in FIG. 5 to check whether the source voltage VCC of the source is normally operated in the corresponding memory area through the node N1. A PMOS transistor PM11 supplied to one side of the fuses FUSEH0 to FUSEH7 for selecting the PMOS transistors; A plurality of NMOS transistors NM11 to NM18 which are electrically controlled by the signals MS0 to MS7 that decode the upper X address and ground the other side of the fuses FUSEH0 to FUSEH7 connected to respective drains through a common grounded source. )Wow; An inverter (I31) for inverting and outputting the voltage of the node (N1); An inverter (I32) for inverting the output signal of the inverter (I31) and outputting it as a control signal (YHIT); An inverter (I33) for inverting an output signal of the inverter (I31) and feeding it back to an input terminal of the inverter (I31); Controlled by the pre-decoding bar signal PREB to supply the source voltage VCC of the source to one side of the fuse FUSEJ0 to FUSEJ7 which selects an upper region and a lower region to be used among the corresponding memory regions through the node N2. A PMOS transistor PM12; An NMOS transistor NM30 for conducting control by the control signal YHIT and outputting a source ground voltage to a drain; A source is commonly connected to the drain of the NMOS transistor NM30 and is electrically controlled by the signals MS0 to MS7 decoded for the upper X address, so that the other side of the fuses FUSEJ0 to FUSEJ7 connected to the drain are common to the source. A plurality of NMOS transistors NM21 to NM28 connected to the drains of the connected NMOS transistor NM30; An inverter (I34) for inverting and outputting the voltage of the node (N2); An inverter I35 for inverting the output signal of the inverter I34 and outputting the inverted signal as a control signal YRUB; An inverter I35 for inverting and inverting the output signal of the inverter I34 will be described in detail with reference to FIGS. 6 and 7 attached to the operation process according to the present invention.

First, the process of checking for the presence of a bad cell is to scan the X address and the Y address from the lower bit to the upper bit to test the normal operation of a plurality of cells in the memory array unit 100 to store an abnormal cell address. In addition, the memory region including the stored abnormal cells is classified using the upper 3 bits of the X address as shown in FIG. 7, and the upper region and the lower region of the memory region are separated.

The presence or absence of abnormal cells in the corresponding memory area is selected according to whether the fuses FUSEH0 to FUSEH7 are shorted, and whether the area where the abnormal cells are located is an upper region or a lower region is a short circuit of the fuses FUSEJ0-FUSEJ7. Choose whether or not.

When the Y address buffer 110 receives the first column addresses CA0 to CA8 and buffers the first address, the Y predecoder 130 receives the column addresses CA0hh to CA8h output from the Y address buffer 110. 6 pre-decodes the column addresses CA0hh to CA8h according to the pre-decoding bar signal PREB applied as shown in FIG.

In the case of using the memory as a normal memory, if the signal MS1 of the decoded signals MS0 to MS7 is applied at high potential as shown in FIG. 6B, the pre-decoded bar signal PREB is applied to the gate. As the MOS transistors PM11 and PM12 are turned on and the NMOS transistors NM12 and NM22 that receive the high potential signal MS1 to the gate are turned on, the voltage of the first node N1 is abnormal to the bit line. If not, the fuse FUSEH1 is in a connected state, and thus becomes low potential. In the inverters I31 and I32 which have reversed it sequentially, the control signal YHIT is a section in which the signal MS1 has a high potential as shown in FIG. And the inverter I34 and I35 sequentially inverting the high potential output signal of the turned-on PMOS transistor PM12 as the NMOS transistor NM30 is turned off. The high potential is output and maintained by (I36).

In addition, the negative gate NAND9 and the inverter I3 in the selection output unit 131 receiving the low potential control signal YHIT are inverted to output high potentials, and the inverting terminal and the non-inverting terminal are respectively inverted. The transfer gate S1 receiving the low potential control signal YHIT and the output signal of the high potential inverter I3 is enabled to output the column address hCA8h as shown in FIG.

The inverted gate NAND10 receiving the high potential output signal of the inverted gate NAND9 inverts and outputs the column address hCA8h input through the transfer gate S1.

Here, the Y-predecoder 130 inverts the column address hCA8h from the selection output unit 131 and outputs the column address CA0hh to CA2h, CAh3h to CA5h, and CAh6h to CA6h. Predecoding is then performed and output to the Y address (AY0h <0: 7>, AY3h <0: 7>, AY6h <0: 7>).

Then, the Y decoder 140 receiving the pre-decoded Y addresses (AY0h <0: 7>, AY3h <0: 7>, AY6h <0: 7>) from the Y predecoder 130 decodes the memory and decodes them. The sense amplifier connected to the corresponding bit line pair in the array unit 100 is enabled to store or output data in the corresponding cell.

However, in the case of using a defective product as a half product, in order to selectively use the memory area as shown in FIG. 7, the fuses FUSEH0 to FUSEH7 are cut as shown in Table 1 below.

Therefore, since the fuses FUSEH0 to FUSEH7 are shorted, the voltage of the first node N1 becomes high potential by the PMOS transistor PM11 turned on by the pre-decoding bar signal PREB. The half product control unit 120 has a high potential as shown in FIG. 6D by the inverters I31 and I32 and the inverter I33 which sequentially reverse the voltage of the node N1 to the control signal YHIT. Keep it after printing.

In addition, if the location of the faulty cell in the corresponding memory area is an upper area or a lower area to be used, the fuse of the corresponding area among the fuses FUSEJ0 to FUSEJ7 is cut. If the upper area is the fuse, the fuses FUSEJ0 to FUSEJ7 are used. Do not cut the fuse in the corresponding area.

Here, when the fuse (FUSEJ0, FUSEJ1, FUSEJ3, FUSEJ4, FUSEJ5) is cut and output the control signal (YRUE) at high potential, as shown in FIG. 7, as shown in Table 2 in the WY predecoder 130 The low level is output at the address AY6h <4: 6> to use only the lower area.

That is, since the NMOS transistor NM30 receiving the high potential control signal YHIT is turned on and the NMOS transistor NM22 is turned on by the signal MS1, the fuse FUSEJ1 is shorted. Since the voltage of the node N2 becomes high potential by the PMOS transistor PM12, the half product control unit 120 inverts the control signal YRUB by inverting the high potential of the node N2 sequentially. After outputting at high potential by I35 and inverter I36, it is maintained.

The negative gate NAND9 and the inverter I3 in the selection output unit 131 which have received the high potential control signal YHIT YRUB output low potentials, respectively, and the negative gate NAND9. Since the negative gate NAND10 receiving the low potential output of the N + 10 outputs a high potential irrespective of other inputs, the Y-predecoder 130 performs the column addresses CA0hh to CA2h and CAh3h of the selection output unit 131. Pre-decoded to ~ CA5h) h with the Y addresses (AY0h <0: 7>, AY3h <0: 7>) as before.

However, for the column addresses CAh6h to CA8h, the Y-predecoder 130 determines that only the highest column address CA8h is applied at a high potential, and thus the Y-address AY6h <4: 7> is determined as the column address CA6h. Regardless of CA7h, a low potential is output, and a predecoded output is performed for the Y address (AY6h <0: 3>).

Accordingly, the Y decoder 140 receiving the pre-decoded Y addresses (AY0h <0: 7>, AY3h <0: 7>, AY6h <0: 3>) from the Y predecoder 130 decodes them and stores the memory. The sense amplifier connected to the corresponding bit line pair in the array unit 100 is enabled to store or output data in the corresponding cell.

In addition, when the fuses FUSEJ2, FUSEJ6, and FUSEJ7 are not cut and the control signal YRUE is output at a low potential, the Y address of the predecoder 130 is determined as shown in Table 2 in the Y address (AY6h <0: 7>). ) Outputs a low potential to use only the upper region.

That is, the NMOS transistor NM30 receiving the high potential control signal YHIT is turned on and is applied through the PMOS transistor PM12 turned on by receiving the pre-decoding bar signal PREB. The power supply voltage is grounded through the NMOS transistor NM22 turned on by the signal MS1, the uncut fuse FUSEJ2, and the NMOS transistor NM30, and the voltage of the node N2 becomes a high potential. The control signal YRUB maintains the low potential after outputting the low potential by the inverters I34 and I35 and the inverter I36 which sequentially reverse the low potential of the node N2.

The inverter I3 receiving the high potential control signal YHIT outputs a low potential, respectively, and outputs a low potential output signal of the inverter I3 and a high potential control signal YHIT, respectively. And the transfer gate S1 applied to the inverting terminal are disabled, but the PMOS transistor PM1 applied to the gate of the low potential output signal of the inverter I3 is turned to the negative gate NAND10 as the PMOS transistor PM1 is turned on. Output the above

The negative gate NAND9, which receives the high potential control signal YHIT and the low potential control signal YRUB, performs a multiplication operation on the negative gate NAND9, and outputs a high potential. The negative gate NAND10 receiving the high potential output inverts the high potential applied through the PMOS transistor PM1 and outputs the low potential.

Therefore, the Y-predecoder 130 has the same Y-address (AY0h <0: 7>, AY3h <0 :) for the column addresses CA0hh to CA2h and CAh3h to CA5h of the selection output unit 131. 7>), the predecoder is outputted, but for the column addresses CAh6h to CA8h, the Y-predecoder 130 determines that only the highest column address CA8h is applied at a low potential. ?) Is output regardless of the column addresses CA6h and CA7h, and is predecoded and output to the wye addresses AY6h <4: 7>.

Accordingly, the Y decoder 140 receiving the pre-decoded Y addresses (AY0h <0: 7>, AY3h <0: 7>, AY6h <4: 7>) from the Y predecoder 130 decodes the Y decoder. The sense amplifier connected to the corresponding bit line pair in the memory array unit 100 is enabled to store or output data in the corresponding cell.

As described in detail above, in the present invention, when the repair using the redundancy cell is impossible, the defective product is used as a half product by using only the Y address of the memory area including only the bit line without the defective cell by the Y address fuse information having the X address. Thereby, there exists an effect which improved the manufacturing efficiency of a half article.

Claims (4)

A memory array unit including a plurality of cells storing data and a sense amplifier sensing the data; A Y address buffer which receives the column address and buffers it; A half product control unit for outputting address information on whether the half product is to be rescued and the area to be used when the half product is to be repaired in a memory area corresponding to a signal obtained by decoding the upper 3 bit X address; A Y-predecoder for selectively pre-decoding h column addresses output from the Y-address buffer by memory area address information of the half product control unit; A W decoder to decode a W address pre-decoded by the W pre decoder and to enable a sense amplifier connected to a corresponding bit line pair; A comparison and fuse unit which determines whether a bit line is defective and cuts a fuse corresponding to a defective address; And a bit redundancy decoder for disabling the bit line corresponding to the bad address when the corresponding bad address is applied by the fuse in the comparison unit and the fuse unit. 2. The apparatus of claim 1, wherein the Wy-free decoder comprises: first and second inverters for inverting first and second column addresses, respectively; A selection output unit for inverting and outputting the third column address according to the first and second control signals of the half product control unit; Third, fourth, and fifth inverters which invert the output signals of the first, second inverters and the selective output unit, respectively; A first negative gate configured to receive an output signal of the first and second inverters and the selective output unit, and perform a multiplication operation; A second negative gate that receives the output signals of the second and third inverters and the selective output unit, and performs a multiplication; A third negative gate configured to receive an output signal of the first and fourth inverters and the selective output unit, and perform a multiplication operation; A fourth negative gate configured to receive an output signal of the third and fourth inverters and the selective output unit, and perform a multiplication operation; A fifth negative gate configured to receive an output signal of the first, second, and fifth inverters and perform a multiplication; A sixth integer gate that receives an output signal of the second, third, and fifth inverters and performs an arithmetic operation; A seventh integer gate that receives an output signal of the first, fourth, and fifth inverters and performs an arithmetic operation; An eighth integer gate which receives an output signal of the third, fourth, and fifth inverters and performs an arithmetic operation; And a plurality of inverters for inverting and outputting the output signals of the first to eighth gates, respectively. 3. The gate driving circuit of claim 2, wherein the selection output unit comprises: a first negative gate which receives a first and second control signal of a half product control unit and performs a multiplication; An inverter for inverting the first control signal; A transmission gate transferring the highest column address of an input terminal to an output terminal by the first control signal applied to the inverting terminal and the non-inverting terminal and the output signal of the inverter; A PMOS transistor configured to be electrically controlled by an output signal of the inverter to output a power supply voltage of a source to an output terminal of the transfer gate; And a second AND gate which receives an output signal of the first AND gate and a transfer gate, and performs an AND operation on the output signals. The half product control unit of claim 1, wherein the half product control unit is electrically controlled by a pre-decoding bar signal to supply the source voltage of the source to one side of the first through eighth fuses to select whether the memory area is normally operated through the first node. A first PMOS transistor; First to eighth NMOS transistors electrically controlled by a signal decoded by an upper X address to ground the other side of the first to eighth fuses connected to respective drains through a common grounded source; A first inverter for inverting and outputting the voltage of the first node; A second inverter for inverting the output signal of the first inverter and outputting the first control signal; A third inverter for inverting the output signal of the first inverter and feeding back to the input terminal of the first inverter; A second PMOS transistor connected to the pre-decoding bar signal to supply a power supply voltage of a source to one side of the ninth to sixteenth fuses to select an upper region and a lower region of a corresponding memory region through a second node; ; A ninth NMOS transistor electrically conductively controlled by the first control signal to output a ground voltage of the source to a drain; A tenth through seventeenth NMOS transistors connected to drains of the ninth NMOS transistors commonly connected to a source, the other side of each of the ninth to sixteenth fuses connected to a drain by conducting control by a signal obtained by decoding the upper X address; Wow; A fourth inverter for inverting and outputting the voltage of the second node; A fifth inverter for inverting the output signal of the fourth inverter and outputting the second control signal; And a sixth inverter configured to invert the output signal of the fourth inverter and feed it back to the input terminal of the fourth inverter.