KR100308395B1 - Structure of semiconductor package - Google Patents

Structure of semiconductor package Download PDF

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Publication number
KR100308395B1
KR100308395B1 KR1019960074119A KR19960074119A KR100308395B1 KR 100308395 B1 KR100308395 B1 KR 100308395B1 KR 1019960074119 A KR1019960074119 A KR 1019960074119A KR 19960074119 A KR19960074119 A KR 19960074119A KR 100308395 B1 KR100308395 B1 KR 100308395B1
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KR
South Korea
Prior art keywords
heat sink
semiconductor chip
semiconductor package
outside
insulating layer
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KR1019960074119A
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Korean (ko)
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KR19980054918A (en
Inventor
윤주훈
강대병
Original Assignee
마이클 디. 오브라이언
앰코 테크놀로지 코리아 주식회사
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Priority to KR1019960074119A priority Critical patent/KR100308395B1/en
Publication of KR19980054918A publication Critical patent/KR19980054918A/en
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Publication of KR100308395B1 publication Critical patent/KR100308395B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE: A structure of a semiconductor package is provided to improve capacity of the semiconductor package including a heat-sink by preventing leakage generated from the heat-sink. CONSTITUTION: A lead(20) is used for transferring a signal of a semiconductor chip(10) to an outside. A wire(30) is used for connecting the lead(20) with the signal of the semiconductor chip(10). A heat-sink(50) is adhered to a bottom face of the semiconductor chip(10) to emit generated heat to the outside. A sealant(40) is used for protecting the semiconductor chip(10) and each component from the outside. The heat-sink(50) is exposed to the outside of the sealant(40). An insulating layer(51) is formed on a bottom face of the heat-sink(50). The insulating layer(51) is formed by performing an oxidation process for the bottom face of the heat-sink(50).

Description

반도체 패키지의 구조Structure of Semiconductor Package

본 발명은 반도체 패키지의 구조에 관한 것으로, 더욱 상세하게는 열방출의 목적으로 히트싱크가 내장된 반도체 패키지를 마더보드에 실장시 발생되는 리키지(Leakage)를 방지하기 위하여 히트싱크의 표면에 절연층을 형성하여 반도체 패키지의 성능을 향상시키도록 된 반도체 패키지의 구조에 관한 것이다.The present invention relates to a structure of a semiconductor package, and more particularly, to insulate the surface of the heat sink in order to prevent leakage caused when mounting the semiconductor package having a heat sink on the motherboard for the purpose of heat dissipation. It relates to a structure of a semiconductor package to form a layer to improve the performance of the semiconductor package.

일반적인 반도체 패키지의 구성은 도 1에 도시된 바와같이 전자회로가 집적되어 있는 반도체칩(1)과, 상기 반도체칩(1)의 신호를 외부로 전달하는 리드(2)와, 상기의 리드(2)와 반도체칩(1)의 신호를 연결해주는 와이어(3)와, 상기 반도체칩(1)의 회로동작시 발생되는 열을 외부로 방출하도록 반도체칩(1)의 저면에 부착된 히트싱크(5)와, 상기 반도체칩(1)과 그 외의 구성 부품들을 외부로 부터 보호하기 위하여 몰딩된 봉지재(4)로 이루어지는 것이다.As shown in FIG. 1, a general semiconductor package includes a semiconductor chip 1 in which an electronic circuit is integrated, a lead 2 for transmitting a signal of the semiconductor chip 1 to the outside, and the lead 2. ) And a wire (3) connecting the signal of the semiconductor chip (1), and a heat sink (5) attached to the bottom surface of the semiconductor chip (1) to dissipate heat generated during the circuit operation of the semiconductor chip (1) to the outside. ) And the encapsulant 4 molded to protect the semiconductor chip 1 and other components from the outside.

상기 히트싱크(5)의 저면에는 산화방지 및 마킹을 용이하게 하기 위하여 구리(Cu) 또는 니켈/팔라디움(Ni/Pd)을 코팅한 것으로, 이러한 반도체 패키지는 도 2에 도시된 바와같이 마더보드(6)에 실장하여 사용되는 것으로, 이때 마더보드(6)와 반도체 패키지의 저면과는 그 간격이 좁은 것이다. 특히, 비아 홀(6a ; Via Hole)이 노출된 마더보드(6)에 반도체 패키지가 실장될 경우에는 상기 반도체 패키지에 내장된 히트싱크(5)가 열적,전기적으로 전도체임으로서, 상기 히트싱크(5)를 통한 리키지(Leakage)가 발생되어 불량을 초래하고, 성능을 저하시키는 등의 문제점이 있었던 것이다.The bottom surface of the heat sink 5 is coated with copper (Cu) or nickel / palladium (Ni / Pd) in order to facilitate oxidation prevention and marking. Such a semiconductor package includes a motherboard (as shown in FIG. 2). 6), and the gap between the motherboard 6 and the bottom of the semiconductor package is narrow. In particular, when the semiconductor package is mounted on the motherboard 6 in which the via holes 6a are exposed, the heat sink 5 embedded in the semiconductor package is thermally and electrically conductive. 5) Leakage is generated to cause a defect, such as deterioration in performance.

본 발명의 목적은 이와같은 문제점을 해결하기 위하여 발명된 것으로서, 히트싱크가 내장된 반도체 패키지를 마더보드에 실장시 리키지(Leakage)를 방지하기 위하여 히트싱크의 표면에 절연층을 형성하여 불량을 방지하고, 성능을 향상시키도록 된 반도체 패키지의 구조를 제공함에 있다.An object of the present invention is to solve the above problems, and when a semiconductor package with a heat sink is mounted on the motherboard, an insulation layer is formed on the surface of the heat sink to prevent leakage. To provide a structure of a semiconductor package to prevent and improve the performance.

제1도는 종래의 반도체 패키지의 구조를 나타낸 단면도.1 is a cross-sectional view showing the structure of a conventional semiconductor package.

제2도는 종래의 반도체 패키지의 실장상태를 나타낸 단면도.2 is a cross-sectional view showing a mounting state of a conventional semiconductor package.

제3도는 본 발명에 따른 반도체 패키지의 구조를 나타낸 단면도.3 is a cross-sectional view showing the structure of a semiconductor package according to the present invention.

제4도의 (a)(b)는 본 발명에 따른 히트싱크의 구조를 나타낸 정면도.Figure 4 (a) (b) is a front view showing the structure of the heat sink according to the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 반도체칩 20 : 리드10: semiconductor chip 20: lead

30 : 와이어 40 : 봉지재30: wire 40: encapsulant

50 : 히트싱크 51 : 절연층50: heat sink 51: insulating layer

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명에 따른 반도체 패키지의 구성을 나타낸 단면도로서, 그 구조는 전자회로가 집적되어 있는 반도체칩(10)과, 상기 반도체칩(10)의 신호를 외부로 전달하는 리드(20)와, 상기의 리드(20)와 반도체칩(10)의 신호를 연결해주는 와이어(30)와, 상기 반도체칩(10)의 회로동작시 발생되는 열을 외부로 방출하도록 반도체칩(10)의 저면에 부착된 히트싱크(50)와, 상기 반도체칩(10)과 그 외의 구성 부품들을 외부로 부터 보호하기 위하여 몰딩된 봉지재(40)를 포함하며, 상기의 히트 싱크(50)는 봉지재(40)의 외부로 노출되며, 이 노출되는 히트싱크(50)의 저면에 절연층(51)을 형성한 것을 특징으로 한다.3 is a cross-sectional view showing a configuration of a semiconductor package according to the present invention, the structure of which is a semiconductor chip 10 in which an electronic circuit is integrated, a lead 20 for transmitting a signal of the semiconductor chip 10 to the outside; On the bottom surface of the semiconductor chip 10, the wire 30 connecting the signal of the lead 20 and the semiconductor chip 10 and the heat generated during the circuit operation of the semiconductor chip 10 to the outside are discharged to the outside. An attached heat sink 50 and an encapsulant 40 molded to protect the semiconductor chip 10 and other components from the outside, and the heat sink 50 includes an encapsulant 40 ) Is exposed to the outside, and the insulating layer 51 is formed on the bottom of the exposed heat sink 50.

상기 히트싱크(50)의 저면에 형성된 절연층(51)은 도 4의 (a)에 도시된 바와같이 히트싱크(50)의 저면을 산화(Oxidation) 처리하여 절연층(51)을 형성할 수 있고, 히트싱크(50)의 저면에 폴리이미드(Polyimide) 또느 폴리이미드 테이프(Polyimide Tape)를 이용하여 절연층(51)을 형성할 수도 있으며, 히트싱크(50)의 저면에 마킹 잉크(Marking Ink)를 이용하여 반도체 패키지 제조공정에서 절연층을 형성할 수 있다. 또한, 도 4의 (b)에 도시된 바와같이 히트싱크(50)의 저면에 세라믹(Ceramic)이나, 양극 산화처리된 알루미늄(Al) 등의 절연체(51a)를 접착제(52)로 부착할 수 있는 것이다.As shown in FIG. 4A, the insulating layer 51 formed on the bottom surface of the heat sink 50 may oxidize the bottom surface of the heat sink 50 to form the insulating layer 51. The insulating layer 51 may be formed on the bottom surface of the heat sink 50 using polyimide or polyimide tape, and marking ink may be formed on the bottom surface of the heat sink 50. ) May be used to form an insulating layer in a semiconductor package manufacturing process. In addition, as shown in FIG. 4B, an insulator 51a such as ceramic or anodized aluminum (Al) may be attached to the bottom of the heat sink 50 with the adhesive 52. It is.

이와같이 구성된 본 발명의 반도체 패키지를 마더보드에 실장시 마더보드와 반도체 패키지의 저면과의 간격이 없어도 상기 히트싱크(50)의 저면에 형성된 절연층(51)에 의해 리키지(Leakage)의 발생을 방지함으로서 성능을 향상시킬 수 있는 것이다.When the semiconductor package of the present invention configured as described above is mounted on the motherboard, the occurrence of leakage is caused by the insulating layer 51 formed on the bottom of the heat sink 50 even without a gap between the motherboard and the bottom of the semiconductor package. This can improve performance.

이상의 설명에서 알 수 있듯이 본 발명의 반도체 패키지 구조에 의하면, 히트싱크가 내장된 반도체 패키지를 마더보드에 실장시 전도체인 히트싱크에 의해 발생되던 리키지의 발생을 방지함으로서 반도체 패키지의 성능을 향상시킬 수 있는 효과가 있다.As can be seen from the above description, according to the semiconductor package structure of the present invention, when a semiconductor package having a heat sink embedded therein is mounted on a motherboard, the performance of the semiconductor package can be improved by preventing the generation of a liquid generated by the heat sink as a conductor. It has an effect.

Claims (5)

전자회로가 집적되어 있는 반도체칩과, 상기 반도체칩의 신호를 외부로 전달하는 리드와, 상기의 리드와 반도체칩의 신호를 연결해주는 와이어와, 상기 반도체칩의 회로동작시 발생되는 열을 외부로 방출하도록 반도체칩의 저면에 부착된 히트싱크와, 상기 반도체칩과 그 외의 구성 부품들을 외부로 부터 보호하기 위하여 몰딩된 봉지재를 포함하며, 상기의 히트싱크는 봉지재의 외부로 노출되며, 이 노출되는 히트싱크의 저면에는 절연층을 형성한 것을 특징으로 하는 반도체 패키지의 구조.The semiconductor chip in which the electronic circuit is integrated, the lead which transmits the signal of the semiconductor chip to the outside, the wire which connects the signal of the lead and the semiconductor chip, and the heat generated during the circuit operation of the semiconductor chip to the outside A heat sink attached to the bottom surface of the semiconductor chip to emit, and an encapsulant molded to protect the semiconductor chip and other components from the outside, wherein the heat sink is exposed to the outside of the encapsulant. A structure of a semiconductor package, wherein an insulating layer is formed on the bottom of the heat sink. 청구항 1에 있어서, 상기 절연층은 히트싱크의 저면을 산화(Oxidation) 처리하여 형성된 것을 특징으로 하는 반도체 패키지의 구조.The structure of claim 1, wherein the insulating layer is formed by oxidizing a bottom surface of a heat sink. 청구항 1에 있어서, 상기 절연층은 히트싱크의 저면에 폴리이미드(Polyimide) 또는 폴리이미드 테이프(Polyimide Tape)를 부착한 것을 특징으로 하는 반도체 패키지의 구조.The structure of claim 1, wherein the insulating layer is formed by attaching polyimide or polyimide tape to a bottom surface of a heat sink. 청구항 1에 있어서, 상기 절연층은 히트싱크 저면에 마킹 잉크(Marking Ink)를 이용하여 형성된 것을 특징으로 하는 반도체 패키지의 구조.The structure of claim 1, wherein the insulating layer is formed on a bottom surface of a heat sink by using marking ink. 청구항 1에 있어서, 상기 절연층은 히트싱크의 저면에 세라믹(Ceramic)이나, 양극산화처리된 알루미늄(Al)의 절연체를 접착제로 부착하여서 된 것을 특징으로 하는 반도체 패키지의 구조.The structure of a semiconductor package according to claim 1, wherein the insulating layer is formed by attaching an insulator of ceramic or anodized aluminum (Al) to the bottom of the heat sink with an adhesive.
KR1019960074119A 1996-12-27 1996-12-27 Structure of semiconductor package KR100308395B1 (en)

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