KR100307221B1 - Semiconductor memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, in which a plurality of global data bus lines are grouped to reduce the area occupied by global data bus sense amplifiers and write data drivers, and global data bus sense amplifiers and write data drivers are common to many groups. By reducing the number of global data bus sense amplifiers and write data drivers, unnecessary current consumption and layout area are reduced.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a reduced layout area by reducing the number of global data bus sense amplifiers and write data drivers.

As shown in FIG. 1, a conventional 64 mega EDO DRAM has a global data bus sense amplifier 10, 14, 18, 22 (DB SA) and a write date driver (12, 16, 20, 24; WD DRV). One for each pair of global data bus lines 26, 28, 30, 32 is connected.

According to this conventional configuration, since the global data bus sense amplifiers 10, 14, 18, and 22 are connected to each of the global data bus lines 26, 28, 30, and 32, the corresponding global data bus sense amplifiers are provided by the Y address. Will be selected.

However, as shown in FIG. 1, the conventional configuration is connected to one global data bus sense amplifier and a write data driver per pair of global data bus lines, thus occupying a large area on the short side middle side, and thus the density of a limited size wafer. In order to increase the number and increase the number of net dies, the area cannot be reduced any more, although the area must be further reduced.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of reducing the layout area of a semiconductor device and achieving high integration by reducing the number of global data bus sense amplifiers and write data drivers. have.

In order to achieve the above object, a semiconductor memory device according to an embodiment of the present invention includes a plurality of global data bus line and global data bus line bar pairs grouped into a plurality of groups, and a global data bus sense amplifier and a write data driver. It is configured to correspond to a plurality of groups in common.

In addition, the semiconductor memory device of the present invention includes a global data bus selection means, whereby one of the plurality of global data bus line groups is selected to thereby receive data signals of the global data bus line and the global data bus line bars. Configured to switch to global data bus sense amplifiers and write data drivers.

1 is a diagram illustrating a problem in a global data bus sense amplifier and a write data driver connected to a conventional global data bus line;

2 is a diagram showing the configuration of a semiconductor memory device according to a first embodiment of the present invention;

3 is an internal circuit diagram of the global data bus selecting means shown in FIG.

4 is a diagram showing the configuration of a semiconductor memory device according to a second embodiment of the present invention;

FIG. 5 is an internal circuit diagram of the global data bus selecting means shown in FIG.

<Description of the symbols for the main parts of the drawings>

40, 42, 44, 46: switch blocks 50 to 65: global data bus lines

70, 72, 74, 76, 79, 81, 83, 85: global data bus sense amplifiers

Light data driver: 71, 73, 75, 77, 78, 80, 82, 84

90: global data bus selection means

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a diagram showing the configuration of a semiconductor memory device according to a first embodiment of the present invention, which shows one 8 mega block of 64 megabytes divided into eight 8 mega blocks.

The first embodiment of the present invention has a basic structure in which a single global data bus sense amplifier and a write data driver are connected to two global data bus lines, selected by the global data bus selection signals gdb_sel and gdb_selb. The data of the global data bus line is transferred to the corresponding global data bus sense amplifiers (70, 72, 74, 76, 79, 81, 83, 85; DB SA) and write data drivers (71, 73, 75, 77, 78, 80, 82, 84; A plurality of switch blocks 40, 42, 44, 46 for transmitting to WD DRV, a data bus precharge bar (dbpb) and column address signals (ay7, ay7b) are inputted. And a global data bus selecting means 90 (SEL_GDB) for signal processing to provide global data bus selection signals gdb_sel and gdb_selb to the plurality of switch blocks 40, 42, 44 and 46.

The plurality of switch blocks 40, 42, 44, and 46 block a plurality of global data bus lines 50 to 65 in units of a predetermined number (four in the embodiment of the present invention), and the global data bus lines A predetermined number (two in the embodiment of the present invention) of the global data bus lines are provided so as to share one global data bus sense amplifier and write data driver, each of which includes a plurality of PMOS transistors 40a to 40d; 42a to 42d. 44a-44d; 46a-46d).

That is, the global data bus lines 50 and 58 share the global data bus sense amplifier 70 and the write data driver 71 via the PMOS transistors 40a and 44a, and the global data bus lines 51 And 59 share the global data bus sense amplifier 72 and the write data driver 73 via the PMOS transistors 40b and 44b, and the global data bus lines 52 and 60 share the PMOS transistor 40c. 44c), the global data bus sense amplifier 74 and the write data driver 75 are shared.

The global data bus lines 53 and 61 share the global data bus sense amplifier 76 and the write data driver 77 via the PMOS transistors 40d and 44d, and the global data bus lines 54 and 62. ) Share the global data bus sense amplifier 79 and the write data driver 78 via the PMOS transistors 42a and 46a, and the global data bus lines 55 and 63 share the PMOS transistors 42b and 46b. ), The global data bus sense amplifier 81 and the write data driver 80 are shared.

The global data bus lines 56 and 64 share the global data bus sense amplifier 83 and the write data driver 82 via the PMOS transistors 42c and 46c, and the global data bus lines 57 and 65. ) Share the global data bus sense amplifier 85 and the write data driver 84 via the PMOS transistors 42d and 46d.

Meanwhile, as illustrated in FIG. 3, the global data bus selecting unit 90 receives a data bus precharge bar signal dbpb and a column address bar signal ay7b and processes the first global data bus selection signal. A second global data bus selection signal gdb_selb is received by processing an AND gate 90A serving as a first output unit for outputting gdb_sel, the data bus precharge bar signal dbpb, and a column address signal ay7. And AND gates 90B serving as a second output section for outputting each of the &lt; RTI ID = 0.0 &gt; &lt; / RTI &gt; and each of the AND gates 90A and 90B has a series connection structure of NAND gates N1 and N2 and inverters IV1 and IV2.

Therefore, when comparing FIG. 2 with FIG. 1, it can be seen that the number of global data bus sense amplifiers and write data drivers in the first embodiment of the present invention is halved in comparison with the prior art.

Next, the operation of the first embodiment of the present invention configured as described above will be described.

First, in the case of precharging, the data bus precharge bar signal (dbpb), which is a pulse signal that receives a column address and passes through an address transition detector (not shown), is operated to precharge unconditionally. Eight pairs of global data bus lines connected to the sense amplifier and write data driver are precharged.

That is, when the data bus precharge bar signal dbpb is active, &quot; low L &quot; is input to the inputs of the NAND gates N1 and N2 constituting the global data bus selecting means 90 (see FIG. 3). Therefore, the output is &quot; high &quot; The outputs of the respective NAND gates N1 and N2 are converted into &quot; low &quot; through the corresponding inverts IV1 and IV2, so that the PMOS transistors 40a to 40d of the switch blocks 40, 42, 44, and 46 are 42a. ~ 42d; 44a ~ 44d 44a ~ 46d) will be turned on.

In the case of selecting a global data bus line, the global data bus line is selected using the column address 7, that is, 7 blocks (ie, switch blocks 40 and 42) and 7B block (ie, Since the control signals of the switch blocks 44 and 46 must operate simultaneously without skew, the column address bar signal ay7b and the column address signal ay7 are simultaneously input to the decoding.

For example, when the data bus precharge bar signal dbpb is " high " and the column address bar signal ay6b is " low " to the global data bus selector 90 (see FIG. 3), the output of the NAND gate N1. This becomes " high " and the global data bus select signal gdb_sel output via the inverter IV1 is " low ". Since the column address signal ay7b is " high ", the output of the NAND gate N2 is " low " and the global data bus select signal gdb_selb output via the invert IV2 is " high ".

Therefore, the PMOS transistors 40a to 40d (42a to 42d) of the switch blocks 40 and 42 are turned on, and the PMOS transistors 44a to 44d; 46a to 46d of the switch blocks 44 and 46 are turned off. .

Therefore, each of the data carried on the global data bus line is input to the global data bus sense amplifier and the write data driver through the turned-on PMOS transistors 40a to 40d; 42a to 42d.

FIG. 4 is a diagram illustrating a configuration of a semiconductor memory device according to a second embodiment of the present invention, in which the same components and coupling relations as those described in FIG. 2 are formed, except for differences between the switch blocks in the second embodiment of the present invention. (40, 42, 44, 46) is composed of NMOS transistors 40a-40d, 42a-42d, 44a-44d, 46a-46d, and global data bus selector 90 (SEL_GDB) is implemented as a level shifter. This is different from the configuration of the first embodiment of the present invention.

That is, the global data bus selecting means 90 of the second embodiment of the present invention uses the NMOS transistor N3, the column address signal ay7 as the input of the data bus precharge bar signal dbpb, as shown in FIG. By controlling the N4, N5, and N6, the potentials of the nodes a and b are determined to generate a global data bus selection signal gdb_sel and a global data bus selection bar signal gdb_selb.

Therefore, when comparing FIG. 4 with FIG. 1, it can be seen that the number of global data bus sense amplifiers and write data drivers in the second embodiment of the present invention is halved.

Referring to the operation of the second embodiment of the present invention configured as described above are as follows.

First, when the data bus precharge bar signal dbpd is " low " (when performing the precharge operation), the NMOS transistors N4 and N5 constituting the global data bus selecting means 90 (see Fig. 5) are used. It is turned off and NMOS transistors N3 and N6 are turned on to make nodes a and b "low".

Therefore, the PMOS transistors P1 and P4 are turned on and both the NMOS transistors N1, N2, N7, and N8 global data bus select signal gdb_sel and global data bus select bar signal gdb_selb are at the "VPP" level. The NMOS transistors 40a to 40d and 42a to the switch blocks 40, 42, 44, and 46 that receive the global data bus selection signal gdb_sel and the global data bus selection bar signal gdb_selb of the "VPP" level. 42d, 44a-44d, 46a-46d) are turned on to precharge the global data bus lines to a certain level.

On the other hand, when operating with input of ay7, which is the column address 7, the operation is performed while the data bus precharge bar signal dbpd is "high", and the data bus precharge bar signal dbpd is "high". ", The NMOS transistors N4 and N5 constituting the global data bus selecting means 90 (see Fig. 5) are turned off and the NMOS transistors N3 and N6 are turned off. In this state, the column address an7 ) Becomes " high ", the output of the inverter inv2 is " low ", and the potential of the node b, which has been kept " high "

Accordingly, the PMOS transistor P2 is turned on to make node a "high" at the "VPP" level to turn off the PMOS transistor P1, and turn on the NMOS transistor N2 to turn on the global data bus selection bar signal. Make (gdb_selb) "low".

In contrast, the global data bus select bar signal gdb_sel becomes "high" at the "VPP" level because the PMOS transistor P4 is turned on and the NMOS transistor N8 is turned off.

On the other hand, when the column address ay7 is " low ", the output of the inverter inv2 becomes " high ", and the potential of the node a, which has been kept in the " high " state, becomes " low ".

Accordingly, the PMOS transistor P3 is turned on to make the node b "high" at the "VPP" level to turn off the PMOS transistor P4, and turn on the NMOS transistor N8 to turn on the global data bus select bar signal. Make (gdb_sel) "low".

On the contrary, the global data bus select bar signal gdb_selb becomes “high” at the “VPP” level because the PMOS transistor P2 is turned on and the NMOS transistor N2 is turned off.

Therefore, among the switch blocks 40, 42, 44, and 46 that receive the global data bus selection signal gdb_sel and the global data bus selection bar signal gdb_selb having potentials opposite to each other, the " high " The NMOS transistor in the switch block to which the signal is input is turned on to input the data carried on the global data bus line to each global data bus sense amplifier and write data driver.

According to the present invention as described above, the number of global data bus sense amplifiers and write data drivers can be typically reduced compared to the prior art, thereby reducing unnecessary current consumption and layout area, thereby greatly improving integration.

On the other hand, the present invention is not limited only to the above-described embodiments, but may be modified and modified without departing from the scope of the present invention.

Claims (7)

A plurality of bus line groups each including one or more global data bus line and global data bus line bar pairs; One or more global data bus sense amplifiers corresponding in common to the plurality of bus line groups; One or more write data drivers corresponding to the plurality of bus line groups in common; A global data bus selection means for receiving a data bus precharge bar signal and a column address signal and outputting a global data bus selection signal for selecting one of the plurality of bus line groups accordingly; According to the selection signal, the data signals of the one or more global data bus line and the global data bus line bar pair belonging to one of the plurality of bus line groups, the one or more global data bus sense amplifier and the one or more write data driver Switching means for switching to; Semiconductor memory device comprising a. The data bus precharge device of claim 1, wherein the global data bus selecting unit comprises: a first output unit configured to receive a data bus precharge bar signal column address bar signal and process a signal to output a first global data bus selection signal; And a second output unit configured to receive a bar signal and a column address signal, and process the signal to output a second global data bus selection signal. 3. The semiconductor memory device of claim 2, wherein the first and second output units comprise two input and gate gates. The semiconductor memory device according to claim 1, wherein said switching means is comprised of a MOS element. The semiconductor memory device according to claim 4, wherein the MOS device is a PMOS transistor. The semiconductor memory device according to claim 4, wherein the MOS device is an NMOS transistor. The semiconductor memory device according to claim 1, wherein the global data bus selecting means comprises a level shifter which receives the data bus precharge bar signal and the column address signal and level shifts the level data to generate the global data bus selection signal.