GB2127596A

GB2127596A - Dynamic type MOSRAM

Info

Publication number: GB2127596A
Application number: GB08324526A
Authority: GB
Inventors: Tetsuro Matsumoto
Original assignee: Hitachi Ltd
Current assignee: Hitachi Ltd
Priority date: 1982-09-22
Filing date: 1983-09-13
Publication date: 1984-04-11
Also published as: JPH0379799B2; IT8322952A1; DE3333974A1; FR2533349A1; KR840005885A; FR2533349B1; IT8322952A0; JPS5954096A; GB8324526D0; IT1168282B

Abstract

In a dynamic type MOSRAM of the address multiplexing system wherein column selecting address signals and row selecting address signals are time-serially multiplexed and applied to the memory, an individual row address buffer R-ADB and column address buffer C-ADB are provided. Their outputs are multiplexed by a multiplexor MPX on common address lines CR-ADLs, in order to reduce the area occupied by those lines. Thus, the column address buffer can be brought into a precharged status without awaiting the end of the operation of the row address buffer. Accordingly, in the case where the row address buffer and the column address buffer are to be continuously operated at an enhanced speed, the enhancement of the operating speed is not limited by a period of time taken for precharging the column address buffer. Accordingly, the operating speed of this RAM can be enhanced. <IMAGE>

Description

SPECIFICATION Dynamic type MOSRAM This invention relates to a dynamic type MOS (metal-oxide-semiconductor) RAM (random access memory) of the address multiplexing system wherein address signals such as row address signals and column address signals, for example, are multiplexed in time series and then applied to the memory.

When constructing a dynamic type MOSRAM (hereinbelow, termed "D-RAM") on an iC (integrated circuit) chip, the principal circuit blocks and principal wiring thereof are arranged as follows by way of example. A row address buffer and a column address buffer are disposed on the peripheral part of the IC chip, a plurality of memory arrays are disposed on other parts of the IC chip except the peripheral part and are spaced from one another, and address decoders such as row and column decoders are disposed in correspondence with the plurality of memory arrays, adjoining them. By way of example, the address decoder may be arranged between two memory arrays adjacent to each other.

The output wiring leads of the column address buffer and those of the row address buffer are formed on the area of the IC chip other than the area where the memory arrays are constructed, and they extend respectively to the row decoders and column decoders. The numbers of the output wiring leads are comparatively large. This is because all the output address signals of the address buffers are processed into complementary address signals. Moreover, the distances between the address buffers disposed on the peripheral part of the IC chip and the address decoders disposed on the central part thereof are comparatively long. Therefore, the area of the wiring to be set on the IC chip becomes large, and the area for constructing the memory arrays becomes relatively small.Thus, increase in the number of memory cells to be formed on a fixed area, that is, enhancement in the density of integration of the IC, is limited by the comparatively large wiring area.

With note taken of the fact that, in the D-RAM of the address multiplexing system, the row address signals and column address signals are inputted in time series, the inventor of the present application considered, prior to the present invention, using a single address buffer as both a row address buffer and a column address buffer, thereby to render the output wiring thereof common. When the output wiring is rendered common, the wiring area can be reduced, and hence, a larger number of memory cells can be integrated. The inventor's study, however, has revealed that the sharing of the address buffer poses a new problem as explained below. Since the address buffer is constructed of a dynamic circuit, a predetermined node of the circuit must be precharged before the starting of the circuit operation thereof.Accordingly, after the address buffer has operated upon application of the row address signals thereto, this address buffer must be precharged before the column address signals are applied thereto. The precharging requires a predetermined period of time which is not negligible. Accordingly, in a case where the address buffer is to be continuously operated at high speed, the operating speed is limited by the time taken for the precharging. That is, when the address buffer is shared, enhancement in the operating speed of a D-RAM is limited.

In a dynamic type MOSRAM of the present invention, individual row address and column address buffers are provided, and the output wiring of the row address buffer and that of the column address buffer are rendered common through a multiplexor.

Since an individual row address buffer R-ADB and column address buffer G-ADB are provided, the column address buffer C-ADB can be brought into a precharged status without awaiting the end of the operation of the row address buffer.

Accordingly, in a case where the row address buffer R-ADB and column address buffer C-ADB are to be continuously operated at an enhanced speed, the enhancement of the operating speed is not limited by the precharging period of time for the column address buffer C-ADB.

Thus, it is possible to enhance the operating speed of the dynamic type MOSRAM of the address multiplexing system.

Further, since the output wiring of the row address buffer R-ADB and that of the column address buffer C-ADB are rendered common by the multiplexer MPX, the area of the wiring is halved. It is accordingly possible to increase the number of memory cells to be formed on a fixed area of an IC chip, in other words, to enhance the density of integration of the MOSRAM.

Preferred embodiments of the invention will now be described by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a circuit block diagram showing an embodiment of this invention; Figure 2 is a circuit diagram showing a practicable form of the embodiment; Figure 3 is a timing chart for explaining the address setting operation of the embodiment; and Figure 4 is a circuit diagram showing another embodiment of a column decoder C-DCR.

Shown in Figure 1 is a circuit block diagram of a D-RAM of an embodiment. Although not especially restricted to this, the illustrated D-RAM includes eight memory arrays M-ARY1 to M ARY8 each having memory cells arrayed in 128 rowsx64 columns, that is, a memory capacity of 8192 bits (about 8 kbits), and it has a memory capacity of about 64 kbits as a whole. The arrangement of principal circuit blocks in the figure is depicted in conformity with the geometrical arrangement thereof in the case where these blocks are actually constructed on an IC chip.

The row-group address select lines (word lines WL) of each of the memory arrays M-ARY1 to M ARY8 are supplied with 128 decoder output signals which are obtained on the basis of address signals Ag-A6. As a result, any one of the 128 word lines WL is selected and brought to a high level in each memory array.

In this case, in order to shorten the wiring length of the word line WL in each memory array, that is, to reduce the propagation delay time of the transmission of a signal from one end to the other end of the word line WL, row decoders R DCR1 to R-DCR4 totaling four are respectively arranged between the two adjacent memory arrays, as between the memory arrays M-ARY1 and M-ARY3.

A column decoder C-DCR provides 128 decode outputs on the basis of address signals Ag-A15.

The column decoder C-DCR selects four columns at the same time. Thus, adjoining upper and lower columns in the memory arrays arranged on both the sides of the column decoder C-DCR, namely, four columns in total, are selected by the column selecting decode outputs simultaneously brought to a high level.

In order to further select any one of the four columns, address signals A7 and A8 are allotted.

For example, the signal A7 is allotted for the lateral selection, and A8 for the vertical selection.

It is a 6vii signal generator #virSG that provides four combinations of signals on the basis of the address signals A7 and Ag. It is column switch selectors CSW-S 1 and CSW-S2 that select any one of the four columns on the basis of the output signals yOot XyOt' XYtO and Xytt of the circuit SG.

In this manner, a decoder for selecting the column of the memory array is divided into the two stages of the column decoder C-DCR and the column switch selectors CSW-S 1, CSW-S2. The first aim of the division of the decoder in the two stages is to prevent any wasteful blank part from appearing within the IC chip. That is, the vertical length of the column decoder C-DCR and that of the memory array portions arranged bilaterally thereof are prevented from differing greatly, whereby the circuit blocks are arranged on the IC chip in order and without waste. More specifically, the area occupied by NOR gates bearing one pair of right and left output signal lines of the column decoder C-DCR is comparatively large. Therefore, in a case where the decoder is constructed in one stage, the vertical length of the column decoder C-DCR becomes great with respect to that of the memory array portions.For this reason, by dividing the decoder into the two stages, the number of transistors required for the NOR gates is reduced, diminishing the area occupied thereby. In addition, the number of the NOR gates required for the column decoder C-DCR is reduced, thereby to adjust the vertical length of the column decoder C-DCR. The second aim of the division of the decoder into the two stages is to reduce the number of the NOR gates which need to be connected to one address signal line, to lighten the load coupled to the address signal line, and enhance the switching speed in the address signal line.

In this embodiment, in order to enhance the operating speed of the dynamic type MOSRAM of the address multiplexing system, a row address buffer R-ADB and a column address buffer C-ADB are provided individually in accordance with the technical idea of the present invention.

The row address buffer R-ADB accepts the row address signals Ag-A7 of the 8-bit external row address signals Ag-A7 and A8~Ats inputted in multiplexed fashion, in synchronism with an internal timing signal far of high level formed according to the change of an address strobe signal RAS to a low level. At this time, the row address buffer R-ADB has the predetermined node of its internal circuit precharged in advance.

Thus, the row address buffer R-ADB forms eight sorts of complementary row address signals a0- a7 by accepting the row address signals Ag-A7.

The column address buffer C-ADB accepts the 8-bit column address signals A8-A15 in synchronism with an internal timing signal XaC of high level formed according to the change of an address strobe signal CAS to a low level. At this time, the column address buffer C-ADB has the predetermined node of its internal circuit precharged in advance. Thus, the column address buffer C-ADB forms eight sorts of complementary column address signals a8-a18 by accepting the column address signals A8-A18.

Since the row address buffer R-ADB and column address buffer C-ADB are provided individually, the column address buffer C-ADB can be brought into the precharged status without awaiting the end of the operation of the row address buffer R-ADB. Accordingly, in a case where the row address buffer R-ADB and column address buffer C-ADB are to be continuously operated at high speed, enhancement in the operating speed is not limited by the period of time for precharging the column address buffer C ADB.

With this embodiment, therefore, the operating speed of the dynamic type MOSRAM of the address multiplexing system can be enhanced.

Furthermore, in this embodiment, in order to package the memory cells at a higher density, the output wiring of the row address buffer R-ADB and that of the column address buffer C-ADB are coupled to common complementary address signal lines CR-ADLs through a multiplexor MPX in accordance with the technical idea of the present invention. The output signals of the address buffer R-ADB and those of the address buffer C-ADB are time-serially transmitted to the common address signal lines CR-ADLs through the multiplexor MPX whose operation is controlled by the internal timing signals part ac.

Accordingly, the complementary address signals a0-a7 and a8-a15 are still held multiplexed.

In Figure 1, the eight sorts of complementary address signal lines (column/row address lines) CR-ADLs extend vertically in the central part of the drawing (in actuality, the common complementary address signal lines CR-ADLs are arranged on the IC chip so as to pass through substantially the middle part of the column decoder C-DCR). Since these common complementary address signal lines CR-ADLs are used in common for the row selecting complementary address signals a0-a7 and the column selecting complementary address signals a8-a15, the number of wiring leads and the occupying area thereof decrease to half as compared with those in the case where the address signal lines are disposed independently in correspondence with the rows and columns.

Since, in this manner, the output wiring of the row address buffer R-ADB and that of the column address buffer C-ADB are rendered common by the multiplexor MPX, the wiring area is halved.

This makes it possible to increase the number of memory cells to be formed on a fixed area of the IC chip, that is, to integrate the memory cells at a higher density.

The column/row address lines CR-ADLs are branched in both the right-hand and left-hand directions and connected to the row decoders R DCR1 to R-DCR4 through change-over switches SW which are disposed near between the first and second rows of the memory arrays and between the third and fourth rows thereof.

The change-over switches SW have their switching operations controlled by the timing signal far so as to pass only the complementary row address signals a0-a7 therethrough.

Whether the column decoder C-DCR falls into its operating status or non-operating status is determined by whether the timing signal Xdf of the column group (column decoder control signal) is at a high level or low level. Accordingly, the multiplexed complementary column address signals a8-a15 are distinguished from the complementary address signals a0-a7.

Shown in Figure 2 is a circuit diagram of a practicable embodiment of the multiplexor MPX, column decoder C-DCR, row decoder R-DCR and change-over switch SW mentioned above.

Transfer gate MOSFETs (insulated-gate field effect transistors) Q1, Q2 constitute the multiplexor MPX, while a MOSFET Q7 constitutes the change-over switch SW. The timing signal far is impressed on the gates of the MOSFET Qt for transmitting the output signal of the row address buffer R-ADB and the MOSFET Q7 described above, while the timing signal faC is impressed on the gate of the MOSFET Q2 for transmitting the output signal of the column address buffer C ADB.

The row decoder R-DCR is constructed of a plurality of NOR gate circuits. One of the NOR gate circuits is composed of, for example, a precharge MOSFET Q8 and MOSFETs Q9, Q1O constituting a logic block. Likewise, the column decoder C-DCR is constructed of a plurality of NOR gate circuits, one of which is composed of, for example, a precharge MOSFET Q3 and logic block MOSFETs Q4,Q5similar to the above and a MOSFET Q8 disposed between the common source of the logic block MOSFETs 04,08and a ground point.The gate of this MOSFET Q6 is supplied with the timing signal 5df- The circuit operations of the D-RAM in the course of setting an address will now be described with reference to a timing chart in Figure 3.

When the address strobe signal RAS changes to the low level, the timing signal Xar is changed from the low level to the high level. The address buffer R-ADB is operated in synchronism with the change of the timing signal ~ar to the high level, with the result that the eight sorts of complementary address signals a0-a7 corresponding to the external address signals Ag-A7 are formed.These complementary address signals a0-a7 are transmitted to the row decoders R-DCR1 to R-DCR4 through the multiplexor MPX composed of the MOSFETs Qt etc. and the change-over switch SW composed of the MOSFET 07, the MOSFETs Qt and Q7 being held "on" by the high level of the timing signal 'iar Next, when a word line select timing signal Xx rises to its high level, the word line select signals are respectively formed by the four row decoders R-DCR1 to R-DCR4 and transmitted to the word lines WL of the memory arrays. As a result, the word line selection is done.

Subsequently, the timing signal 5iar is rendered low prior to the inputting of the column address signals A8-A 15 After awaiting the word line selecting operation, a timing signal pa is taken to its high level. Sense amplifiers SA1--SA8 are activated by the high level of the timing signal ~pax to amplify stored data read out from the selected memory cells onto data lines DL.

Next, the timing signal Xdf turns from the low level to the high level in accordance with the change of the address strobe signal CAS to the low level. The column decoder C-DCR becomes operable because the power switch MOSFET Q6 thereof is brought into the "on" state by the timing signal ~df of high level.When the timing signal Xac has risen to the high level somewhat later than the time at which the timing signal ~df rises to the high level, the address buffer C-ADB is brought into the operating status, to form the eight sorts of complementary address signals a8-a18 corresponding to the external address signals Ag-A18. These complementary address signals a8-a18 are transmitted to the column decoder C-DCR through the multiplexor MPX composed of the MOSFETs Q2 etc., the MOSFET Q2 being held "on" by the high level of the timing signal XacX Since, at this time, the timing signal ~ar is already at the low level, the change-over switch SW (Q7) is "off", and hence, the complementary address signals a8-a18 are not applied to the row decoder R-DCR. The row address signals a0-a6 are held at the input of the row decoder R-DCR.

Subsequently, upon rise of a column switch control signal Xy to its high level, the sbyij signal generator XVji-SG is brought in response into its operating status.

The complementary address signal a7 corresponding to the address signal A7, and the complementary address signal a8 corresponding to the address signal A8 have already been respectively applied to the yi; signal generator yij~SG at the time when the timing signal star, and the timing signal fac are brought to the high level.

Accordingly, the fYij signal generator çsyj-SG transmits the column select timing signals byoo~ Xytt to the column switch selectors CSW-S1, CSW-S2 substantially simultaneously with the rise of the column switch control signal by to the high level.

In this way, one pair of 512 MOSFET pairs, in the column switches C-SW1 and C-SW2 is selected by the output signals of the column decoder C-DCR and fyij signal generator XyiI-SG.

As a result, one pair of data lines DL and DL in the memory array are connected to a common data line pair CDL, CDL through the pair of MOSFETs selected.

In the D-RAM of the embodiment, the common complementary address signal lines (CR-ADLs) for supplying the eight sorts of complementary address signals to the row decoders R-DCR1 to R DCR4 and the column decoder C-DCR respectively can be shared, so that the density of integration of the IC chip can be sharply enhanced.

By the way, since the area occupied by the address signal lines can be reduced owing to the sharing of the address signal lines CR-ADLs, about forty more memory cells can be arranged in the lateral direction than in the case where the address signal lines are not shared. Since the 512 memory cells can be formed in the vertical direction as described before, the area occupied by the memory cells could be reduced by an area corresponding to about 4 kbits.

Moreover, since this embodiment is provided with the independent address buffers for the row address signals Ag-A7 and column address signals A8-A15, the operation of accepting the address signals can be rendered fast. In a case where an address buffer is used for the row address signals and column address signals in common, a precharging operation which takes a comparatively long time is required in accepting the column address signals after having accepted the row address signals, and hence, the address signal accepting operation delays by the precharging time.

Figure 4 is a circuit diagram of essential portions showing another embodiment óf the present invention.

In this embodiment, by utilizing the fact that the common data lines CDL, CDL are wired in the same direction as that of the address signal lines CR-ADLs, some of the address signal lines CR ADLs are used in common as the common data lines CDL, CDL. The reason why such common use is possible is that the time at which the read/write data signals are transmitted to the common data lines CDL, CDL is later than the transmission of the complementary column address signals a8-a18 to the column decoder C DCR through the address signal lines CR-ADLs.

In the case where the common data lines CDL, CDL and address signal lines CR-ADLs are shared in this manner, the function of latching the address signals needs to be added. The column decoder C-DCR is constructed of MOSFETs O,- Q5 similar to those of the column decoder C-DCR in Figure 2. Circuit elements to be stated below, constituting a latch circuit LA are added to the output stage of the column decoder C-DCR.

The output of a NOR gate constituting the column decoder C-DCR is transmitted to the gate of a MOSFET Qt4 constituting the column switch selector CSW-S, through a transfer gate MOSFET Qt2 The gate of the transfer gate MOSFET Qr2 is connected to a precharge MOSFET Qtt and a discharge MOSFET Q,3, the gate of which is supplied with the column switch select timing signal fy~j which passes through the MOSFET Qt4.

Now, the operations of the circuit of this embodiment will be described.

When the column address signals applied from the common complementary address signal lines CR-ADLs to the gates of the input MOSFETs of the column decoder C-DCR are all at the low level and the decode output thereof is at the high level, the timing signal byi; supplied turns "on" MOSFETs015andQ16 constituting the column switch C-SW and also turns "on" the discharge MOSFET Q3, so that the MOSFET 012 turns "off".

Accordingly, the decode output signal is retained at the gate of the MOSFET 014.

Simultaneously with the turn-on of the MOSFETs Q15 QX6 constituting the column switch C-SW, in the reading mode, read signals from the data lines DL, DL are transmitted to some of the common complementary address signal lines CR-ADLs and applied to the inputs of a data output buffer not shown (DOB in Figure 1), while in the writing mode, write data formed by a data input buffer not shown (DIB in Figure 1) are transmitted from the common complementary address signal lines CR-ADLs to the data lines DL, DL.

Even when, at this time, logic MOSFETs Q5, Q6 etc. constituting the column decoder C-DCR are turned "on" by the data signals on the address signal lines, no influence is exerted owing to the "off" state of the MOSFET 012.

In this embodiment, the wiring area of the common data lines CDL, CDL can be curtailed by sharing the common data lines CDL, CDL and common complementary address signal lines CR ADLs, so that enhancement in the packaging density of the IC chip can be achieved still more.

This invention is not restricted to the foregoing embodiments.

The arrangement of memory arrays may be any other than the foregoing 8-mat type, for example, the 4-mat type as long as row address signal lines and column address signal lines or/and common data lines run in parallel.

It will be needless to say that, when the sharing of the address signal lines makes it necessary to precharge or reset them in transmitting different signals, a circuit therefor is provided.

Further, the layout and practicable circuit arrangements of the peripheral circuits thereof can adopt various aspects of performance. That is, this invention is extensively applicable to D-RAMs of the address multiplexing type.

Claims

1. A dynamic type MOSRAM comprising: a row address buffer which forms, on the basis of input row address signals, output row address signals corresponding thereto in synchronism with a first internal timing signal; a column address buffer which forms, on the basis of input column address signals which are inputted in time-series multiplex with the input row address signals, output column address signals corresponding thereto in synchronism with a second internal timing signal; a multiplexor which time-serially multiplexes the output row address signals and the output column address signals and transmits them to common address signal lines in synchronism with the first and second internal timing signals; a row decoder which forms a word line select signal on the basis of the row address signals transmitted to said common address signal lines; and a column decoder which forms a data line select signal on the basis of the column address signals transmitted to said common address signal lines.

2. A dynamic type MOSRAM according to Claim 1, further comprising a transfer gate circuit which selectively transmits the row address signals transmitted to said common address signal lines, to said row decoder.

3. A dynamic type MOSRAM according to claim 1 or claim 2, wherein said column decoder is controlled so as to operate only while the column address signals are being transmitted to said common address signal lines.

4. A dynamic type MOSRAM according to Claim 3, further comprising: a switching MOSFET whose source-drain path couples the common address signal line and a data line with input/output terminals of a memory cell coupled thereto; and a latch circuit which latches the output signal of said column decoder and which applies this signal to a gate of said switching MOSFET; input/output signals of the memory cell being transmitted by said common address signal line.

5. A dynamic type MOSRAM substantially as described herein with reference to the accompanying drawings.