KR100305762B1 - Device test device on board - Google Patents

Abstract

The present invention relates to a device test apparatus on a board, and an apparatus for determining whether a device is defective in a board equipped with an FPGA, an oscillator, a JTAG supporting device, and a main control unit (MCU) for controlling the devices. Receiving a control command for testing each device from the main control unit, and a sequence output generated by dividing a predetermined value by a predetermined value by the clock of the oscillator and a sequence output generated from each FPGA and a JTAG command to the JTAG supporting device. A test FPGA for determining whether the respective devices are defective based on the output of the JTAG supporting device obtained by generating a signal generator, and LED display means for displaying whether the respective devices are defective based on the test result of the test FPGA. Characterized in that configured.

Accordingly, it is possible to check which device is malfunctioning in the board of the general transmission apparatus with the board mounted on the transmission equipment, thereby providing an effect of stabilizing the equipment more quickly.

Description

Device test device on board

The present invention relates to a device test apparatus in a board, and more particularly, to a device test apparatus in a board that enables the JTAG to search for and determine whether or not each element in the board is defective without removing the board from the device.

Generally, when a board included in a transmission device is manufactured or operated in a device, a board operation error may occur due to a poor soldering or damage to a chip on the board. At this time, to check which part on the board is damaged, the board is detached from the device and inspected by a tester, or a separate test board is used to check for defects. However, using this method, it can take a long time to find out which part is damaged. On the other hand, the BIST (Built-In Self Test) method or boundary scan test (JTAG), which is widely used, is a structure for determining whether or not there is a defect in devices on the board.

The interface scan test is a protocol for test circuits to check if the device is working properly. It is a method of inputting a command and a data clock to analyze the serial data output. The boundary scan test has a structure in which multiple devices are connected in series to use a single clock and data line, and a structure in which multiple devices are connected in parallel to use multiple clock and data lines.

The boundary scan test specifies three commands that must be supported. The commands of bypass, sample / preload, and extest may be different depending on each device. Here, the defect status of the device can be checked through a bypass test.

In general, the boundary scan test is to test each board independently, and a separate circuit is required to read the test information through the control unit in the device. Therefore, it is difficult to check on the transmission equipment itself, and it must be disconnected from the equipment and connected to a test apparatus or a computer to check the output result.

In the case of an FPGA, when initialization is performed through a ROM, a method of inspecting the LED by connecting a pin indicating that the initialization is completed is used. However, once the FPGA is set up without using ROM, it is not applicable to a fusing method that remains set regardless of power supply.

The methods used to determine if a device is defective are indicated by LEDs using certain pins held at specific values when the FPGA device is not working, and devices that do not support these pins can be used to There is a method of separating and verifying with a tester, and an operation test of an element in a board through a boundary scan test. JTAG has a single scan and multiple scan method, and a controller to control TCK, TMA, and TDI is required. Typically, these controllers are independent of the board or implemented in computer programming.

1 and 2 show a single scan path structure and multiple scan paths, respectively. As shown in FIG. 1, in a single scan path structure, a plurality of devices are connected in series to use one clock and data line. As shown in FIG. Is connected in parallel and uses multiple clocks and data lines.

The interface scan test is a protocol for a device inspection circuit that determines the state of device operation as a result of an input command. The internal structure of the interface scan scan is shown in FIG. 3, and each scan state is shown in FIG.

As shown in FIG. 3, there are three signals controlling the boundary scan test, TCK, TDI, and TMS. The TMS is a signal that controls what is the state of the current boundary scan test, and the TDI is a command to be performed by the interface scan test. TCK is a clock signal for the device to receive the inputs of TDI and TMS.

By using the bypass command among the devices that support the boundary scan test, the bypass command can be used to mask the failure of the device. 11 '. If the chip does not operate, the desired output is not output from the TDO. Therefore, it is possible to determine whether the chip is bad or not, and devices that support JTAG must have this command.

However, in order to find a defective device in the board using the boundary scan test, a circuit for controlling signals such as TCK, TDI, and TMS is required, and a circuit or a program for checking the output data is required. The structure that is widely used at present is to inspect and control data by using a separate device or program outside the board, and it is difficult to check the device defects in the board in the transmission equipment. In the case of an FPGA, a pin indicating that configuration is completed from the ROM is used to determine whether a device is defective. However, in the case of a fusing FPGA, such a pin is not present, and thus it is difficult to apply. In addition, the structure that simply counts the output of the oscillator and judges that the clock is coming out when it reaches a certain value has a problem that cannot be notified immediately if a problem occurs in the oscillator during operation.

Accordingly, the present invention solves the above problems and enables the check of which device is malfunctioning in the transmission equipment by identifying a device defect supporting an FPGA, an oscillator, and a JTAG in connection with the control unit of the device. It is an object of the present invention to provide a device test apparatus in a board that can be checked in a state where the is mounted.

1 is a conventional single scan path structure diagram.

2 is a conventional multiple scan path structure diagram.

3 is an internal structure diagram of a boundary scan test (JTAG).

4 is a scanning state diagram of a boundary scan test (JTAG).

5 is a block diagram of a device test apparatus in a board according to an embodiment of the present invention.

6 is an internal operation block diagram of a test FPGA according to an embodiment of the present invention.

7 is a block diagram illustrating a configuration of a JTAG control unit according to an embodiment of the present invention.

8 (a) is a circuit diagram for checking the output of a clock according to an embodiment of the present invention.

8 (b) is a sequence investigation circuit diagram of a specific pin on an FPGA according to an embodiment of the present invention.

8 (c) is a sequence generating circuit for a specific pin on an FPGA according to an embodiment of the present invention.

9 (a) to 9 (k) are detailed circuit diagrams of a JTAG control unit of a test FPGA according to an embodiment of the present invention.

10 (a) to 10 (c) are circuit diagrams of a device command unit according to an embodiment of the present invention.

11 (a) to 11 (g) are detailed circuit diagrams of a byte read unit according to an embodiment of the present invention.

12 (a) to 12 (d) are circuit diagrams of a device check donor unit according to an embodiment of the present invention.

13 is a circuit diagram of Make JTAG Clk for timing adjustment of TCK.

14 is a circuit diagram of Count 4 for adjusting a sequence according to an embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

100: oscillator 200: FPGA

300: JTAG supporting device 400: test FPGA

410: FPGA control unit 420: clock control unit

430: JTAG control unit 431: device command unit

432: byte lead unit 433: device check money unit

An on-board device test apparatus according to the present invention for achieving the above object is to determine whether each device in the board is equipped with an FPGA, an oscillator, a JTAG support device and a control unit (MCU) for controlling the devices. An apparatus comprising: a sequence output obtained by dividing a predetermined value by a sequence output generated from each FPGA and a clock of the oscillator by receiving a control command for testing each device from the main control unit; A test FPGA for determining whether each device is defective based on the output of a JTAG supporting device obtained by issuing a JTAG command to the LED, and an LED display indicating whether the respective devices are defective through the test results by the test FPGA. Characterized in that it comprises a means.

According to an exemplary embodiment of the test FPGA, a FPGA controller for determining whether an FPGA device is defective by identifying sequence information of each FPGA by receiving a sequence output value from each FPGA, and setting a constant value by a clock provided from the oscillator Based on the data divided into two parts, a clock control unit for determining whether the oscillator is defective by the sequence output outputted by the two parts, and a JTAG command generated for each of the JTAG supporting elements and bypassed to the JTAG supporting elements. JTAG control unit for determining whether the JTAG support element is defective, and the MCU command processing unit for controlling each unit to process the command received from the MCU and report the status information of each device to the MCU.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

5 shows the configuration of a device test apparatus in a board according to an embodiment of the present invention.

As shown, the device test apparatus on a board according to an embodiment of the present invention includes an oscillator 100 for generating a clock, a plurality of FPGAs 200 arranged in multiple stages and associated with operation of the board, and a boundary inspection. Receives a sequence output from the plurality of JTAG support devices 300, the devices on the board, and each of the FPGAs, and outputs JTAG control signals (TCK, TCM, TDI) based on the clock of the oscillator to output JTAG support devices. Test FPGA 400 which stores the test results and stores the test results and reports them to a main control unit (MCU), and a plurality of devices for indicating whether or not each device is defective through the test results of the test FPGA. It consists of an LED element 500.

As described above, the device test apparatus in the board according to an embodiment of the present invention stores the test / results of the FPGA, the oscillator, and each device in order to check the device failure in the board including the FPGA, the oscillator, and the JTAG supporting device. Set up the test FPGA 400 which is responsible for reporting to the control unit of the equipment, and assign one pin to each of the FPGAs 200 related to the operation of the actual board. Generate a sequence of 01 ”. The test FPGA checks whether the sequence is coming from each FPGA and displays it as an LED, and stores it as a status corresponding to each FPGA internally. If an error occurs in one FPGA, the LED 500 indicating an error is turned on, and a corresponding status bit is set to '1'.

6 is a block diagram illustrating an internal configuration of a test FPGA 400 for a device test apparatus in a board according to an embodiment of the present invention.

As shown in the drawing, the test FPGA 400 receives sequence output values from the respective FPGAs, checks the state information of each FPGA, and determines whether the FPGA device is defective or not from the oscillator 100. JTAG command is given to the clock control unit 420 and the JTAG supporting element 300 to determine whether the oscillator is defective by dividing the signal into a predetermined value by the provided clock, and outputting the divided signal. A JTAG control unit 430 for determining whether the JTAG support element is defective or not based on data generated and bypassed by the JTAG support element 300, and controlling the units 410, 420, 430 and processing a command received from the MCU. And MCU command processing unit 440 for reporting the status information of each device to the MCU.

As shown in the figure, the control unit receives a control command from a board performing unit control, interprets the command, and performs a corresponding task. The FPGA controller 410 stores information on an operation confirmation pin of an input FPGA, and the clock controller 420 divides a predetermined value based on a clock input from an oscillator, and divides a predetermined value into “010101... Check if the sequence of 01 ”is output correctly and judge whether the clock input is correct from oscillator and judge whether the oscillator is defective or not.

The structure of the JTAG according to an embodiment uses a multi-scan structure and is designed to select which of the devices on the board are to be searched.

7 shows a JTAG control unit 430 of an on-board device test apparatus according to an embodiment of the present invention.

As shown, the JTAG control unit 430 generates a JTAG bypass start command and a JTAG control signal (TCK, TMS, TDI) to the JTAG support element 300 to be tested through the MCM command processing unit 440. A byte read section 432 for reading the data TDO bypassed from the JTAG supporting element and comparing the data TDI input to the JTAG supporting element and latching the result in each flag; And a device check donor 433 for reporting the inspection result of the JTAG supporting device to the MCU and generating a corresponding sequence to terminate the JTAG command.

When a command for testing a device is input from the MCU command processor 440, the device command unit 431 generates a JTAG bypass start command to the selected JTAG support device 300, and generates a JTAG control signal (TCK, TMS, TDI).

The byte read unit 432 reads the data TDO bypassed from the JTAG support element, compares it with the data TDI input to the JTAG support element, and latches the result in each flag.

The device check donor unit 433 reports the test result of the JTAG supporting device to the MCU and generates a JTAG command sequence to terminate the JTAG command.

An on-board device test apparatus according to an embodiment of the present invention is designed to inspect a defect of an FPGA, an oscillator, and a JTAG supporting device on a board in connection with a control unit of the device.

8 (a) to 8 (c) show detailed circuits of the FPGA controller 410 and the clock controller 420. The logic circuits 801 to 804 of the clock controller 420 are shown in FIG. 8 (a), and the logic circuits 805 to 807 of the FPGA controller 410 are shown in FIG. 8 (b). 8 (c), a logic circuit 808 for generating a sequence is shown. As shown in FIG. 8 (c), failure inspection of the FPGA is performed by setting a specific pin on the FPGA as shown in FIG. The sequence of " 01 " is generated so that the test FPGA receives the values of these pins and examines the sequence as shown in FIG. 8 (b). If the FPGA is not properly aligned or there is a problem during operation, there will be a problem with the output sequence, so an error will be immediately indicated by the corresponding LED, and the status bit for the FPGA in question is set to '1'.

In order to determine whether the oscillator is defective, a predetermined value is divided into two by a clock output from the oscillator, and the divided "0101..." Check that the 01 " sequence is correct, and check the output of the clock as shown in Fig. 8A. If the oscillator encounters a problem while the board is running, the LED will light up indicating that there is a problem with the clock, and its state is set to bit 1. If the LED indicates a problem, reading the corresponding status bits from the control unit of the transmitting equipment will indicate which device has the problem.

9 (a) to 9 (k), detailed circuit diagrams of the MCU command processor 440 and the JTAG controller 430 are shown.

FIG. 9A illustrates a setting status of the MCU command processor 440. As shown in the figure, the unit control board of the device receives the command through the address line and interprets it to determine which command to perform and which device to select. It is assumed that there are three devices to be checked through JTAG, and the address line for commanding is set to 4 bits, and the line for selecting devices is set to 2 bits (this value can be expanded as necessary).

The part controlling JTAG is divided into three parts, and there is a counter circuit for generating TCK externally. The TCK is generated in 8-bit units, and the JTAG timing of each device can be different, so it adjusts the external counter circuit to change the period of the TCK.

FIG. 9B shows the device command unit 431, the byte read unit 432, and the device check donor unit 433.

In Fig. 9 (c), the OR logic circuits 901 to 903 for outputting the TMS control signal are shown. In the example, it is assumed that there are three devices to be tested, so three OR logic circuits are provided.

In Fig. 9 (d), the OR logic circuits 904 to 906 for outputting a TDI control signal are shown. Three OR logic circuits are also provided. In Fig. 9E, the OR logic circuits 907 to 909 for outputting the TCK clock are shown.

FIG. 9 (f) shows logic circuits 910 to 921 which output a TCK COMMAND signal which is one of the input signals in FIG. 9 (e), and output a JTAG_COUNT signal. As shown, the EN_DEVICE signal output from the MCU command processor 440 of FIG. 9 (a) and the EN_COMMAND signal output from the device command unit 431 of FIG. 9 (b) are received as inputs.

In Fig. 9 (g), logic circuits 922 to 936 which output a TCK DATA signal which is one of the input signals in Fig. 9 (e), and output BIT8_COUNT_FIRST0 to 3, BIT8_COUNT_SECOND0 to 3, and BIT8_COUNT_THIRD0 to 3 signals. Is shown. As shown, the EN_DEVICE signal output from the MCU command processor 440 of FIG. 9A and the JTAG_READ_MODE signal output from the byte readout part 432 of FIG. 9B are input.

9 (h) shows logic circuits 937 to 942 for outputting the JTAG_COUNT 0-4 signals and the JTAG_COMMAND_DONE signal. As shown, JTAG_COUNT 0 is output by receiving the input signals JTAG_COUNT_FIST0, JTAG_COUNT_SECOND0, and JTAG_COUNT_THIRD0 as the input signals of FIG. 9 (f). In addition, the JTAG_COMMAND_DONE signal is calculated by outputting the JTAG_COMMAND_DONE_FIRST and JTAG_COMMAND_DONE_SECOND and JTAG_COMMAND_DONE_THIRD signals.

9 (i) shows logic circuits 943 to 946 for outputting BIT8_COUNT0 to 3 signals. As shown, the output signal BIT8_COUNT 0 is calculated by outputting the BIT8_COUNT_FIRST0 and BIT8_COUNT_SECOND0 and BIT8_COUNT_THIRD 0 signals which are the output signals of FIG. 9 (h).

In FIG. 9 (j), logic circuits 947 to 961 which output a TCK_END signal which is one of the input signals in FIG. 9 (e), and output COUNT_END_FIRST0 to 3, COUNT_END_SECOND0 to 3, and COUNT_END_THIRD0 to 3 signals Shown. As shown, the EN_DEVICE signal which is the output signal of the MCU command processor 440 shown in FIG. 9 (a) and the device check donor unit 433 of FIG. 9 (b) are shown. It receives END_JTAG_COMMAND signal as an output signal.

In Fig. 9 (k), logic circuits 962 to 965 for outputting the COUNT_END0 to 3 signals are shown. As shown, the output signal COUNT_END0 receives the COUNT_END_FIRST0, COUNT_END_SECOND0, and COUNT_END_THIRD0 signals as inputs, and is output.

10 (a) to 10 (e) show detailed circuits of the device command unit 431. As shown, the start command of JTAG is issued. Here, it is assumed that the bypass command of each device is 32 bits. The number of bits can be adjusted by adjusting the JTAG COUNT of the external TCK counter parts. Bypass command is input, followed by 8bit of 01010101 for device identification.

10 (a) shows logic circuits 1001 and 1002 for outputting FIRST_BYTE_TMS, and FIG. 10 (b) shows AND logic circuits 1003 to 1006 for outputting SECOND_BYTE_TMS, FIRST_BYTE_TDI, SECOND_BYTE_TDI, and THIRD_BYTE_TDI, respectively. Fig. 10 (c) shows logic circuits 1007 and 1008 outputting THIRD_BYTE_TMS, and Fig. 10 (d) shows logic circuits 1009 and 1010 outputting FOURTH_BYTE_TMS and Fig. 10 (e) In the diagram, logic circuits 1011 and 1012 in which FOURTH_BYTE_TDI are output are shown.

11 (a) to 11 (d) show a detailed circuit diagram of the byte read section 432. As shown, the data is read through the TTAG of the JTAG and the current device is checked to see if it is 01010101. Check the value and assign a value to each flag. If there is an error, the flag value for that device is set to '1'. If any flag is set to '1', the LED indicates that the device is bad.

11A shows a logic circuit 1101 for outputting a JTAG_READ_MODE signal for reading the TDO of the device. FIG. 11B shows logic circuits 1102 to 1112 for reading the 8-bit TDO of the element and receiving the latched data as inputs and outputting flag data based on the sequence. 11 (c) shows logic circuits 1113 to 1115 for receiving flag data as an output signal of FIG. 11 (b) as an input and outputting flag values of respective elements. FIG. 11 (d) shows a demux 1116 for outputting LATCH_SIG0 to 7 which are data latch signals for reading 8-bit TDO data based on the JTAG_READ_MODE signal of FIG. 11 (a). FIG. 11E shows a mux 1117 for outputting a TDI for a command to read 8-bit TDO data based on the JTAG_READ_MODE signal. 11 (f) and 11 (g) receive LATCH_0-7 and TDO_DATA, which are the conversion signals of LATCH_SIG0-7, which are the mux output signals shown in FIG. 11 (d), and output them as LATCHED_DATA0-7. Logic circuits 1118-1125 are shown for converting to parallel form. The LATCHED_DATA0 to 7 are used as input data of a logic circuit for outputting flag data shown in FIG. 11 (b).

12 (a) to 12 (d), detailed circuits of the device check donor 433 are shown. Generate the sequence to terminate the JTAG instruction. As shown in FIG. 12 (a), when it is confirmed that the TDO data has been read by receiving the READ_DONE and COUNT_END signals, an END_JTAG_COMMAND signal, which is an end command signal for termination, is output (1201). 12B illustrates an AND logic circuit 1202 that receives the END_JTAG_COMMAND signal and the COUNT_END0 to 3 signals as inputs and outputs a TMS control signal. FIG. 12 (c) shows the AND logic circuits 1203 to 1205 for receiving the TMS control signal, the SELECTED_FIRST, SELECTED_SECOND, and SELECTED_THIRD signals as inputs, and performing an AND operation to output TMS_FIRST, TMS_SECOND, and TMS_THIRD. FIG. 12 (d) shows the AND logic circuits 1206 to 1208 for receiving the END_JTAG_COMMAND signal, the SELECTED_FIRST, SELECTED_SECOND, and SELECTED_THIRD signals as inputs, and performing an AND operation to output TDI_FIRST, TDI_SECOND, and TDI_THIRD.

The TCK is generated in units of 8 bits, and the timing adjustment of the TCK is performed in Make Jtag Clk as shown in FIG. 13, and the adjustment of the sequence is processed in the count 4 portion as shown in FIG.

13 shows counter circuits 1301 to 1314 for converting and providing the period of TCK since the JTAG timing of each element may be different. As shown, three flip-flops that generate an 8-bit TCK clock and their output are ORed and NAND-operated to output JTAG_CLK for each device. 14 shows counter circuits 1401-1409 that consist of four bits for adjusting the sequence. The operation of reading the output data of the TDO is counted by the counter circuits 1401-1409.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, conversions, and modifications are possible within the scope without departing from the technical spirit of the present invention. It will be apparent to those who have knowledge.

According to the present invention, the defective devices supporting FPGA, oscillator, and JTAG in the board of a general transmission device can be confirmed in connection with the control unit of the device. When a specific device is added due to the failure, it is possible to check which device is in operation with the board mounted on the transmission equipment, and provides the effect of stabilizing the equipment more quickly.

Claims (4)

An apparatus for determining whether an element in a board including an FPGA 200, an oscillator 100, a JTAG support element 300, and a main control unit (MCU) for controlling the elements is defective. A sequence output generated from each FPGA 200 by receiving a control command for testing each device from a control unit, a sequence output obtained by dividing a predetermined value by a clock of the oscillator 100, and the JTAG Based on the output of the JTAG support device obtained by generating a JTAG command to the support device 300 to determine whether each device is defective, the sequence information is received from the respective FPGA 200 and the state information of each FPGA is grasped. An FPGA controller 410 for determining whether the FPGA device is defective; A clock controller (420) for determining whether the oscillator (100) is defective by dividing a predetermined value by a clock provided from the oscillator (100), and dividing the predetermined value by a sequence output that is divided and outputted; A JTAG control unit 430 for generating a JTAG command to each JTAG support element 300 to determine whether the JTAG support element 300 is defective based on data bypassed to the JTAG support element 300; For controlling the units 410, 420, 430 and processing the command received from the main control unit (MCU), including a MCU command processing unit 440 for reporting the status information of each device to the main control unit (MCU) FPGA 400; Device testing apparatus on board, characterized in that it comprises a LED display means (500) for indicating whether or not each of the devices are defective through the test by the test FPGA (400). The JTAG controller 430 of claim 1, wherein the JTAG controller 430 generates a JTAG bypass start command and a JTAG control signal (TCK, TMS, TDI) to the JTAG supporting device 300 to be selected through the MCU command processor 440. A device command unit 431; A byte read portion 432 for reading the data TDO bypassed from the JTAG support element and comparing the data TDI input to the JTAG support element and latching the result in each flag; And a device check donor unit 433 for reporting a test result of the JTAG supporting device to the MCU and generating a corresponding sequence so that a JTAG command is terminated. 4. The device test apparatus of claim 3, wherein the JTAG control unit (430) further includes a JTAG clock generator for providing a clock that matches the JTAG timing of each JTAG supporting element. 4. The byte read unit 432 reads the output data of the JTAG supporting device, checks the bypassed value of the corresponding device, and sets the flag value corresponding to the device to 1 when there is an error. The device test apparatus of the board characterized in that it is configured to determine that the device is defective if the flag of is set to 1.