CN117517937A - Universal test structure and test system for digital chip - Google Patents
Universal test structure and test system for digital chip Download PDFInfo
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- CN117517937A CN117517937A CN202311491948.7A CN202311491948A CN117517937A CN 117517937 A CN117517937 A CN 117517937A CN 202311491948 A CN202311491948 A CN 202311491948A CN 117517937 A CN117517937 A CN 117517937A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31724—Test controller, e.g. BIST state machine
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
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Abstract
The invention relates to the technical field of digital chip testing, and discloses a universal test structure and a test system of a digital chip, wherein the universal test structure and the test system comprise a working mode detection unit, a BIST analysis unit, a scan chain test interface unit and N BIST test interface units; when the invention is used, the current working mode is set by the working mode detection unit, the BIST analysis unit selects one IP module for testing according to the current working mode, and the two mode setting pins of the working mode detection unit are multiplexed, so that the pin number for testing can be reduced, the CP testing cost is reduced, and the testing risk is reduced; in addition, because the BIST analysis unit analyzes the external data and sends the analyzed external data to the BIST test interface unit or the scan chain test interface unit, the invention can realize two tests by only connecting one working mode detection unit with the tester, thereby realizing the unification of test interfaces and universal test.
Description
Technical Field
The invention relates to the technical field of digital chip testing, in particular to a universal test structure and a universal test system for a digital chip.
Background
After the wafer is manufactured, thousands of unpackaged chips which are regularly distributed are distributed on the surface of the whole wafer, CP (Chip Probing) testing is needed to be carried out on the chips before the chips are packaged, namely, each unpackaged chip is subjected to function and performance testing, and only the chips passing the CP testing can be packaged, so that the unnecessary chip packaging tool quantity is reduced.
After the chip is packaged, a FT (Final Test) test is required to be performed on the packaged chip, so that whether the function of the packaged chip is normal or not and whether new defects are generated in the packaging process or not are detected, and the chip passing the FT test can meet the requirements of practical application only.
Current technologies for performing CP test and FT test include BIST (Build in selftest) test, scan chain test, JTAG (Joint Test Action Group) test;
the BIST test is also called built-in self test, and is a technology for embedding related circuits in a chip circuit for providing a self-test function when designing the chip, so that the dependence of device test on Automatic Test Equipment (ATE) is reduced;
scan Chain test is to replace the original general trigger in the circuit with the observable and controllable Scan trigger to test, and the Scan triggers are connected in series to form a Scan Chain, so that external data can be serially moved in and out through the Scan Chain in a test mode to realize the control and observation of the whole circuit;
the JTAG Test is mainly carried out by using a JTAG interface, and the JTAG interface is an international standard Test protocol and is mainly used for testing the inside of a chip.
With the existing test technology, since each IP module (power module LDO, clock module OSC, flash module, etc.) of the chip has a respective BIST test interface, unlike a scan chain interface, the non-uniformity of the BIST test interface significantly increases the cost of developing test programs on Automated Test Equipment (ATE). Although JTAG test technology provides a unified test interface, it also needs to be matched by software to actually implement test functions.
In addition, for CP testing, since the probe card needs to be pricked to a chip pin to be connected with a test machine for testing, the greater the number of test pins, the higher the risk of inaccurate needle pricking position of the probe card, which can cause lower accuracy of CP testing. Meanwhile, the more the number of pins is, the fewer the number of chips which can be tested in parallel on the wafer is, and the cost of CP test is increased, so that the fewer the number of test pins used in the test process is, the better the test effect is;
for scan chain testing, it requires four test pins, CK (clock) pin, SE (scan enable) pin, SI (scan in) pin and SO (scan out) pin;
for JTAG testing, it requires five pins, TCK (clock) pin, TMS (mode select) pin, TDI (data in) pin, TDO (data out) pin, and optional pin TRST (test reset) pin;
for BIST testing, the interfaces are not uniform because the individual modules are designed separately, but at least four pins, clock pins, test enable pins, input pins, and output pins, are required, and the more complex functional IP modules may require more pins.
Disclosure of Invention
In view of the shortcomings of the background art, the invention provides a general test structure and a test system of a digital chip, and aims to solve the technical problems that the interface structure for unified BIST test and scan chain test is lacking at present, the number of test pins is large, and at least four pins are needed.
In order to solve the technical problems, the first aspect of the invention provides the following technical scheme: the universal test structure of the digital chip comprises a working mode detection unit, a BIST analysis unit, a scan chain test interface unit and N BIST test interface units, wherein N is a positive integer;
the working mode detection unit comprises a clock pin for receiving a clock, M mode setting pins for setting a working mode, a test clock output pin, a test data input pin, a test data output pin and a working mode output pin, M is a positive integer greater than 1, and two mode setting pins in the M mode setting pins are multiplexing pins for inputting external data and outputting detection data respectively;
the working mode detection unit outputs a test clock through the test clock output pin based on the clock, outputs a working mode selection signal through a working mode output pin based on the input signal level states of the M mode setting pins, and the test data input pin and the test data output pin are electrically connected with the two multiplexing pins;
the BIST analysis unit comprises analysis output interfaces, and is respectively and electrically connected with N BIST test interface units and a scan chain test interface unit through the analysis output interfaces, and each BIST test interface unit is used for being connected with one test IP module;
the BIST analysis unit is respectively and electrically connected with the test clock output pin, the test data input pin, the test data output pin and the working mode output pin, receives a test clock through the test clock output pin, is electrically connected with the two multiplexing pins through the test data input pin and the test data output pin, and is used for receiving external data and output detection data, and receives a working mode selection signal through the working mode output pin;
the BIST analysis unit selects one BIST test interface unit for testing based on the working mode selection signal, and inputs a test clock to the selected BIST test interface unit and performs data interaction through the analysis output interface, wherein the data interaction comprises the step of inputting analyzed external data to the selected BIST test interface unit and the step of receiving detection data output by the selected BIST test interface unit.
In certain embodiments of the first aspect, the selected value of M needs to satisfy the following formula:
2 M ≥N+1。
in a certain implementation manner of the first aspect, the operation mode detection unit is configured to latch the operation mode based on the signal level states of the M mode setting pins at power up and output an operation mode selection signal.
In a certain implementation manner of the first aspect, the operation mode detection unit further includes a reset pin, and latches the operation mode based on signal level states of the M mode setting pins and outputs an operation mode selection signal when the reset pin inputs a reset signal for a set period of time.
In a certain implementation manner of the first aspect, after the operation mode is latched, the operation mode detection unit starts to input external data and output detection data by using two multiplexing pins.
In certain implementations of the first aspect, the external data includes start bit data, data bit data, command bit data, and end bit data;
the detection data includes start bit data, data bit data, and end bit data.
In a certain embodiment of the first aspect, the BIST test interface unit includes a BIST test clock pin, a BIST operation mode setting pin, a BIST command pin, x BIST test input pins, and y BIST test output pins, the analysis output interface of the BIST analysis unit is configured to input a test clock to the BIST test clock pin, the analysis output interface of the BIST analysis unit is configured to input a signal of a first level state to the BIST operation mode setting pin of the selected BIST test interface unit to enable the selected BIST test interface unit to be in a test operation mode, the BIST operation mode setting pin is in a normal operation mode when inputting a signal of a second level state, the first level state and the second level state are in opposite two level states, the x BIST test input pins are configured to input analyzed external data, the y BIST test output pins are configured to output external data, and x and y are positive integers, and the BIST test interface unit is configured to input the analyzed external data input to the x BIST test input pins to an IP block electrically connected thereto when in the test operation mode.
In a certain implementation manner of the first aspect, the BIST test interface unit further comprises x normal input pins, wherein the x normal input pins are used for inputting normal operation data, and the BIST test interface unit sends the normal operation data input by the x normal input pins to an IP module electrically connected with the x normal input pins when the BIST test interface unit is in a normal operation mode.
In a certain implementation manner of the first aspect, the scan chain test interface unit includes a scan clock pin, a scan input pin, a scan output pin, and a scan enable pin, the BIST analysis unit inputs an enable signal to the scan enable pin based on the operation mode selection signal, the BIST analysis unit inputs a clock signal to the scan clock pin, inputs external data to the scan input pin, receives test data through the scan output pin, and transmits the test data to the test data output pin.
In a second aspect, the present invention further provides a test system, including the above-mentioned general test structure of a digital chip, and further including a test machine, where the test machine is electrically connected to the working mode detection unit, and is configured to send external data to the working mode detection unit and receive detection data output by the working mode detection unit.
Compared with the prior art, the invention has the following beneficial effects: according to the invention, the current working mode is set by the working mode detection unit, the BIST analysis unit selects one IP module for testing according to the current working mode, and the two mode setting pins of the working mode detection unit are multiplexed, so that the number of pins for testing can be reduced, the CP testing cost is reduced, and the testing risk is reduced;
in addition, because the BIST analysis unit analyzes the external data and sends the analyzed external data to the BIST test interface unit or the scan chain test interface unit, the invention can realize two tests by only connecting one working mode detection unit with the tester, thereby realizing the unification of test interfaces and universal test.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention in an embodiment;
FIG. 2 is a schematic diagram of pins of a BIST test interface unit;
FIG. 3 is a schematic diagram of pins of a scan chain test interface unit;
FIG. 4 is a schematic diagram of the structure of external data;
fig. 5 is a schematic diagram of the structure of the detection data.
Detailed Description
The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.
As shown in fig. 1, a general test structure of a digital chip includes a working mode detecting unit 1, a BIST analyzing unit 2, a scan chain test interface unit 4, and a plurality of BIST test interface units 3; the number of the BIST test interface units 3 can be set according to the number of the IP blocks actually required to be detected, i.e. the BIST test interface units can be extended according to the actual requirements, which is not limited herein;
IN fig. 1, the operation MODE detection unit 1 includes a clock pin CLK0 for receiving a clock, a plurality of MODE setting pins for setting an operation MODE, a test clock output pin CLK10, a test data input pin IN10, a test data output pin OUT10, and an operation MODE output pin MODE, two of the plurality of MODE setting pins being multiplexing pins for inputting external data and outputting detection data, respectively;
the working MODE detection unit 1 outputs a test clock through a test clock output pin CLK10 based on the clock, outputs a working MODE selection signal through a working MODE output pin MODE based on the input signal level states of the M MODE setting pins, and the test data input pin IN10 and the test data output pin OUT10 are electrically connected with two multiplexing pins;
the BIST analysis unit 2 comprises analysis output interfaces, and is respectively and electrically connected with the N BIST test interface units 3 and the scan chain test interface unit 4 through the analysis output interfaces, and each BIST test interface unit 3 is used for being connected with one test IP module;
the BIST analysis unit 1 is respectively and electrically connected with a test clock output pin CLK10, a test data input pin IN10, a test data output pin OUT10 and a working MODE output pin MODE, receives a test clock through the test clock output pin CLK10, is electrically connected with two multiplexing pins through the test data input pin IN10 and the test data output pin OUT10, is used for receiving external data and output detection data, and receives a working MODE selection signal through the working MODE output pin;
the BIST analysis unit 1 selects one BIST test interface unit 3 for testing based on the operation mode selection signal, and inputs a test clock to the selected BIST test interface unit 3 and performs data interaction including inputting analyzed external data to the selected BIST test interface unit 3 and receiving detection data output from the selected BIST test interface unit 3 through the analysis output interface.
Specifically, in this embodiment, the number of BIST test interface units 3 may be set according to the number of IP blocks actually required to be detected, i.e. may be extended according to the actual requirement, which is not limited herein; for more complex chips, the number of the IP modules is more, in this case, the invention still only needs to connect with an external testing mechanism through the working mode detecting unit 1, then the BIST analyzing unit analyzes the external data and selects a specific IP module for testing, thereby reducing the number of pins connected with the external testing mechanism and reducing the testing cost.
Specifically, IN this embodiment, the number of mode setting pins may be determined according to the sum of the number of IP blocks to be actually tested and the number of scan chain test interface units 4, and is not limited herein, IN fig. 1, the mode setting pins include pins IN0/TST0, OUT0/TST1, and TSTN, where pins IN0/TST0 and OUT0/TST1 are multiplexing pins.
In this embodiment, the relationships of the BIST test interface unit 3, the scan chain test interface unit 4, and the mode setting pins are as follows: assuming that the number of BIST test interface units 3 is N, N is a positive integer, and assuming that the number of mode setting pins is M, M is a positive integer, the values of N and M need to satisfy the following formula:
2 M ≥N+1。
by way of example, it is assumed that only three BIST test interface units 3 and one scan chain test interface unit 4 are present, and that only two mode setting pins are required to set the operation modes of the three IP blocks, and that the three IP blocks are IP0, IP1, and IP2, respectively, and that the operation modes are required to be set according to the signal level states of the two mode setting pins, for example, IP1 may be selected for testing when the signal level state of the two mode setting pins is "00", IP2 may be selected for testing when the signal level state of the two mode setting pins is "01", IP3 may be selected for testing when the signal level state of the two mode setting pins is "10", and scan chain test interface unit 4 may be selected for testing when the signal level state of the two mode setting pins is "11". As can be seen from this example, the operation mode checking unit 1 of the present invention can use at least three pins to interact with external devices, thereby reducing the number of pins for chip test.
In the present embodiment, the process of setting the operation mode by the operation mode detection unit 1 is as follows:
first, the operation mode detection unit 1 may latch the operation mode based on the signal level state of the mode setting pin and output an operation mode selection signal when power is on.
Next, the operation mode detection unit 1 further includes a reset pin for latching the operation mode based on a signal level state of the mode setting pin when a reset signal of a set period is input to the reset pin and outputting an operation mode selection signal.
In addition, in the present embodiment, with regard to the mode setting pins for multiplexing, the operation mode detecting unit 1 starts to input external data and output detection data after latching the operation mode. IN actual use, when the setting of the working mode is completed, external data is input to the pin IN0/TST0, then is input to the BIST analysis unit 2 through the test data input pin IN10 for analysis, and the BIST analysis unit 2 sends inspection data to the external test mechanism through the test data output pin OUT10 and the pin OUT0/TST1 after receiving the detection data.
In this embodiment, the formats of the external data and the detection data are as follows: referring to fig. 4, the external data includes start bit data, data bit data, command bit data and end bit data, wherein the number of bits of the start bit data, the data bit data, the command bit data and the end bit data of the external data may be set according to actual requirements, and is not limited herein, and illustratively, the start bit data and the end bit data are four, and the four-bit start bit data and the end bit data of the external data are high level signals;
taking 20-bit external data as an example, the format is as follows: 1111_yyyy_xxxxxxxxx_1111;
wherein 1111 on the right side is a start bit, 1111 on the left side is an end bit, yyyy is a command bit (defining 4 bits), and xxxxxxx is a data bit (defining 8 bits).
Referring to fig. 5, the detection data includes start bit data, data bit data and end bit data, and exemplary, the number of bits of the start bit data, the data bit data and the end bit data of the detection data may be set according to actual requirements, and exemplary, the number of bits of the start bit data and the end bit data of the detection data are both 4, and the four-bit start bit data and the end bit data of the detection data are both high level signals;
taking 16-bit external data as an example, the format is as follows: 1111_xxxxxxx_1111;
where 1111 on the right is the start bit, 1111 on the left is the end bit, and xxxxxxxx is the data bit (8 bits are defined).
It should be noted that, when defining the lengths of the data bits of the external data and the detection data, the number of bits of the data bits needs to satisfy the number of bits of all the IP blocks.
When in actual use, the BIST analysis unit 2 analyzes the B-bit data and the C-bit command data, and thus transmits the analyzed data to the specified BIST test interface unit 3; in addition, when the working mode is set, the BIST analysis unit 2 can analyze external data according to an external data format defined in advance, and the data can be sent to the working mode detection unit 1 according to the external data format defined in advance and sent to an external test mechanism through the pin OUT0/TST1 of the working mode detection unit 1, so that the analysis of the external data can be realized only from hardware without the participation of software.
Referring to fig. 2, in the present embodiment, the BIST test interface unit 3 includes a BIST test clock pin tst_clk, a BIST operation mode setting pin ip1_tst_en, a BIST command pin ip1_bist_cmd, x BIST test input pins and y BIST test output pins, wherein the x BIST test input pins are respectively a pin ip1_in1, a pin ip1_in2 and a pin ip1_inx, and the y BIST test output pins are respectively a pin ip1_out1, a pin ip1_out2 and a pin ip1_outy;
the analysis output interface of the BIST analysis unit 2 is used for inputting a test clock to the BIST test clock pin tst_clk, the analysis output interface of the BIST analysis unit 2 is used for inputting a signal in a first level state to the BIST operation mode setting pin ip1_tst_en of the selected BIST test interface unit 3 to enable the BIST operation mode, the BIST operation mode setting pin ip1_tst_en is in a normal operation mode when inputting a signal in a second level state, the first level state and the second level state are in opposite two level states, in this embodiment, the first level state is a high level device, the second level state is in a low level state, the x BIST test input pins are used for inputting analyzed external data, the y BIST test output pins are used for outputting external data, x and y are positive integers, and the BIST test interface unit 3 inputs the analyzed external data input by the x BIST test input pins to the IP module electrically connected with the BIST test interface unit when in the test operation mode.
In practical use, the BIST analysis unit 2 inputs a high-level signal to the BIST operation mode setting pin ip1_tst_en of the corresponding BIST test interface unit 3 to enable the BIST test interface unit to be in a test operation mode, so that the selection test of all BIST test interface units 3 can be realized by only setting the corresponding mode setting pin, and the number of connection pins with an external test mechanism can be reduced. In addition, the number of BIST test input pins and BIST test output pins may be increased and decreased for different IP blocks, without limitation.
In this embodiment, the BIST test interface unit 3 further includes x normal input pins, where the x normal input pins are used for inputting normal operation data, and the BIST test interface unit 3 sends the normal operation data input by the x normal input pins to the IP module electrically connected thereto when in the normal operation mode.
By way of example, the functional definition of pins of the BIST test interface unit 3 shown in FIG. 4 can be referred to Table 1, table 1 being specifically as follows:
TABLE 1
Referring to fig. 3, IN the present embodiment, the SCAN chain test interface unit 4 includes a SCAN clock pin scan_clk, a SCAN input pin scan_in, a SCAN output pin scan_out, and a SCAN enable pin scan_en, the BIST parsing unit 2 inputs an enable signal to the SCAN enable pin scan_en based on an operation mode selection signal, the BIST parsing unit 2 inputs a clock signal to the SCAN clock pin scan_clk, inputs external data to the SCAN input pin scan_in, receives test data through the SCAN output pin scan_out, and transmits the test data to the test data output pin OUT10.
In summary, the present invention sets the current working mode by setting the working mode detecting unit 1, and makes the BIST analyzing unit 2 select an IP module for testing according to the current working mode, and makes two mode setting pins of the working mode detecting unit 1 multiplex, thereby reducing the pin number for testing, further reducing CP testing cost and reducing testing risk;
in addition, the external data is analyzed through the BIST analysis unit 2 and the analyzed external data is sent to the BIST test interface unit 3 or the scan chain test interface unit 4, so that two tests can be realized only by connecting one working mode detection unit 1 with a tester, further, the unification of test interfaces is realized, and the universal test is realized.
In a second aspect, the present invention further provides a test system, including a general test structure of a digital chip as described above, and further including a test machine (ATE), where the test machine is electrically connected to the operation mode detection unit 1, and is configured to send external data to the operation mode detection unit 1 and receive detection data output by the operation mode detection unit 1.
The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.
Claims (10)
1. The universal test structure of the digital chip is characterized by comprising a working mode detection unit, a BIST analysis unit, a scan chain test interface unit and N BIST test interface units, wherein N is a positive integer;
the working mode detection unit comprises a clock pin for receiving a clock, M mode setting pins for setting a working mode, a test clock output pin, a test data input pin, a test data output pin and a working mode output pin, M is a positive integer greater than 1, and two mode setting pins in the M mode setting pins are multiplexing pins for inputting external data and outputting detection data respectively;
the working mode detection unit outputs a test clock through the test clock output pin based on the clock, outputs a working mode selection signal through a working mode output pin based on the input signal level states of the M mode setting pins, and the test data input pin and the test data output pin are electrically connected with the two multiplexing pins;
the BIST analysis unit comprises analysis output interfaces, and is respectively and electrically connected with N BIST test interface units and a scan chain test interface unit through the analysis output interfaces, and each BIST test interface unit is used for being connected with one test IP module;
the BIST analysis unit is respectively and electrically connected with the test clock output pin, the test data input pin, the test data output pin and the working mode output pin, receives a test clock through the test clock output pin, is electrically connected with the two multiplexing pins through the test data input pin and the test data output pin, and is used for receiving external data and output detection data, and receives a working mode selection signal through the working mode output pin;
the BIST analysis unit selects one BIST test interface unit for testing based on the working mode selection signal, and inputs a test clock to the selected BIST test interface unit and performs data interaction through the analysis output interface, wherein the data interaction comprises the step of inputting analyzed external data to the selected BIST test interface unit and the step of receiving detection data output by the selected BIST test interface unit.
2. The universal test structure of a digital chip according to claim 1, wherein the selected value of M is required to satisfy the following formula:
2 M ≥N+1。
3. the universal test structure of a digital chip according to claim 1, wherein the operation mode detecting unit is configured to latch the operation mode based on signal level states of the M mode setting pins at power up and output an operation mode selection signal.
4. A universal test structure for a digital chip according to any of claims 1 to 3, wherein the operation mode detecting unit further comprises a reset pin for latching an operation mode and outputting an operation mode selection signal based on signal level states of the M mode setting pins when the reset pin inputs a reset signal of a set period of time.
5. The universal test structure of a digital chip as claimed in claim 4, wherein the operation mode detecting unit starts to input external data and output detection data by two multiplexing pins after latching the operation mode.
6. The universal test structure of a digital chip according to claim 1, wherein the external data comprises start bit data, data bit data, command bit data, and end bit data;
the detection data includes start bit data, data bit data, and end bit data.
7. The universal test structure of a digital chip according to claim 1, wherein the BIST test interface unit comprises a BIST test clock pin, a BIST operation mode setting pin, a BIST command pin, x BIST test input pins, and y BIST test output pins, the parse output interface of the BIST parse unit is used for inputting a test clock to the BIST test clock pin, the parse output interface of the BIST parse unit is used for inputting a signal of a first level state to the BIST operation mode setting pin of the selected BIST test interface unit to be in a test operation mode, the BIST operation mode setting pin is in a normal operation mode when inputting a signal of a second level state, the first level state and the second level state are in opposite two level states, the x BIST test input pins are used for inputting parsed external data, the y BIST test output pins are used for outputting external data, and x and y are positive integers, and the BIST test interface unit inputs the parsed external data input to the x BIST test input pins to an IP block electrically connected thereto when in the test operation mode.
8. The universal test architecture for a digital chip as set forth in claim 7, wherein said BIST test interface unit further comprises x normal input pins for inputting normal operation data, said BIST test interface unit transmitting the normal operation data input by the x normal input pins to an IP block electrically connected thereto when in a normal operation mode.
9. The universal test structure of a digital chip according to claim 1, wherein the scan chain test interface unit includes a scan clock pin, a scan input pin, a scan output pin, and a scan enable pin, the BIST analysis unit inputs an enable signal to the scan enable pin based on the operation mode selection signal, the BIST analysis unit inputs a clock signal to the scan clock pin, inputs external data to the scan input pin, receives test data through the scan output pin, and transmits the test data to the test data output pin.
10. A test system comprising a universal test structure for a digital chip according to any one of claims 1-9, and further comprising a tester electrically connected to the operation mode detection unit for sending external data to the operation mode detection unit and receiving detection data output from the operation mode detection unit.
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2023
- 2023-11-09 CN CN202311491948.7A patent/CN117517937A/en active Pending
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