KR100303444B1 - Thin film transistor substrate for liquid crystal display and a manufacturing method thereof - Google Patents

Abstract

In a thin film transistor substrate for a liquid crystal display device, a gate line and a common electrode line extend in a horizontal direction on the substrate, a common electrode branch line and a shielding pattern are formed in a vertical direction, and an insulating film is stacked thereon. A pixel electrode having a data line extending in the vertical direction and having branch lines parallel to the data line is formed on the insulating layer, and a connection pattern for connecting the shielding pattern with the gate line at the front end is formed. At this time, the shielding pattern is disposed between the data line and the pixel electrode branch line, and the connection pattern is in contact with the shielding pattern and the gate line through a contact hole formed in the insulating film. The shielding pattern may partially overlap the pixel electrode branch line. In this way, the shielding pattern can be used as the storage capacitor electrode while preventing the interference between the data line and the pixel electrode.

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method thereof {THIN FILM TRANSISTOR SUBSTRATE FOR LIQUID CRYSTAL DISPLAY AND A MANUFACTURING METHOD THEREOF}

The present invention relates to a liquid crystal display device and a method for manufacturing the same, and more particularly, to a liquid crystal display device and a method for manufacturing the same in which a common electrode and a pixel electrode are formed on the same substrate.

As a method of arranging the common electrode and the pixel electrode in a method of forming the common electrode and the pixel electrode on the same thin film transistor substrate, there are a method of arranging the common electrode adjacent to the data line and a method of arranging the pixel electrode adjacent to the data line. However, while the size of the pixel varies according to the specification of the panel, the pixel electrode and the common electrode must be arranged at regular intervals to generate an appropriate electric field. Therefore, in order to increase the aperture ratio, the pixel electrode should be disposed adjacent to the data line. There is.

However, in the case where the pixel electrode is disposed adjacent to the data line, signal interference (coupling) occurs between the two to reduce the image quality.

An object of the present invention is to block mutual interference between a data line and a pixel electrode due to an increase in an aperture ratio in a liquid crystal display device having a common electrode and a pixel electrode formed on a same substrate.

Another object of the present invention is to increase the storage capacitance between the common electrode and the pixel electrode.

Another object of the present invention is to minimize the occurrence of defects due to disconnection of the gate line or the common electrode line.

1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1;

3 is a cross-sectional view taken along line III-III 'of FIG. 1,

4A and 5A are cross-sectional views taken along line II-II 'of FIG. 1 according to a manufacturing process sequence.

4B and 5B are cross-sectional views taken along line III-III ′ of FIG. 1 according to a manufacturing process sequence.

6 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view taken along line VII-VII 'of FIG. 6,

8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention.

9 is a cross-sectional view taken along line VII-VII 'of FIG. 8,

10A and 10B are cross-sectional views taken along line VII-VII 'of FIG. 9 according to a manufacturing process sequence.

11 is an equivalent circuit diagram of a thin film transistor substrate for a liquid crystal display according to a fourth embodiment of the present invention.

In order to solve the above technical problem, the present invention forms a shielding pattern between the data line and the pixel electrode adjacent to the data line and insulated from the data line and connected to the gate line of the front end.

In addition, the shielding pattern connecting line may be connected to the same pad as the gate line of the front end, and may form a repair line that crosses one end of the common electrode line to which the common electrode connecting line is not connected.

Alternatively, the common electrode may be formed in a shape where the rings are continuously connected, and the edge thereof may pass between the data line and the pixel electrode adjacent to the data line.

Specifically, a gate line is formed on the substrate, the gate electrode is connected to the gate line, the common electrode line is formed separately from the gate line on the substrate, and the common electrode branch line is connected to the common electrode line. The insulating film covers the gate line, the gate electrode, the common electrode line, and the common electrode branch line, and a data line intersecting the gate line is formed on the insulating film, and a plurality of pixel electrode branch lines alternately arranged with the common electrode branch line on the insulating film. Is formed, and the pixel electrode main body which connects the pixel electrode branch line by one is formed. A pixel layer formed on the insulating film on the gate electrode, a source electrode connected to the data line and the semiconductor layer, a drain electrode connected to the pixel electrode body and the semiconductor layer, and adjacent to the data line; A shielding pattern is formed between the substrate and the insulating film between the data lines. The connection pattern connects the shielding pattern with the gate line of the front end.

Here, the shielding pattern may partially overlap the pixel electrode and may be connected as one by a connection line. When the shielding pattern is connected by a connection line, only a part of the shielding pattern may be connected to the gate line of the front end.

Alternatively, a gate line is formed on the substrate in a vertical direction, the data line is insulated from and intersects with the gate line, and the pixel area is defined as an area where two rows of gate lines and data lines cross each other. The pixel electrode has branch lines parallel to the edges and data lines formed along the periphery of the pixel area, and the common electrode is formed in a continuous ring shape between the gate lines, and the edges and data lines passing between the edges of the data line and the pixel electrode. The thin film transistor has parallel branch lines and is insulated from the pixel electrode and the data line, and the thin film transistor is formed of a source electrode connected to the data line, a drain electrode connected to the pixel electrode, a semiconductor layer, and the like.

The edge of the common electrode may partially overlap the pixel electrode or the data line.

In addition, the gate line extends in the horizontal direction on the substrate, and the shielding pattern connecting line is formed in parallel with the gate line and connected to the same pad as the gate line of the previous stage, and the data line is insulated from the gate line and the shielding pattern connecting line in the vertical direction. A shielding pattern is connected to the shielding pattern connecting line, and the connecting pattern extends from the upper part of the part of the shielding pattern to the upper part of the gate line of the front end. The common electrode line having the common electrode is formed in parallel with the gate line, the common electrode connecting line connects one end of the common electrode line, and the repair that the common electrode connecting line of the common electrode line intersects with one end which is not connected. A line is formed.

The common electrode line may be connected to the repair line.

The thin film transistor substrate for a liquid crystal display device may include forming a gate line, a common electrode line, a common electrode branch line, and a shielding pattern on the substrate, forming an insulating layer covering the gate line, the common electrode line, the common electrode branch line, and the shielding pattern; Forming first and second semiconductor layers in the insulating film, forming contact holes in the insulating film over the shielding pattern and the gate line, and forming a data line, a pixel electrode, a source electrode, a drain electrode, and a connection pattern on the insulating film , By etching and separating the second semiconductor layer and forming a protective film.

An embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, the structure of the liquid crystal display according to the first embodiment of the present invention will be described with reference to FIGS. 1 to 3. 1 is a layout view of a thin film transistor substrate for a liquid crystal display according to a first exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line II-II ′ of FIG. 1, and FIG. 3 is a line III-III ′ of FIG. 1. The cross section for

The gate line 110 is formed in the horizontal direction on the substrate 10, and the common electrode line 120 parallel to the gate line 110 is formed adjacent to the gate line 110, and the common electrode branch line 121 is common. It extends at right angles from the electrode line 120. An isolated electrostatic shielding pattern 13 is formed on the substrate 10 in parallel with the common electrode branch line 121. The insulating film 140 is formed on the gate line 110, the common electrode line 120, the shielding pattern 13, and the like, and the data line 160 extends in the vertical direction on the insulating film 140. The electrode 180, the connection pattern 17 connecting the shielding pattern 13 and the gate line 110, and the amorphous silicon layer 151 forming the thin film transistor are formed.

One pixel area is defined as an area where two adjacent rows of the gate line 110 and the data line 160 intersect, and one pixel area includes a gate electrode 111 and a gate electrode 111 that are part of the gate line 110. On the doped amorphous silicon layer 152 and the doped amorphous silicon layer 152 which are separated on both sides of the amorphous silicon layer 151 forming an island on the gate insulating layer 140, A thin film transistor and data including a source electrode 161 formed on a branch of the data line 160 and a drain electrode 182 formed on the doped amorphous silicon layer 152 and connected to the pixel electrode 180. One pixel electrode 180 having branch lines 181 extending parallel to the line 160 is formed.

The pixel electrode branch lines 181 and the common electrode branch lines 121 are alternately arranged at regular intervals, and the left and right pixel electrode branch lines 181 are formed adjacent to the data line 160. A shielding pattern 13 is formed between the data line 160 and the left and right pixel electrode branch lines 181 to block interference between the data line 160 and the pixel electrode branch lines 181. In this case, the shielding pattern 13 may be formed to partially overlap the pixel electrode branch line 181. The shielding pattern 13 is electrically connected to the front gate line 110 by the connection pattern 17. To this end, contact holes 141 and 142 are formed in the insulating layer 140. In this way, the shielding pattern 13 can also serve as a storage capacitor electrode. The passivation layer 19 is stacked on the data line 160, the pixel electrode 180, and the like.

A method of manufacturing a liquid crystal display according to a first embodiment of the present invention will now be described with reference to FIGS. 4A to 5B. 4A and 5A are cross-sectional views taken along line II-II 'of FIG. 1 according to a manufacturing process sequence, and FIGS. 4B and 5B are cross-sectional views taken along line III-III' of FIG. 1 according to a manufacturing process sequence. The figure shown.

First, as shown in FIGS. 4A and 5A, a metal layer is stacked and patterned on a transparent substrate 10 such as glass to form a gate line 110, a common electrode line 120, a common electrode branch line 121, and a shielding pattern. 13, the insulating film 140, the amorphous silicon layer 151, and the amorphous silicon layer 152 heavily doped with N-type impurities are sequentially stacked and then patterned to form an insulating film on the gate line 110. An island of an amorphous silicon layer 151 and a doped amorphous silicon layer 152 is formed on the 140.

Next, as illustrated in FIGS. 4B and 5B, contact holes 141 and 142 are formed in the shielding pattern 13 and the insulating layer 140 on the gate line 110, and the metal layers are stacked and patterned to form the data line 160. The source electrode 161, the drain electrode 182, the connection pattern 17, and the pixel electrode 180 are formed.

Next, the doped amorphous silicon layer 152 is etched using both the source electrode 161 and the drain electrode 182 as a mask, separated into two sides, and a protective film 19 is stacked.

Now, the structure of the liquid crystal display according to the second embodiment of the present invention will be described. FIG. 6 is a layout view of a thin film transistor substrate for a liquid crystal display according to a second exemplary embodiment of the present invention, and FIG. 7 is a cross-sectional view taken along the line 'VIII' of FIG. 6.

The gate electrode 21 extends in the horizontal direction on the substrate 20, and a common electrode 220 is formed in which a ring is continuously connected between the gate lines 210. An insulating film 24 is formed on the gate line 210 and the common electrode 220, a data line 260 extending in the vertical direction on the insulating film 24, and a pixel electrode 280 in which two rings are connected. ), An amorphous silicon layer 251 constituting the thin film transistor is formed. In this case, the pixel electrode 280 may be formed in a form in which three or more rings are connected.

The doped amorphous silicon layer 252 is formed on both sides of the amorphous silicon layer 251, and the drain electrode 282 and the data line are connected to the pixel electrode 280 on the doped amorphous silicon layer 252. A source electrode 261 which is a branch of 260 is formed.

The branch lines 221 and the pixel electrode branch lines 281 forming the ring of the common electrode 220 are formed in parallel with the data lines and are alternately arranged at regular intervals. The left and right edges of the pixel electrode 280 are It is arranged adjacent to the data line 260. The common electrode 220 is formed between the data line 260 and the left and right edges of the pixel electrode 280 to function as an electrostatic shielding pattern. The common electrode 220 is formed below the data line so that the center thereof is empty so that the common electrode 220 is divided into pixel regions, and the area of the common electrode 220 overlapping the data line 260 is reduced to reduce the data line. Voltage 260 is reduced from being affected by common electrode 220 voltage.

The passivation layer 29 is stacked on the data line 260, the pixel electrode 280, and the like.

The structure of the liquid crystal display according to the third embodiment of the present invention will be described. FIG. 8 is a layout view of a thin film transistor substrate for a liquid crystal display according to a third exemplary embodiment of the present invention, and FIG. 9 is a cross-sectional view taken along the line 'VIII' of FIG. 8.

The gate line 310 extends in the horizontal direction on the substrate 30, and the common electrode line 320 and the shielding pattern connecting line 330 are formed parallel to the gate line 310, and the common electrode branch line is formed on the common electrode line 320. In the shielding pattern connecting line 330, the shielding pattern 331 is formed as a branch 321. An insulating film 340 is formed on the gate line 310, the common electrode line 320, the shielding pattern 331, and the like, and the data line 360 and the data line 360 extending in the vertical direction on the insulating film 340. ) Is formed with a pixel electrode 380 having branch lines 381 parallel to each other, a connection pattern 37 connecting the shielding pattern 331 with the gate line 310, an amorphous silicon layer 351 forming a thin film transistor, and the like. It is.

In one pixel area defined as an intersection area between two adjacent rows of the gate line 310 and the data line 360, a gate insulating film (a gate electrode 311 which is a part of the gate line 310 and a gate insulating layer on the gate electrode 311) may be formed. 340 is formed on the amorphous silicon layer 351 forming an island, the doped amorphous silicon layer 352 formed on both sides of the amorphous silicon layer 351, and the doped amorphous silicon layer 352. One thin film transistor and one pixel electrode formed of a source electrode 361 which is a branch of the line 360 and a drain electrode 382 formed on the doped amorphous silicon layer 352 and connected to the pixel electrode 380. 380 is formed.

The pixel electrode branch lines 381 and the common electrode branch lines 321 are alternately arranged at regular intervals, and the left and right pixel electrode branch lines 381 are formed adjacent to the data line 360. A shielding pattern 331 is disposed between the data line 360 and the left and right pixel electrode branch lines 381 so as to block interference between the data line 360 and the pixel electrode branch lines 381.

In this case, the blocking pattern 331 may be formed to overlap a portion of the pixel electrode branch line 381, and the right blocking pattern 331 is connected to the front gate line 310 by the connection pattern 37. . Contact holes 341 and 342 are formed in the right blocking pattern 331 and the insulating layer 340 on the gate line 310 to contact the connection pattern 37. Here, the two contact holes 341 and 342 may not be formed. In this case, the connection pattern 37 may be formed by irradiating a laser only when the gate line 310 is disconnected after the thin film transistor substrate is manufactured. The gate line 310 may be repaired by contacting the blocking pattern 331 and the gate line 310.

In addition, since the shielding pattern connecting line 330 and the common electrode line 320 are connected at regular intervals, defects due to disconnection of the common electrode line 320 may be reduced.

The passivation layer 39 is formed on the data line 360, the pixel electrode 380, the connection pattern 37, and the like.

A method of manufacturing a liquid crystal display device according to a third embodiment of the present invention will be described. 10A and 10B are cross-sectional views taken along line VII-VII 'of FIG. 8 according to a manufacturing process sequence.

First, as shown in FIG. 10A, the metal layer is stacked and patterned on the transparent substrate 30 to form a gate line 310, a common electrode line 320, branch lines 321, a shielding pattern 331, and a shielding pattern connecting line 330. After forming the insulating film 340, the amorphous silicon layer 351, and the doped amorphous silicon layer 352 are sequentially stacked and patterned on the insulating film 340 on the gate line 310 and the amorphous silicon layer 351 and An island of doped amorphous silicon layer 352 is formed.

Next, as shown in FIG. 10B, contact holes 341 and 342 are formed in the insulating film 340 on the upper right shielding pattern 331 and the upper gate line 310, and then a metal layer is stacked and patterned on the insulating film 340. The data line 360, the source electrode 361, the pixel electrode 380 and the drain electrode 382, and the connection pattern 37 are formed. In this case, the step of forming the contact holes 341 and 342 may be omitted or only one of the two contact holes 341 and 342 may be formed.

Subsequently, the doped amorphous silicon layer 352 is etched using both the source electrode 361 and the drain electrode 382 as a mask to be separated on both sides, and then a protective film 39 is formed.

Now, the present invention describes a means for reducing the defect caused by disconnection of the gate line 310 or the common electrode line 320. 11 is an equivalent circuit diagram of a thin film transistor substrate for a liquid crystal display according to a fourth embodiment of the present invention.

As shown in Fig. 11, the arrangement of each pixel region is the same as that of the liquid crystal display device according to the third embodiment. Here, the shielding pattern connecting line 330 is connected to the same pad 311 as the gate line 310 of the previous stage, and the right shielding pattern 331 of each pixel area is connected to the gate of the preceding stage by the connecting pattern 37. The shielding pattern connecting line 330 may compensate for the disconnected portion A of the gate line 310 because it is connected to the line 310.

In this case, the connection pattern 37 extends from the right shielding pattern 331 to the upper portion of the gate line 310 of the front end, but may not be connected to them. In this case, the connection pattern 37 is connected to the gate line 310 and the shielding pattern 331 at the front end by using a laser only when the gate line 310 at the front end is disconnected.

In addition, the common electrode line is formed by forming a repair line 420 connected to the redundant pad 421 on the opposite side of the substrate on which the common electrode connecting line 410 connecting the common electrode line 320 to the common electrode pad 411 is formed. A portion B of 320 can be prepared for disconnection. That is, when a part B of the common electrode line 320 is disconnected, the common electrode line 320 and the repair line 420, which are disconnected using a laser, are connected (C) and a common potential is applied to the redundant pad 421. As a result, even when the common electrode line 320 is disconnected, a defect may be prevented from occurring. At this time, the common electrode line 320 may be connected to the repair line 420 from the beginning.

As described above, by forming the electrostatic shielding pattern, interference between the data line and the pixel electrode can be prevented, the shielding pattern can be utilized as the storage capacitor electrode, and the shielding pattern connecting line can be used as the auxiliary gate line to prepare for the gate line disconnection. have. In addition, by forming a repair line, it is possible to prepare for disconnection of the common electrode line.

Claims (16)

A gate line formed on the substrate, A gate electrode connected to the gate line, A common electrode line formed on the substrate to be parallel to the gate line and separated from the gate line; A plurality of common electrode branch lines connected to the common electrode line, An insulating film covering the gate line, gate electrode, common electrode line, and common electrode branch line, A data line formed on the insulating film and crossing the gate line; A plurality of pixel electrode branch lines formed on the insulating layer and alternately arranged with the common electrode branch lines; A pixel electrode main body connecting the pixel electrode branch lines to one; A semiconductor layer formed on the insulating film over the gate electrode, A source electrode connected to the data line and the semiconductor layer; A drain electrode separated from the source electrode and connected to the pixel electrode body and the semiconductor layer; A shielding pattern formed between the substrate and the insulating film between the pixel electrode branch line and the data line adjacent to the data line; And a connection pattern connecting the shielding pattern to the gate line of a previous stage. In claim 1, The shielding pattern is a thin film transistor substrate for a liquid crystal display device in which a portion of the pixel electrode branch line overlaps. The method of claim 1 or 2, And the connection pattern is formed on the insulating film and is in contact with the shielding pattern and the gate line of the front end through a contact hole formed in the insulating film. In claim 1, And a shielding pattern connecting line connecting the shielding patterns as one. In claim 4, The shielding pattern is a thin film transistor substrate for a liquid crystal display device in which a portion of the pixel electrode branch line overlaps. In claim 4, The thin film transistor substrate for the liquid crystal display device wherein the shielding pattern connection line and the common electrode connection line are connected at regular intervals. In any one of claims 4, 5 and 6, The connection pattern is a thin film transistor substrate for a liquid crystal display device to connect the gate line of the front end only one crossing the shielding pattern. A gate line formed on the substrate, A gate electrode that is part of the gate line, An insulating film formed over the gate line, A data line formed on the insulating film and crossing the gate line; A pixel area defined as an area formed by crossing the two adjacent gate lines with the data line; A pixel electrode having an edge formed along a circumference of the pixel area and a branch line parallel to the data line; A common electrode formed between the gate lines in a continuous ring shape, the common electrode having an edge passing between the edge of the data line and the pixel electrode and branch lines parallel to the data line, and insulated from the pixel electrode or the data line; A semiconductor layer formed over the insulating film on the gate electrode; A source electrode connected to the semiconductor layer and the data line; A drain electrode connected to the semiconductor layer and the pixel electrode, A thin film transistor substrate for liquid crystal display devices having a. In claim 8, The edge of the common electrode passing between the data line and the edge of the pixel electrode overlaps a portion of the edge of the pixel electrode. The method of claim 8 or 9, The edge of the common electrode passing between the data line and the edge of the pixel electrode partially overlaps the data line. A gate line extending horizontally on the substrate, A storage capacitor electrode connection line formed to be parallel to the gate line and connected to the same pad as the gate line at the front end; A data line insulated from the gate line and the storage capacitor electrode line and extending in a vertical direction; A common electrode line formed to be parallel to the gate line; A plurality of common electrode branch lines which are branches of the common electrode line, A plurality of pixel electrode branch lines alternately arranged with the common electrode branch line; A pixel electrode main body connecting the pixel electrode branch lines to one; A storage capacitor electrode connected to the storage capacitor electrode connection line so as to be parallel to the data line and partially overlapping the pixel electrode branch line; A connection pattern extending from an upper portion of a portion of the storage capacitor electrode to an upper portion of a gate line of the front end; A common electrode connecting line connecting one end of the common electrode line, And a repair line intersecting with one end of said common electrode line not connected to said common electrode connection line. In claim 11, The connection pattern is a thin film transistor substrate for a liquid crystal display device connecting a portion of the storage capacitor electrode and the gate line of the front end. The method of claim 11 or 12, The repair line is a thin film transistor substrate for a liquid crystal display device connecting the common electrode line as one. Forming a gate line, a common electrode line, a common electrode branch line, and a shielding pattern on the substrate; Forming an insulating layer covering the gate line, the common electrode line, the common electrode branch line, and the shielding pattern; Forming first and second semiconductor layers on the insulating film, Forming a contact hole in the insulating layer on the shielding pattern and the gate line; Forming a data line, a pixel electrode, a source electrode, a drain electrode, and a connection pattern on the insulating layer; Etching and separating the second semiconductor layer; A method of forming a thin film transistor substrate for a liquid crystal display device comprising the step of forming a protective film. The method of claim 14, And forming wirings for connecting the shielding pattern in the step of forming the gate line and the like. In claim 11, The storage capacitor electrode is a thin film transistor substrate for a liquid crystal display device having a function of blocking the interference phenomenon between the data line and the pixel electrode.