KR100302097B1 - Channel card circuit for base station in wll system - Google Patents

Abstract

PURPOSE: A channel card circuit for base station in a WLL(Wireless Local Loop) system is provided to process three sectors having capacity of four channels by using one sector modem. CONSTITUTION: The first to the fourth MUXs(11-0 to 11-3) select one sector having an input signal from selectors of an IF conversion card. The first to the fourth modems(12-0 to 12-3) modulates ADPCM data in a forward link process or demodulates output data of the first to the fourth MUXs(11-0 to 11-3) in a backward link process. The first to the fourth Viterbi decoders(13-0 to 13-3) performs a decoding operation for the modulated data of the first to the fourth modems(12-0 to 12-3). A channel processing portion(10) is formed with the first to the fourth MUXs(11-0 to 11-3), the first to the fourth modems(12-0 to 12-3), and the first to the fourth Viterbi decoders(13-0 to 13-3). A processor(20) and a control portion(30) control the channel processing portion(10). A memory portion(40) and a DPRAM(50) store temporary data generated from control operations of the processor(20) and the control portion(30). An HDLC controller(60) receives or transmits a control signal from or to a route and a control card. A combiner portion(70) divides the modulated data of the first to the fourth modems(12-0 to 12-3) into three sectors. A summing portion(80) sums up output data of each sector and outputs the result to the IF conversion card.

Description

Channel card circuit for base station of wireless subscriber network system

The present invention utilizes one sector modem in a base station of a wireless local loop (WLL) system employing a wideband-code division multiple access (CDMA) scheme. The present invention relates to a channel card circuit for a base station of a WLL system capable of processing three sectors (?,?,?) Of four channel capacities.

In general, the WLL system is a technology for constructing a telephone line using a wireless system instead of a wired line connecting a telephone subscriber's premises to a subscriber's premises. A radio interface unit, a base station (Radio Port) for establishing a wireless link with the subscriber access apparatus by wired connection with a telephone switching center, and a base station controller (Radio Port Controller) for controlling the base station.

On the other hand, the base station is provided with a channel card for performing a call processing, and the interface from the IF (Intermediate Frequency) conversion card (IF) from the forward link (Forward Link) or reverse link (Reverse Link) from the IF conversion card Send and receive digitally sampled signals.

It also exchanges voice-coded data and graphics-related information with a Route & Control Card, and also controls information related to call formation, truncation, and handoff with a cell controller.

As shown in FIG. 1, a channel card which performs the above-described main functions includes a channel element 1 composed of controllers 1-4 to 1-7 and modem units 1-8 to 1-11. -0 to 1-3, a processor 2 and a controller 4 for controlling the operation of the channel elements 1-0 to 1-3, a memory unit 3, and a DPRAM ( 5) a combiner unit 7 for combining the signals output from the HDLC controller 6 and the modem units 1-8 to 1-11 in the channel elements 1-0 to 1-3. And a D / A converter 8 for converting the digital signal output from the combiner unit 7 into an analog signal and outputting it to an IF conversion card, which is used in a CDMA communication system.

However, the channel card circuit having the above structure has the channel elements 1-0 to 1-3 for controlling the processor 2 and the modem units 1-8 to 1-11 for controlling the entire channel card circuit. As the controllers 1-4 to 1-7 are provided in the control panel, the control of the channel card is processed in a double manner, and the structure of the channel card as well as the control process are complicated.

In addition, since the data modulated by the modem units 1-8 to 1-11 must be transmitted to the vocoder through the HDLC controller 6, the interface with the route and the control card is very complicated, and the modem units 1-8 to 1 Since the demodulated data in -11) is converted into an analog signal and transmitted to the IF conversion card, there is a problem of high error occurrence.

In addition, the conventional channel card has a problem that it takes a lot of cost as using the chip of Qualcomm processing three sectors.

The present invention has been made to solve the above problems, the object of which is controlled by one processor to transmit the modulated data from the modem unit directly to the route and control card via the E1 line, and demodulated data Channels for base stations in WLL systems can be aggregated and transferred to an IF conversion card to enable high-speed data transmission and reduce error rates, and can handle 4 channels even with a modem that has a mux to process a single sector. It is to provide a card circuit.

The channel card circuit for the base station of the WLL system of the present invention to achieve this object modulates the ADPCM data of the route and control card input from the modem through the E1 line interface in the forward link and then modulates the IPC through the combiner. When the Q channel data is divided into three sectors, the summation unit adds the output data of the separated sectors and outputs them to the IF conversion card. In reverse linking, α, β, Only one sector having an input signal among the sectors is selected, and after demodulating the data of the selected sector through a modem, the Viterbi decoder decodes the demodulated data and outputs the directly to the route and control card. It is done.

1 is a view showing the structure of a channel card circuit used in a conventional CDMA system,

2 is a view showing a structure of a channel card circuit for a base station of a wireless subscriber network system according to the present invention.

3 is a view showing a structure of a channel card circuit used in a forward link;

4 shows the structure of a channel card circuit used in the reverse link.

<Description of the symbols for the main parts of the drawings>

10: channel processing unit 11-0 to 11-3: mux 0 to mux 3

12-0 to 12-3 Modem 0 to Modem 3 13-0 to 13-3 Viterbi decoder 0 to Viterbi decoder 3

20 processor 30 control unit

40: memory unit 50: dipram

60: HDLC controller 70: combiner unit

80: adding part

Hereinafter, with reference to the accompanying drawings will be described in detail the configuration and operation of the base station channel card circuit of the WLL system according to the present invention.

FIG. 2 is a block diagram of a channel card circuit for a base station of a WLL system according to the present invention, wherein mux0 to mux3 (selecting only one sector having an input signal among the alpha, beta and gamma sectors output from an IF conversion card). 11-0 to 11-3) and demodulate the ADPCM data output from the route and control card in the forward link or the data selected and output from the mux 0 to mux 3 (11-0 to 11-3) in the reverse link. Viterbi Decoder 0 to Viterbi decoder for decoding the demodulated data of Modem 0 to Modem 3 (12-0 to 12-3) and Modem 0 to Modem 3 (12-0 to 12-3). A channel processor 10 comprising three (13-0 to 13-3), a processor 20 and a controller 30 for controlling the channel processor 10, and a processor 20 and a controller 30 Sends a control signal to the memory unit 40 and the dipram 50 for storing temporary data generated during a control operation, and to a route and a control card. The combiner unit 70 combines the HDLC controller 60, the data modulated by the modems 0 through 3 (12-0 through 12-3) in the channel processing unit 10 into three sectors, and And a summing section 80 for summing output data of each sector separated by the combiner section 70 and outputting the sum data to the IF conversion card.

The channel card circuit for the base station of the WLL system of the present invention configured as described above is configured as shown in FIGS. 3 and 4 in the forward link and the reverse link, respectively.

That is, the channel card circuit in the forward link includes modems 0 to modem 3 (12-0 to 12-3) for modulating ADPCM data output from the route and control card, and modems 0 to modem 3 (12-0 to 12). Combiner 0 to combiner 2 (70-0 to 70-2) for separating and outputting the I and Q channel data modulated in -3) into three sectors, and combiner 0 to combiner 2. And a summation section 0 through a summation section 2 (80-0 through 80-2) for summing output data of the sectors separated and outputted at (70-0 through 70-2) and outputting them to the IF conversion card.

The channel card circuit in the reverse link inputs alpha, beta, gamma sector signals output from the IF conversion card through transceivers 0 to 5 (14-0 to 14-5), and then buffers 0 to buffer 5 (15). Mux 0 to mux 3 (11-0 to 11-3) for selecting only one sector having an input signal among the alpha, beta and gamma sectors output through -0 to 15-5), and the mux 0 to mux 3 In modems 0 to modem 3 (12-0 to 12-3) for demodulating data selected and outputted in (11-0 to 11-3), and for modems 0 to modem 3 (12-0 to 12-3). And Viterbi decoder 0 to Viterbi decoder 3 (13-0 to 13-3) for decoding the demodulated data and outputting the decoded data to the route and the control card.

The operation of the channel card circuit for the base station of the WLL system of the present invention configured as described above is divided into a forward link and a reverse link as follows.

In the forward link, first, modems 0 to 3 (12-0 to 12-3) in the channel processing unit 10 input and modulate ADPCM data serially output from the route and control card through the E1 line interface.

At this time, 10 bits of I and Q channel data are output for each modem 0 to modem 3 (12-0 to 12-3).

Subsequently, in combiner 0 to combiner 2 (70-0 to 70-2), the I and Q channel data modulated by the modem 0 to modem 3 (12-0 to 12-3) are separated into three sectors. To print.

Then, the summation section 0 to summation section 2 (80-0 to 80-2) add up the output data of each sector separately output from the combiner 0 to combiner 2 (70-0 to 70-2). 4 bits per sector are output to the IF conversion card.

In this case, the four bits each represent two bits of I and Q channels, and each channel is composed of odd bits and even bits to form two bits.

Next, in the reverse link, mux 0 to mux 3 (11-0 to 11-3) in the channel processing section 10 are transmitted from two antennas, and then transceiver 0 to transceiver 5 (14-0 to 14-5). Input the α, β, γ sector signal output from the IF conversion card through the following, and as long as the input signal of the α, β, γ sector output through the buffer 0 to buffer 5 (15-0 to 15-5) is loaded. Only sectors are selected and output to one of four modems 0 to 3 (12-0 to 12-3).

At this time, the mux 0 to mux 3 (11-0 to 11-3) inputs 24 bits for each sector, and outputs one sector 24 bits under the control of the processor 20.

Subsequently, modems 0 to 3 (12-0 to 12-3) demodulate data output from one sector selected from three sectors.

Then, the data demodulated by the modems 0 through modem 3 (12-0 through 12-3) is decoded through the Viterbi decoder 0 through Viterbi decoder 3 (13-0 through 13-3) to the route and control card. Output

At this time, the decoded signal is directly output to the route and the control card through the E1 line interface without being controlled by the processor 20.

As described above, according to the present invention, the control and channel structure of the present invention can be simplified by using a single processor, and the modulation data can be directly transmitted to the route and control card through the E1 line, and the demodulation data can be digitally summed to form an IF conversion card. The high speed data transmission and the error rate can be reduced, and the MUX and the single sector modem can be used to process more than three sectors and four channels.

In addition, the channel card circuit of the present invention is easy to build a network, and has a merit that it is shorter in duration and cost than a conventional wireless network. I think it will be used.

Claims (3)

Mux 0 to mux 3 (11-0 to 11-3), which selects only one sector among the α, β, and γ sectors output from the IF conversion card, and ADPCM data output from the route and control card in the forward link. Modems 0 to modem 3 (12-0 to 12-3) and modems 0 to modem for demodulating or demodulating data selected and output from the mux 0 to mux 3 (11-0 to 11-3) at the reverse link. A channel processing section (10) comprising Viterbi decoders 0 to Viterbi decoders 3 (13-0 to 13-3) for decoding the data demodulated in three (12-0 to 12-3); A processor (20) and a controller (30) for controlling the channel processor (10); A memory unit 40 and a dipram 50 for storing temporary data generated during a control operation of the processor 20 and the controller 30; HDLC controller 60 for transmitting and receiving a control signal to the route and control card; A combiner unit 70 for dividing data modulated by modems 0 to 3 (12-0 to 12-3) in the channel processing unit into three sectors; And a summation unit (80) for summing output data of the sectors separated by the combiner unit (70) and outputting the sum data to an IF conversion card. The channel card circuit in the forward link comprises: modems 0 to modem 3 (12-0 to 12-3) for modulating ADPCM data output from the route and control card, and the modems 0 to modem 3 ( Combiner 0 to combiner 2 (70-0 to 70-2) for separating and outputting data modulated in 12-0 to 12-3 into three sectors, and combiner 0 to combiner. And a summation section 0 through summation section 2 (80-0 through 80-2) for summing output data of the sectors separated and outputted at 2 (70-0 through 70-2) and outputting them to the IF conversion card. A channel card circuit for a base station of a wireless subscriber network system. The channel card circuit in the reverse link inputs alpha, beta, gamma sector signals output from the IF conversion card through transceivers 0 through 5 (14-0 through 14-5), and then buffers 0. Mux 0 to mux 3 (11-0 to 11-3) for selecting only one sector having an input signal among the alpha, beta and gamma sectors outputted through the buffer 5 (15-0 to 15-5); Modem 0 to modem 3 (12-0 to 12-3) for demodulating data selected and output from mux 0 to mux 3 (11-0 to 11-3), and modem 0 to modem 3 (12-0 to 12). Viterbi decoder 0 to Viterbi decoder 3 (13-0 to 13-3) for decoding the demodulated data in 12-3) and outputting the demodulated data to a route and a control card. Channel card circuit.

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