KR100382073B1 - Apparatus for multiplex route IF transmission W-CDMA communication system - Google Patents

Abstract

The present invention is an apparatus for receiving a 3.84Mbps baseband I / Q digital signal modulated by a spread spectrum signal from a plurality of channel cards in the base station and up-converting it to an intermediate frequency (IF) signal having a center frequency of 70 MHz. The present invention relates to an apparatus for transmitting a multipath intermediate frequency in a CDMA communication system capable of operating six sectors or three sectors of diversity by implementing six paths in a pack. The present invention relates to six sectors in an IMT-2000 asynchronous system. Alternatively, six intermediate frequency upconversion paths may be implemented in one multipath intermediate frequency transmitter in order to easily implement a base station with three sector diversity. In addition, the LVDS demultiplexer receives data at a high speed of 215.04 Mbps and performs digital addition to receive a wideband baseband signal from a plurality of channel cards. Also, to reduce the data rate received from multiple channel cards, the FIR filter is placed after the digital adder rather than the channel card. The digital signal output by the FIR filter is converted into an analog signal and the analog baseband I / Q signal is Using the analog 70Mhz local signal generated by the 70Mhz PLL unit, it is converted up to the IF signal of the center frequency 70Mhz and the bandwidth 3.84Mhz and transmitted to the high frequency signal processor (RF).

Description

Apparatus for multiplex route IF transmission W-CDMA communication system in W-CDMA communication system

The present invention relates to a circuit pack for upconverting a digital baseband signal received from a plurality of channel cards to an intermediate frequency. Particularly, a 3.84 Mbps base station modulated with a spread spectrum signal from a plurality of channel cards in a base station of a W-CDMA communication system. W-CDMA communication for receiving band I / Q digital signals and converting them to intermediate frequency signals with a center frequency of 70 MHz and six paths in one circuit pack for six or three sector diversity. A multipath intermediate frequency (IF) transmitter in a system.

In general, the base station system of the IMT-2000 system, which is being developed as a next generation mobile communication system, is a circuit pack for performing intermediate frequency transmission / reception functions on one shelf (alpha), beta (β), and gamma (γ). Three are mounted for sectors and one for redundancy. That is, four circuit packs that perform the ICDA function are mounted together in the center of the shelf.

1 is a view illustrating a structure of a redundancy control device for an intermediate frequency transceiver circuit pack in a conventional IMT-2000 system.

First, FIG. 1A is a diagram for describing a process of transmitting an intermediate frequency signal, and a multi-user modulator board assembly (hereinafter, abbreviated as "MUMA") for modulating a forward baseband signal. 4 transmit digital signals to 4 intermediate frequency and clock distribution board assemblies (hereinafter referred to as " ICDA ") (21 to 24). Here, ICDA 21 is an intermediate frequency transceiver circuit pack for α sector, ICDA 22 is an intermediate frequency transceiver circuit pack for β sector, ICDA 23 is an intermediate frequency transceiver circuit pack for gamma sector, and ICDA 24 Is an intermediate frequency transceiver circuit pack for redundancy. The ICDA thus processed processes the transmission digital signals input from the ICDAs 21 to 23 for each sector, and then outputs the transmission intermediate frequency signals Tx_α, Tx_β, and Tx_γ for each sector. As is well known, if an ICDA for any sector processing fails while the three ICDAs 21 to 23 transmit an intermediate frequency signal for each sector, the redundancy ICDA 24 performs the function instead. Here, the redundancy ICDA 24 can replace one sector for three sectors, and is implemented to replace only the first failing sector ICDA function. Therefore, when one sector processing ICDA fails and the redundancy ICDA takes over its function, when the other sector processing ICDA fails, the function of the failed sector ICDA cannot be replaced later.

FIG. 1B is a view for explaining a process of receiving an intermediate frequency signal. In a normal state, intermediate frequency signals Rx_α, Rx_β, respectively received by three ICDAs 21 to 23, which are intermediate frequency transceiver circuit packs for each sector, are illustrated. Rx_γ) is passed to a Multi-Mode Demodulator board Assembly (hereinafter abbreviated as "MMDA") 30 that demodulates the backward signal. The MMDA 30 then demodulates the received intermediate frequency signal for each sector into the original signal. As is well known, if an ICDA for any sector processing fails while receiving the intermediate frequency signal for each sector in the three ICDAs 21 to 23, the redundancy ICDA 24 performs the function instead. Here, the redundancy ICDA 24 can replace one sector for three sectors, and is implemented to replace only the first failing sector ICDA function. Therefore, when one sector processing ICDA fails and the redundancy ICDA takes over its function, when the other sector processing ICDA fails, the function of the failed sector ICDA cannot be replaced later.

In other words, the conventional base station system has the advantage of implementing three sectors in one shelf, but since only one redundancy circuit pack is implemented for three sectors, among three circuit packs of α, β, and γ sectors, If two or more sectors fail, they cannot be replaced, resulting in a decrease in system performance.

Accordingly, the present invention has been proposed to solve the above conventional problems, and an object of the present invention is to provide a single circuit for easily implementing a base station with 6 sectors or 3 sector diversity in an IMT-200 asynchronous system. Implementing six paths in a pack reduces the number of circuit packs, minimizes the number of lines on the backplane, and reduces data errors when sending and receiving with a channel card. It is to provide a frequency transmission device.

In the W-CDMA communication system according to the present invention for achieving the above object, the multi-path intermediate frequency transmission apparatus, receiving the signal output from the channel card as four differential (Differential) level signal to belong to the in-phase voltage range Low voltage differential signaling (LVDS) receiver for outputting I / Q data by restoring the data to 28 lines of TTL (Transistor to Transistor Logic) level signal, and the baseband signal input from the LVDS receiver 100. A forward IF processor for converting the signal into an intermediate frequency to be transmitted to a high frequency signal processor, a clock receiver configured to receive a frame synchronization clock and a reference clock from an upper processor supplying the clock and process the signal at an LVDS level, and output the received signal from the clock receiver; A PLL unit for generating an analog signal from the signal and supplying a local signal to the forward IF processor; A control logic unit for processing an alarm signal received from the forward IF processor in accordance with the processor unit to be described and generating a control signal in a circuit pack, a clock and a reference clock output from the control logic unit, and the forward IF processor A clock distribution unit for distributing a synchronization signal to be used in a circuit pack, an HDLC matching unit matching a higher processor to an RS-485 level and providing a communication path in a circuit pack in a half-duplex manner, and an upper processor connected to the HDLC matching unit And a processor unit for communicating with the control logic unit, reporting various alarm signals, connected to the forward IF processor, driving a digital filter, and performing initialization of the PLL unit.

1 is a view illustrating a structure of a redundancy control device of an intermediate frequency transceiver circuit pack in a conventional base station system. FIG. 1A is a diagram illustrating a transmission process, and FIG. 1B is a diagram illustrating a reception process.

2 is a view showing the configuration of a multipath IF transmitter in a W-CDMA communication system according to the present invention;

3 is a block diagram illustrating a detailed block configuration of an adder according to FIG. 2;

4 is a view illustrating an operation timing of an adder according to FIG. 2;

5 is a block diagram illustrating a detailed block diagram of the IF processor of FIG. 2.

<Explanation of symbols for the main parts of the drawings>

100: LVDS receiver 110: forward IF processor

111: addition unit 112: digital FIR filter unit

113: IF processor 120: clock receiver

130: PLL section 140: control logic section

150: clock divider 160: HDLC matching unit

170: processor unit

Hereinafter, a preferred embodiment of a multi-path intermediate frequency transmission apparatus in a W-CDMA communication system according to the present invention according to the above technical concept will be described in detail with reference to the accompanying drawings.

2 is a diagram showing the configuration of a multipath intermediate frequency transmitter in a W-CDMA communication system according to the present invention.

As shown in the figure, the signal output from the channel card is received as four differential level signals to restore data belonging to the in-phase voltage range, and then processed into TTL (Transistor to Transistor Logic) level signals of 28 lines. A low voltage differential signaling (LVDS) receiver 100 for outputting I / Q data, and a forward IF processor 110 for converting a baseband signal input from the LVDS receiver 100 into an intermediate frequency and transmitting the intermediate band signal to a high frequency signal processor. And a clock receiving unit 120 which receives a frame synchronizing clock and a reference clock from an upper processor that supplies a clock, processes the signal at an LVDS level, and outputs the signal, and generates an analog signal from the signal received from the clock receiving unit 120. Matched with the PLL unit 130 and the processor unit 170 for supplying a local signal to the forward IF processing unit 110 received from the forward IF processing unit 110 A control logic unit 140 for processing an alarm signal and generating a control signal in a circuit pack, a clock and a reference clock output from the control logic unit 140, and a synchronization signal used by the forward IF processor 110; A clock distribution unit 150 for distributing in the circuit pack, an HDLC matching unit 160 matching the upper processor with an RS-485 level and providing a communication path in the circuit pack in a half-duplex manner, and the HDLC matching unit 160 Connected to communicate with a higher processor, connected to the control logic unit 140 to report various alarm signals, connected to the forward IF processor 110 to drive a digital filter, and of the PLL unit 130 The processor 170 may be configured to perform initialization. The forward IF processor 110 may add a signal input from the LVDS receiver 100 in parallel and then latch the output latch signal to output the latch. A digital FIR filter unit for receiving a parallel I / Q data output from the adder 111 and performing pulse shaping and interpolation, and then outputting a baseband signal ( 112, and an IF processor 113 for receiving parallel I / Q data output from the digital FIR filter unit 112 and converting the received data into a center frequency and an intermediate frequency to output a high frequency signal. It features.

The operation of the multipath intermediate frequency transmitter in the W-CDMA communication system configured as described above is as follows.

The LVDS receiver 100 requires 10 channels as many as the number of channel cards, and the inputs are input at four differentials of 215.04 Mbps and the outputs are clocked at 30.72 Mbps and TTL level. The line is output. That is, the 4:28 demultiplexer uses 24 of them, and four lines of 'I Even / odd' and 'Q Even / odd', which contain bits for parity check, correspond to one sector, and a forward IF processor ( Input to the adder 111 of 110.

The adder 111 latches and outputs an input signal as an output latch signal, and the digital FIR filter 112 receives the parallel 3.84 Mbps 16-bit I / Q data output from the adder 111 to 3G asynchronously. Required by the system Pulse shaping and 4x interpolation functions of 0.22 are performed to transmit the 16-bit I / Q baseband signal to the IF processor 113.

In addition, the IF processing unit 113 receives parallel 3.84 Mbps 16-bit I / Q data output from the digital FIR filter unit 112, and outputs the digital data of the digital FIR filter unit 112 with a center frequency of 70 MHz. It is made of intermediate frequency (IF) of 3.84Mhz bandwidth and transmitted to high frequency signal processor (RF).

On the other hand, the clock receiver 120 receives the frame synchronization clock and the 30.72Mhz clock at the LVDS level from the circuit pack supplying the clock and transmits it to the control logic unit 140.

The PLL unit 130 uses the 15.36Mhz output from the clock receiving unit 120 as a reference clock to make an analog signal of 70Mhz and uses two 3-way dividers to form the I of the forward IF processing unit 113. / Q Provides a local signal to a modulator (not shown).

The control logic unit 140 matches the processor with the HDLC matching unit 160 to process the alarm signal received by the adder 111 of the forward IF processing unit 110, and also generates and outputs various control signals in the circuit pack. In addition, the clock distributor 150 distributes 30.72Mhz and 15.36Mhz and the synchronization signal used by the forward IF processor 110 output from the control logic unit 140 in the circuit pack.

The HDLC matching unit 160 matches the upper processor with the RS-485 level to provide a communication path in a half-duplex manner.

The processor unit 170 is connected to the HDLC matching unit 160 to communicate with the upper processor, and connected to the control logic unit 140 to report various alarm signals to the upper processor, and is also connected to the forward IF processor 110 and the like. Drive the digital filter and initialize the PLL.

3 is a diagram illustrating a detailed configuration of an adder according to FIG. 2, and FIG. 4 is a diagram illustrating an operation timing of the adder according to FIG. 2.

As shown in FIG. 3, each of the four output lines output from the LVDS receiver 100 is received only when the strobe signal indicating whether the corresponding data is valid is in a 'low' state. 16-bit data output from the first and second demultiplexers 201 and 202 and the first and second demultiplexers 201 and 202 to perform demultiplexing in parallel 16 bits according to a synchronization signal. Adds in parallel to receive 20-bit parallel data from the first and second adders 211 and 212 and the first and second adders 211 and 212 to process and transmit 20-bit parallel data. If the upper 4 bits are not '0000', an alarm signal indicating saturation is made high and transmitted; if the upper 4 bits are '0000', the first and second saturation latches and outputs 16 bits as an adder output latch signal. From the processing units 221 and 222 and the clock distribution unit 150. Receives a frequency and a synchronization signal and transmits it to the first and second demultiplexers 201 and 202, and latches the synchronization signal twice so that the first and second saturation processors 221 and 222 A parallel signal output from the clock receiver 230 and the first and second demultiplexers 201 and 202 which are transmitted as an output latch clock and output a parallel / serial conversion control signal of the alarm processor 250 to be described later. The parity check unit 240 performs 'Odd' parity check on the 16-bit data, the parity alert received from the parity check unit 240, and the first and second saturation processing units 221 and 222. It consists of an alarm processing unit 250 for generating two saturation alarm signals in series form and transmitting them to the control logic unit 140, and this configuration is implemented in the form of a field programmable gate array (FPGA). Means 2000, which can be programmed by the user. Byte-only refers to gate the degree of semi-custom IC logic is feasible, and the timing diagram in accordance with the present invention having the above arrangement is equal to the accompanying drawings FIG.

The operation of the adder 111 in the forward IF processor 110 in the circuit pack configuration according to the present invention having such a configuration will be described below.

First, the demultiplexer 200 receives four outputs from each of the 10 LVDS receivers only when the strobe signal indicating whether the corresponding data is valid is in a 'Low' state. The adder 210 adds 10 16-bit data output from the demultiplexer 200 in parallel to transmit 20-bit parallel data to the saturation processor 220. .

Upon receiving the parallel data, the saturation processor 220 receives 20-bit parallel data from the adder 210 and sets an alarm signal indicating that the upper 4 bits are not saturated to 'High' to make a high alarm state. 250, and if the upper 4 bits are '0000', the lower 16 bits are latched and output by the adder output latch signal.

Next, the clock receiver 230 receives the 30.72Mhz and the synchronization signal from the clock distributor 150 and transmits the synchronization signal to the demultiplexers 201 and 202. In addition, the synchronization signal is latched twice at 30.72Mhz and used as an output latch clock of the saturation processing units 221 and 222, and used as a parallel / serial conversion control signal of the alarm processing unit 250.

The parity checker 240 performs Odd (odd) parity check with the parallel 16-bit data output from the demultiplexer 200. That is, if the 'High' state of the 16 bits is an odd number, an alarm signal indicating that a parity error has occurred is made to the 'High' state, and the alarm state signal is set to 'Low' if the 'High' state is even. Make.

The alarm processor 250 serializes 20 parity alarms received from the parity checker 240 and two saturation alarm signals received from the saturation processor 220 using four 8: 1 parallel / serial converters. Made in the form of and transmits to the control logic unit 140.

5 is a detailed configuration diagram of the IF processor of FIG. 2.

As shown, the IF processor 113 receives the parallel 3.84 Mbps 16-bit I / Q data output from the digital FIR filter 112, and the D / A converter 300, the amplifier 400 and the low pass. It consists of a pass filter 500, an I / Q modulator 600, a band pass filter 700 and a coupler 800, the output digital data of the digital FIR filter 112, the center frequency 70Mhz, bandwidth It is made of 3.84Mhz intermediate frequency (IF) and transmitted to high frequency signal processor (RF).

First, the D / A converter 300 converts 16-bit parallel data into a baseband analog signal, and the amplifier AMP 400 is an analog signal (maximum) output from each of the D / A converters 301 and 302. 20mA) to the voltage level.

The low pass filter (LPF) 500 removes signals other than 0 to 2.5 MHz of the bandwidth of the analog baseband signal, and the I / Q modulator 600 passes through the low pass filters 300 and 301. The baseband I / Q signal is output only by the intermediate frequency (IF) having a center frequency of 70 MHz and a bandwidth of 3.84 MHz by the 70 MHz local signal generated from the PLL unit 130, and the band pass filter (BPF; 700) receives the I / Q signal. Eliminates unwanted harmonic components out of band generated by the Q modulator 600.

Coupler 800 is a 10dB coupler and extracts -10dB power at the input level and uses it for IF signal monitoring.

According to the above-described "multi-path intermediate frequency transmitter in the W-CDMA communication system" described above, the base station of the IMT-2000 asynchronous system accommodates 10 channel cards and has a medium capacity of 6 sectors or 3 sectors of diversity. By implementing the frequency up-conversion function in one circuit pack, the number of circuit packs can be reduced.

In addition, since LVDS is interlocked with the channel card, the number of lines in the backplane can be minimized, and data errors can be reduced when transmitting and receiving with the channel card using a digital adder, and error detection is easy even when an error occurs.

Claims (4)

An apparatus for transmitting a multipath intermediate frequency in a W-CDMA communication system having a channel card, Receives the signals output from the channel card as four differential level signals, restores the data belonging to the in-phase voltage range, and processes the I / Q data by processing the TTL (Transistor to Transistor Logic) level signals of 28 lines. LVDS (Low Voltage Differential Signaling) receiving unit for outputting; A forward IF processor converting the baseband signal input from the LVDS receiver 100 into an intermediate frequency and transmitting the intermediate band signal to a high frequency signal processor; A clock receiving unit which receives a frame synchronization clock and a reference clock from an upper processor that supplies a clock, processes the signal at an LVDS level, and outputs the same; A PLL unit for generating an analog signal from the signal received from the clock receiver and supplying a local signal to the forward IF processor; A control logic unit matching with a processor to be described later, processing an alarm signal received from the forward IF processor, and generating a control signal in a circuit pack; A clock divider for distributing a clock, a reference clock output from the control logic unit, and a synchronization signal used by the forward IF processor in a circuit pack; An HDLC matching unit matching with an upper processor at an RS-485 level and providing a communication path in a circuit pack in a half-duplex manner; A processor connected to the HDLC matching unit to communicate with a higher processor, a connection to the control logic unit to report various alarm signals, a connection to the forward IF processor to drive a digital filter, and initialization of the PLL unit Apparatus comprising a multi-path intermediate frequency transmission apparatus in W. CDMA communication system, characterized in that configured to include. The method of claim 1, wherein the forward IF processing unit, An adder which adds a signal input from the LVDS receiver in parallel and then latches and outputs the signal as an output latch signal; A digital FIR filter unit for receiving parallel I / Q data output from the adder to perform pulse shaping and interpolation, and then output a baseband signal; W-CDMA comprises an IF processing unit for receiving parallel I / Q data from the digital FIR filter unit, converting the received data into a center frequency and an intermediate frequency and outputting a high frequency signal. Multipath intermediate frequency transmitter in communication system. The method of claim 2, wherein the adding unit, Only when the strobe signal indicating whether the corresponding data is valid is received in the 'Low' state, each of the four output lines output from the LVDS receiver is received, and each of the received I and Q is parallel 16 bits in accordance with a synchronization signal. First and second demultiplexing units performing demultiplexing; First and second adders for adding 16-bit data output from the first and second demultiplexers in parallel, processing the 20-bit parallel data, and transmitting the same; 20-bit parallel data is received by the first and second adders, and if the upper 4 bits are not '0000', an alarm signal indicating that the signal is saturated is transmitted to a 'High' state, and when the upper 4 bits are '0000', 16 bits are transmitted. First and second saturation processing units configured to latch and output an adder output latch signal; Receives the frequency and the synchronization signal received from the clock distribution unit and transmits to the first and second demultiplexer, and latches the synchronization signal twice to use as the output latch clock of the first and second saturation processing unit, A clock receiving unit for outputting a parallel / serial conversion control signal of an alarm processing unit to be described later; A parity check unit configured to perform 'Odd' parity check on the parallel 16-bit data output from the first and second demultiplexers; WU-CDM characterized in that it comprises a parity alarm received from the parity check unit and the alarm processing unit for transmitting the two saturation alarm signals received from the first and second saturation processing unit in a serial form to the control logic unit. Multi-path intermediate frequency transmitter in this communication system. The method of claim 2, wherein the IF processing unit, First and second D / A converters for converting 16-bit parallel data into a baseband analog signal; First and second amplifiers for amplifying the analog signals output from the first and second D / A converters to a predetermined level; First and second low pass filter units for removing signals other than the bandwidth of the analog baseband signal converted and output from the first and second amplifiers; An I / Q modulator for outputting a baseband I / Q signal passing through the first and second low pass filter units only by an intermediate signal having a center frequency and a bandwidth by a local signal generated by a PLL unit; A band pass filter unit for removing unwanted harmonic components out of band generated by the I / Q modulator; Multi-path intermediate frequency in the W-CDMA communication system comprising a coupler used for IF signal monitoring by receiving the signal output from the band pass filter, extracting -10dB power of the input level Transmitting device.