KR100299978B1 - Level converter circuit - Google Patents

Abstract

A novel level converter circuit having an input section and a driver section is provided, and the gate of the driver field effect transistor connected to the output section of the driver section is provided at the input section so that the new level converter circuit can exhibit a high speed logical level converting operation. It is directly driven by an input field effect transistor with a gate connected to the input.

Description

Level converter circuit

The present invention relates to a logic level converter circuit, and more particularly, to a logic level converter circuit for converting a high logic voltage level and a low logic voltage level into another high logic level and a low logic level.

A word line driver circuit has been proposed as a level converter circuit for converting a high logic voltage level and a low logic voltage level into other high and low logic levels. This wordline driver circuit was described in ISSCC'95 DIGEST OF TECHNICAL PAPERS "Circuit Design Techniques For Low-Voltage Operating And / Or Giga-Scale DRAMs". 1 is a circuit diagram illustrating a conventional word line driver circuit for converting high and low logic voltage levels to other high and low logic levels, in which a high level corresponding to an internal power voltage VINT is a boosting power. The low level corresponding to the ground level GND is converted to another low voltage level corresponding to the shallow voltage level VBB while the voltage is converted to another high voltage level corresponding to the voltage Vpp.

In order to reduce the sub-threshold leakage current, the word line voltage is controlled at a negative voltage level in the standby state and at a boosting voltage level higher than the internal operating voltage level in the active state.

In the word line driver circuit above, node A3 is driven by an output from a row decoder which is a logic gate. It is now considered that node A3 is indirectly driven by routing from the driver in another block. Fig. 2 is a block diagram showing another existing word line drive circuit for converting high and low logic voltage levels to other high and low logic levels, where node A3 is routed from the driver in another block. Indirectly driven The input waveforms from the inverter D3 of this other block have a large rise time and fall time since the input signal from the inverter D3 is transmitted to the input portion VIN through the load of the line H1. . For this reason, the transition time of the logic voltage level at the input VIN becomes large, whereby a large punch through current I1 responds to the fall of the voltage level from the inverter D3. Flow from power source VPP to line GND through line H1 and transistors Q2 and Q5. In addition, a large punch through current I2 flows from the power source VINT to the power source VBB through the line H1 and the transistors Q6 and Q4 in response to an increase in the voltage level from the inverter D3. . In order to avoid problems of large punch through currents, it is preferable that node A3 is driven directly by the output from the logic gate.

Hereinafter, the circuit configuration and operation of the existing level converter circuit shown in FIG. 1 in which node A3 is directly driven by inverter D2 will be described. 4 is a timing diagram showing waveforms of the conventional level converter circuit shown in FIG. The existing level converter circuit has an input section and a driver section. The driver section of the existing level converter circuit not only p-channel MOS field effect transistors Q1 and Q2 having the substrate voltage VPP but also n-channel MOS field effect transistors Q3 and Q4 having the substrate voltage VBB. Have The input portion of the existing level converter circuit has an n-channel MOS field effect transistor Q5 having a ground level substrate voltage and a gate to which the voltage VINT is applied. The input of the existing level converter circuit also has a p-channel MOS field effect transistor Q6 having a substrate voltage of VINT and a gate to which a voltage of ground level is applied. The input of the existing level converter circuit also includes an inverter D2 comprising n-channel and p-channel MOS field effect transistors each having the same size as the n-channel and p-channel MOS field effect transistors Q5 and Q6. Have

At the input, the inverter D2 has an input side connected to the input terminal VIN of the existing level converter circuit and an output side connected to the node A3. The n-channel MOS field effect transistor Q5 is connected in series between node A3 and node A1, while the p-channel MOS field effect transistor Q6 is connected between node A3 and node A2. Are connected in series.

First, the raising operation of the output voltage VOUT is considered. When the input voltage VIN is at the ground level GND, the node A3 at the output side of the inverter D2 has the voltage level VINT, while the node A2 has the voltage level VINT and the output terminal ( VOUT) has a voltage level VBB. Transistors Q5, Q1 and Q4 are either in the non-conductive state or in the off state, while the remaining transistors Q6, Q2 and Q3 are in the conducting state or on state, so that individual nodes are powered. Connected to the voltages.

When the input voltage VIN rises from the ground level GND to the voltage level VINT, the potential of the node A3 falls from the voltage level VINT to the ground level GND. At this time, transistor Q6 is on, so the potential of node A2 drops to approach the absolute value | VTP | of the negative threshold voltage VTP of the p-channel transistor, so as to source the transistor Q6. And the drain voltage or the voltage applied across the nodes A2 and A3 is reduced. As a result, the driving capability of transistor Q6 falls and the potential of node A2 gradually falls.

On the other hand, the transistor Q5 is in the conductive state or the on state because the potential of the node A3 falls to the voltage level defined by the difference VINT-VTN, which is the positive threshold voltage of the n-channel MOS field effect transistors. Is changed, the potential of the node A1 is increased. When the potential of the node A1 does not become higher than the voltage level VPP- | VTP |, the transistor Q1 is turned on so that the voltage level of the output VOUT remains in the conducting state or the on state of the transistor Q3. It is gradually increased. Thereafter, when the voltage level of the output terminal VOUT is increased until it is not lower than the voltage level VBB + VTN, the transistor Q4 is turned into a conducting state or an on state, so that the potential of the node A2 is at a voltage level. Falls to (VBB). As a result, the transistors Q3 and Q6 are turned off or non-conductive. At this time, the output voltage VOUT is increased to the voltage level VPP and the transistors Q1 and Q5 are in the conductive state or the on state.

Next, the falling operation of the output voltage VOUT will be described. When the input voltage VIN is at the voltage level VINT, the node A3 becomes the ground state GND, the node A2 becomes the voltage level VBB and the output voltage VOUT is the voltage level VPP. ). Transistors Q6, Q2 and Q3 are either in a non-conductive state or in an off state, while the remaining transistors Q5, Q1 and Q4 are in a conducting state or on state so that individual nodes are connected to power voltages.

When the input voltage VIN falls from the voltage level VINT to the ground level GND, the node A3 is increased from the ground level GND to the voltage level VINT. At this time, transistor Q5 is in a conductive state or an on state, so node A1 increases in voltage to approach the voltage level defined by VINT-VTN.

Since the source and drain voltage of the transistor Q5 or the voltage applied across the nodes A1 and A3 is reduced, the driving ability of the transistor Q5 is reduced and the potential of the node A1 gradually decreases.

On the other hand, since the potential of the node A3 is increased to the voltage level defined by the difference | VTP |, the transistor Q6 is turned into the conducting state or the on state, so that the potential of the node A2 is increased. When the potential of the node A2 is not higher than the voltage level VBB + VTN, the transistor Q3 is turned on so that the voltage level of the output VOUT gradually decreases. Thereafter, when the voltage level of the output terminal VOUT falls so as not to be higher than the voltage level VPP + | VTN |, the transistor Q2 is turned into the conducting state or the on state, and the potential of the node A1 is changed to the voltage level VPP. Is increased to). As a result, the transistors Q1 and Q5 are turned on or in a conductive state. At this time, the output voltage VOUT falls to the voltage level VBB, the transistor Q4 is in the non-conductive state or the off state, and the transistors Q3 and Q6 are in the conductive state or the on state.

In the same manner as described above, the level converter circuit has a logic level, for example, a high level such as VINT corresponding to the internal power voltage and a low level such as GND corresponding to the ground level. Then, it is converted to a high level such as VPP corresponding to the booster power voltage and a low level such as VBB which is a negative low voltage VBB.

In the existing level converter circuit above, inverter D2 is operated as an input logic gate at the input, while transistors Q5 and Q6 are passed the logic level of node A3 to voltage level VPP or VBB. It acts as a transfer gate transistor to prevent this. At the input of the existing level converter circuit above, the output from the input logic gate or the voltage level of the node A3 is transferred to the nodes A1 and A2 via the transfer gate transistors Q5 and Q6 and transferred to the transfer gate transistors. Such outputs from Q5 and Q6 or the voltage levels of nodes A1 and A2 are input to the driver section.

The existing level converter circuit above engages with the following problems.

In the rising operation of the output voltage VOUT, the p-channel MOS field effect transistor Q1 in the driver section is the n-channel of the inverter D2 operating as a plurality of transistors, for example as an input logic gate in the input section. It is driven by an MOS field effect transistor and an n-channel transfer gate MOS field effect transistor Q5 at the input.

In addition, in the falling operation of the output voltage VOUT, the n-channel MOS field effect transistor Q3 in the driver section is a plurality of transistors, for example, p- of the inverter D2 operating as an input logic gate of the input section. It is driven by the channel MOS field effect transistor and the p-channel transfer gate MOS field effect transistor Q6 at the input.

Since each of the driver transistors in the driver section is driven by a plurality of transistors in the input section, the above existing level converter circuit cannot exhibit the high speed logic level conversion operation.

In the above environment, it was required to develop a novel level converter circuit which is not bound by the above problems.

It is therefore an object of the present invention to provide a novel level converter circuit free from the above problems.

Another object of the present invention is to provide a novel level converter circuit capable of exhibiting a high speed logic level converting operation.

It is still another object of the present invention to provide a novel level converter circuit, in which a driver section and a gate of a driver field effect transistor connected to an output terminal are driven directly by an input side field effect transistor having a gate connected to an input terminal.

1 is a circuit diagram illustrating a conventional word line driver circuit for converting high and low logic voltage levels to other high and low logic levels.

2 shows another existing word line driver circuit for converting high and low logic voltage levels to other high and low logic levels, in which node A3 is indirectly driven by routing from a driver in another block. The block diagram which shows.

3 shows another existing word line driver circuit for converting high and low logic voltage levels into other high and low logic levels, in which node A3 is indirectly driven by routing from a driver in another block. The block diagram which shows.

4 is a timing diagram showing waveforms of the conventional level converter circuit shown in FIG.

Fig. 5 is a circuit diagram showing a novel level converter circuit capable of exhibiting a fast logic voltage level converting operation in the first embodiment according to the present invention.

Fig. 6 is a circuit diagram showing a novel level converter circuit capable of exhibiting a fast logic voltage level converting operation in the second embodiment according to the present invention.

Fig. 7 is a circuit diagram showing a novel level converter circuit capable of exhibiting a fast logic voltage level converting operation in the third embodiment according to the present invention.

Fig. 8 is a circuit diagram showing a novel level converter circuit capable of exhibiting a fast logic voltage level converting operation in the fourth embodiment according to the present invention.

9 is a timing diagram showing waveforms of the novel level converter circuit shown in FIG.

The above and other objects, features and advantages of the present invention will become apparent from the following description.

According to the present invention, an input field effect transistor having a gate connected to the input terminal and having a gate connected to the input terminal so that the gate of the driver field effect transistor connected to the output terminal of the driver section and connected to the output terminal can exhibit the high speed logic level conversion operation. There is provided a novel level converter circuit having an input section and a driver section, which are directly driven by a.

The first invention provides a voltage level converter circuit for converting a set of original logic voltage levels into a different set of converted voltage levels that are different from these voltage levels. This voltage level converter circuit includes a driver section and an input section connected to the driver section. The driver section has an output terminal from which an output signal is output. The input section has an input terminal through which an input signal is input. The driver section selectively supplies one of the converted voltage levels to the output terminal. The input unit controls the driver unit such that one of the converted voltage levels is selectively supplied to the output terminal according to the input signal. The gates of the drive side transistors provided at the drive portion and directly connected to the output stage are connected to the input side transistors having gates directly connected to the input terminal such that the gates of the driver side transistors are directly driven by the input side transistors.

It is preferable that the high level of the converted voltage levels is higher than the high level of the original voltage levels and the low level of the converted voltage levels is lower than the low level of the original voltage levels.

An inverter having an input side having an input side connected to the input terminal; And series connected transistors provided between the high and low voltage lines having the high voltage level and the original low voltage level and having gates connected to the input terminal and the output side of the inverter to drive the gates of the driver transistors in the driver section. Also preferred.

An input unit having an input side connected to the input terminal; A gate provided between one of the driver transistors in the driver section having gates connected between the input and output terminals of the inverter and having high and low voltage lines respectively having a converted voltage level of high and an original low voltage level. Driving first series coupling transistors; And gates connected between the high and low voltage lines having the original high voltage level and the converted voltage level of low, respectively, connected to the input terminal and the output side of the inverter, and having the other of the driver transistors in the driver section. It is also desirable to include second series connected transistors to drive the gate.

An input unit having an input side connected to the input terminal; A gate is provided between a low voltage line having an original low voltage level and an output side of the inverter and has gates connected to an input terminal and a high voltage line having an original high voltage level, and has a gate of one of the driver transistors in the driver unit. Driving first series coupling transistors; And a gate provided between the low voltage line having the original high voltage level and the output side of the inverter and having gates connected to the input terminal and the low voltage line having the original low voltage level, the other of the driver transistors in the driver section having It is also desirable to include second series connected transistors that drive the gate.

Between the transistor connected to the low voltage line having the original low voltage level and the high voltage line having the original high voltage, the input portion driving the gate of one of the driver transistors in the driver portion with the gates connected to the input stage. A first CMOS inverter; And a transistor connected between a high voltage line having an original high voltage level and a transistor connected to a low voltage line having an original low voltage, which has a gate connected to an input terminal and drives a gate of one of the driver transistors in the driver portion. It is also desirable to include a 2CMOS inverter.

The second invention provides a circuit element of an input portion connected to a driver portion in a voltage level converter circuit for converting a set of original logic voltage levels into a different set of converted voltage levels than the voltage levels. . The driver section has an output terminal from which an output signal is output. The input section has an input terminal through which an input signal is input. The driver section selectively supplies one of the converted voltage levels to the output terminal. The input unit controls the driver unit to selectively supply one of the converted voltage levels to the output terminal according to the input signal. The gates of the driver side transistors provided at the driver portion and directly connected to the output stage are connected to the input side transistors having gates directly connected to the input terminal such that the gates of the drive side transistors are directly driven by the input side transistors.

The high level of the converted voltage levels is higher than the high level of the original voltage levels and the low level of the converted voltage levels is preferably lower than the low level of the original voltage levels.

An input unit having an input side connected to the input terminal; And series connected transistors provided between the high and low voltage lines having the high voltage level and the original low voltage level and having gates connected to an input terminal and an output side of the inverter, and for driving the gates of the driver transistors in the driver section. It is also desirable.

An input unit having an input side connected to the input terminal; A gate provided between one of the driver transistors in the driver section, having gates connected between the high and low voltage lines having the converted voltage level of the high and the original low level voltage, respectively, and connected to the input side and the output side of the inverter. Driving first series coupling transistors; And gates connected between the high and low voltage lines having the original high voltage level and the converted voltage level of low, respectively, connected to the input terminal and the output side of the inverter, and having the other of the driver transistors in the driver section. It is also desirable to include second series connected transistors to drive the gate.

An input unit having an input side connected to the input terminal; A gate is provided between a low voltage line having an original low voltage level and an output side of the inverter and has gates connected to an input terminal and a high voltage line having an original high voltage level, and has a gate of one of the driver transistors in the driver unit. Driving first series coupling transistors; And a gate provided between an original high voltage level and an output side of the inverter and connected to a low voltage line having an input terminal and an original low voltage level, the gate of the other of the driving transistors in the driver unit. It is also desirable to include second series connected transistors to drive.

Transistor connected to the low voltage line with the original low voltage level and the high voltage line with the original high voltage, the input section having a gate connected to the input stage and driving the gate of one of the driver transistors in the driver section Between the first CMOS inverter; And a transistor connected to a high voltage line having an original high voltage level and a low voltage line having an original low voltage, which drive gates of one of the driver transistors in the driver section and having gates connected to the attraction end. It is also desirable to include a second CMOS inverter of.

(First embodiment)

A first embodiment according to the present invention will be described in detail with reference to FIGS. 5 and 9. 5 is a circuit diagram showing a novel level converter circuit capable of exhibiting a high speed logic voltage level converting operation. 9 is a timing diagram showing waveforms of the novel level converter circuit shown in FIG. The novel level converter circuit circuit configuration is described below.

It has a novel level converter circuit input section and driver section. The input section has an input terminal to which the input voltage VIN inputs there, and the driver section has an output terminal to which the output voltage VOUT outputs therefrom. The input unit and the driver unit are connected through the first and second nodes B1 and B2. The input unit has input logic gates biased between the internal power voltage VINT and the ground level GND. The driver unit has a driver circuit biased between the high power voltage VPP higher than the internal power voltage VINT and the low power voltage VBB lower than the ground level GND. The novel level converter circuit converts internal logic levels, for example, a high level such as the internal power voltage VINT and a low level such as the ground level GND, to a high power voltage VPP and a low power voltage VBB. Let's do it.

The circuit configuration of the driver section of the novel level converter circuit is the same as that of the existing level converter circuit described above. That is, the driver section of the novel level converter circuit has first and second p-channel MOS field effect transistors Q1 and Q2 and third and fourth n-channel MOS field effect transistors Q3 and Q4. The first p-channel MOS field effect transistor Q1 is connected in series between the high power voltage line VPP having the high power voltage VPP and the output terminal VOUT. The substrate of the first p-channel MOS field effect transistor Q1 is electrically connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. The gate of the first p-channel MOS field effect transistor Q1 is connected to the first node B1. The third n-channel MOS field effect transistor Q3 is connected in series between the low power voltage line VBB having the low power voltage VBB and the output terminal VOUT. The substrate of the third n-channel MOS field effect transistor Q3 is electrically connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the third n-channel MOS field effect transistor Q3 is connected to the second node B2. The second p-channel MOS field effect transistor Q2 is connected in series between the high power voltage line VPP having the high power voltage VPP and the first node B1. The substrate of the second p-channel MOS field effect transistor Q2 is electrically connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. The gate of the second p-channel MOS field effect transistor Q2 is connected to the output terminal VOUT. The fourth n-channel MOS field effect transistor Q4 is connected in series between the low power voltage line VBB having the low power voltage VBB and the second node B2. The substrate of the fourth n-channel MOS field effect transistor Q4 is electrically connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the fourth n-channel MOS field effect transistor Q4 is connected to the output terminal VOUT.

The input portion of the novel level converter circuit comprises an inverter D1, fifth and seventh n-channel MOS field effect transistors Q5 and Q7 and sixth and eighth p-channel MOS field effect transistors Q6 and Q8. do. The inverter D1 has an input side connected to the input terminal VIN and an output side connected to the third node B3. The fifth n-channel MOS field effect transistor Q5 is connected in series between the first node B1 and a ground line GND having a ground voltage GND. The substrate of the fifth n-channel MOS field effect transistor Q5 is connected to ground line GND such that the substrate has a ground voltage GND. A gate of the fifth n-channel MOS field effect transistor Q5 is connected to the input terminal VIN. The sixth p-channel MOS field effect transistor Q6 is connected in series between the second node B2 and an internal power voltage line VINT having an internal power voltage VINT. The substrate of the sixth p-channel MOS field effect transistor Q6 is connected to the internal power voltage line VINT such that the substrate has an internal power voltage VINT. The gate of the sixth p-channel MOS field effect transistor Q6 is connected to the input terminal VIN. The seventh n-channel MOS field effect transistor Q7 is connected in series between the first node B1 and the internal power voltage line VINT. The substrate of the seventh n-channel MOS field effect transistor Q7 is connected to the internal power voltage line VINT such that the substrate has an internal power voltage VINT. A gate of the seventh n-channel MOS field effect transistor Q7 is connected to the third node B3. An eighth p-channel MOS field effect transistor Q8 is connected in series between the second node B2 and the ground line GND. The substrate of the eighth p-channel MOS field effect transistor Q8 is connected to ground line GND such that the substrate has a ground voltage GND. The gate of the eighth p-channel MOS field effect transistor Q8 is connected to the third node B3. The fifth and seventh n-channel MOS field effect transistors Q5 and Q7 are connected in series between the internal power voltage line VINT and the ground line GND. The sixth and eighth p-channel MOS field effect transistors Q6 and Q8 are also connected in series between the internal power voltage line VINT and the ground line GND.

Compared with the existing level converter circuit, the transistors Q1, Q2, Q3, Q4, Q5 and Q6 of the new level converter circuit are the transistors Q1, Q2, Q3, Q4, Q5 and Q6 of the existing level converter circuit. Have the same size as). The remaining transistors Q7 and Q8 have the same size as or smaller than the transistors Q5 and Q6, respectively. The inverter D1 has a size capable of driving the transistors Q7 and Q8.

First, the rising operation of the output voltage VOUT will be described.

When the input voltage VIN is at the ground level GND, the third node B3 at the output side of the inverter D1 has the voltage level VINT, while the first node B1 has the voltage level ( VPP), the second node B2 has a voltage level VINT, and the output terminal VOUT has a voltage level VBB. Transistors Q1, Q5, Q7, Q4 and Q8 are in non-conducting or off states, while the remaining transistors Q6, Q2 and Q3 are either in conduction or on state so that individual nodes are powered up. Connected to the voltages.

When the input voltage VIN is increased from the ground level GND to the voltage level VINT, the potential of the third node B3 falls from the voltage level VINT to the ground level GND.

When the input voltage VIN is not lower than the voltage level VTN corresponding to the threshold voltages of the n-channel MOS field effect transistors, the fifth transistor Q5 having the gate receiving the input voltage VIN is turned on or When the potential of the third node B3, which becomes the conduction state and the output side of the inverter D1, drops, the seventh transistor Q7 having the gate connected to the third node B3 is turned off or in a non-conductive state. As a result, the potential of the first node B1 drops to the ground level GND.

When the input voltage VIN is not lower than the voltage level VINT- | VTP | when VTP corresponds to the threshold voltages of the p-channel MOS field effect transistors, the gate voltage receiving the input voltage VIN is provided. The sixth transistor Q6 is turned off or is in a non-conductive state, and when the potential of the third node B3, which is the output side of the inverter D1, drops to the ground level GND, the gate connected to the third node B3. The eighth transistor Q8 having the voltage is turned on or in a conductive state, so that the potential of the second node B2 drops to approach the voltage level | VTP |. At this time, since the source and drain voltages of the eighth transistor Q8 or the voltage applied across the second node B2 and the ground line GND are reduced, the driving ability of the eighth transistor Q8 is dropped. The potential or voltage level of the second node B2 gradually drops.

When the potential or voltage level of the first node B1 does not become higher than the voltage level VINT-VTP, the first transistor Q1 is turned on or the third transistor Q3 is left in a conductive state or in an on state. State, and for this reason, the output voltage VOUT gradually increases.

When the output voltage VOUT is not lower than the voltage level VBB + VTN, the fourth transistor Q4 is turned on or in a conductive state, and the potential or voltage level of the second node B2 is the voltage level VBB. Falls into. As a result, the third and eighth transistors Q3 and Q8 are brought into a non-conductive state or turned off. At this time, the output voltage VOUT is increased to the voltage level VPP and the second transistor Q2 remains in the off state or the non-conductive state, while the first and fifth transistors Q1 and Q5 are in the on state or It remains in a conductive state.

Next, the lowering operation of the output voltage VOUT will be described.

When the input voltage VIN is at the voltage level VINT, the third node B3 at the output side of the inverter D1 has a ground level GND, while the first node B1 has a ground level GND. The second node B2 has a voltage level VBB and the output terminal VOUT has a voltage level VPP. Transistors Q2, Q3, Q6, Q7 and Q8 are either in the non-conductive state or in the off state, while the remaining transistors Q1, Q4 and Q5 are either in conduction or on state so that individual nodes are connected to power voltages. do.

When the input voltage VIN falls from the voltage level VINT to the ground level GND, the potential of the third node B3 is increased from the ground level GND to the voltage level VINT.

When the input voltage VIN does not become higher than the voltage level VINT- | VTP |, the sixth transistor Q6 having a gate that receives the input voltage VIN is turned on or in a conducting state and furthermore, the inverter D1. If the potential of the third node B3, which is the output side of the transistor, increases to the voltage level VINT, the eighth transistor Q8 having the gate connected to the third node B3 is turned off or is in a non-conductive state. The potential of the node B2 is increased to the voltage level VINT.

When the input voltage VIN is not higher than the voltage level VTN, the fifth transistor Q5 having the gate receiving the input voltage VIN is turned off or in a non-conductive state, and further, the inverter D1 is turned off. When the potential of the third node B3 on the output side is increased to the voltage level VITN, the seventh transistor Q7 having the gate connected to the third node B3 is turned on or in a conductive state, and thus the first node B1 is turned on. ) Is increased to approach the voltage level (VINT-VTN). In this case, since the source and drain voltages of the seventh transistor Q7 or the voltage applied across the first node B1 and the internal power voltage line VINT are reduced, the driving capability of the seventh transistor Q7 is reduced to thereby reduce the voltage. The potential or voltage level of one node B1 is gradually increased.

When the potential or voltage level of the second node B2 is not lower than the voltage level VBB + VTN, the third transistor Q3 is turned on or in a conductive state.

When the output voltage VOUT does not become higher than the voltage level VPP- | VTP |, the second transistor Q2 is turned on or in a conductive state, and the potential or voltage level of the first node B1 is set to the voltage level ( VPP). As a result, the first and seventh transistors Q1 and Q7 are brought into a non-conductive state or turned off. At this time, the output voltage VOUT drops to the voltage level VBB and the fourth transistor Q4 remains in the off state or the non-conductive state, while the third and sixth transistors Q3 and Q6 are in the on state or in the conduction state. Will remain in the state.

In the novel level converter circuit shown in FIG. 5, the gate of the first transistor Q1 in the driver section is driven by a single transistor Q5 having a gate in the input section and receiving the input voltage VIN. On the other hand, the gate of the third transistor Q3 in the driver portion is driven by a single transistor Q6 having an input portion and having a gate for receiving the input voltage VIN, which is why the gate of the transistor in the driver portion is driven. The driving capability of the transistors in the input section for this is improved so that the level converter circuit can exhibit a high speed output voltage level converting operation.

(Second embodiment)

A second embodiment according to the present invention is described in detail with reference to FIG. 6, which is a circuit diagram showing a novel level converter circuit capable of exhibiting a high speed logic voltage level converting operation. The difference between the configuration of the novel level converter circuit of the second embodiment from the circuit of the first embodiment is that the seventh transistor Q7 is connected to a higher power voltage VPP and the eighth transistor Q8 is a lower power voltage ( VBB). The timing waveforms of the novel level converter circuit of the second embodiment are the same as in the first embodiment and the same as those shown in FIG. The novel level converter circuit converts internal logic levels, for example, a high level internal power voltage (VINT) and a low level ground level (GND) into a high power voltage (VPP) and a low power voltage (VBB). .

The novel level converter circuit has an input section and a driver section. The input section has an input terminal through which the input voltage VIN is input thereto, while the driver section has an output terminal through which the output voltage VOUT is output. The input unit and the driver unit are connected through the first and second nodes B1 and B2.

The circuit configuration of the driver section of the novel level converter circuit is the same as that of the existing level converter circuit described above. That is, the driver portion of the novel level converter circuit includes first and second p-channel MOS field effect transistors Q1 and Q2 and third and fourth n-channel MOS field effect transistors Q3 and Q4. The first p-channel MOS field effect transistor Q1 is connected in series between the high power voltage line VPP having the high power voltage VPP and the output terminal VOUT. The substrate of the first p-channel MOS field effect transistor Q1 is electrically connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. The gate of the first p-channel MOS field effect transistor Q1 is connected to the first node B1. The third n-channel MOS field effect transistor Q3 is connected in series between the low power voltage line VBB having the low power voltage VBB and the output terminal VOUT. The substrate of the third n-channel MOS field effect transistor Q3 is electrically connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the third n-channel MOS field effect transistor Q3 is connected to the second node B2. The second p-channel MOS field effect transistor Q2 is connected in series between the high power voltage line VPP having the high power voltage VPP and the first node B1. The substrate of the second p-channel MOS field effect transistor Q2 is electrically connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. The gate of the second p-channel MOS field effect transistor Q2 is connected to the output terminal VOUT. The fourth n-channel MOS field effect transistor Q4 is connected in series between the low power voltage line VBB having the low power voltage VBB and the second node B2. The substrate of the fourth n-channel MOS field effect transistor Q4 is electrically connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the fourth n-channel MOS field effect transistor Q4 is connected to the output terminal VOUT.

The input portion of the novel level converter circuit comprises an inverter D1, fifth and seventh n-channel MOS field effect transistors Q5 and Q7 and sixth and eighth p-channel MOS field effect transistors Q6 and Q8. do. The inverter D1 has an input side connected to the input terminal VIN and an output side connected to the third node B3. The fifth n-channel MOS field effect transistor Q5 is connected in series between the first node B1 and a ground line GND having a ground voltage GND. The substrate of the fifth n-channel MOS field effect transistor Q5 is connected to ground line GND such that the substrate has a ground voltage GND. A gate of the fifth n-channel MOS field effect transistor Q5 is connected to the input terminal VIN. The sixth p-channel MOS field effect transistor Q6 is connected in series between the second node B2 and an internal power voltage line VINT having an internal power voltage VINT. The substrate of the sixth p-channel MOS field effect transistor Q6 is connected to the internal power voltage line VINT such that the substrate has an internal power voltage VINT. The gate of the sixth p-channel MOS field effect transistor Q6 is connected to the input terminal VIN. The seventh n-channel MOS field effect transistor Q7 is connected in series between the first node B1 and the high power voltage line VPP. The substrate of the seventh n-channel MOS field effect transistor Q7 is connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. A gate of the seventh n-channel MOS field effect transistor Q7 is connected to the third node B3. An eighth p-channel MOS field effect transistor Q8 is connected in series between the second node B2 and the low power voltage line VBB. The substrate of the eighth p-channel MOS field effect transistor Q8 is connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the eighth p-channel MOS field effect transistor Q8 is connected to the third node B3. The fifth and seventh n-channel MOS field effect transistors Q5 and Q7 are connected in series between the high power voltage line VPP and the ground line GND. The sixth and eighth p-channel MOS field effect transistors Q6 and Q8 are also connected in series between the internal power voltage line VINT and the low power voltage line VBB.

Compared with the existing level converter circuits, the transistors Q1, Q2, Q3, Q4, Q5 and Q6 of the new level converter circuits are the transistors Q1, Q2, Q3, Q4, Q5 and Q5 of the existing level converter circuits. Each has the same size as Q6). The remaining transistors Q7 and Q8 have the same size or smaller size than the transistors Q5 and Q6, respectively.

First, the rising operation of the output voltage VOUT will be described.

When the input voltage VIN becomes the ground level GND, the third node B3 on the output side of the inverter D1 has the voltage level VINT, while the first node B1 sets the voltage level VPP. The node B2 has a voltage level VINT, and the output terminal VOUT has a voltage level VBB. Transistors Q1, Q5, Q7, Q4 and Q8 go into non-conducting or off state, while the remaining transistors Q6, Q2 and Q3 are either in conduction or on state so that individual nodes connect to power voltages. do.

When the input voltage VIN is increased from the ground level GND to the voltage level VINT, the potential of the third node B3 falls from the voltage level VINT to the ground level GND.

When the input voltage VIN is not lower than the voltage level VTN corresponding to the threshold voltages of the n-channel MOS field effect transistors, the fifth transistor Q5 having the gate receiving the input voltage VIN is turned on or When the potential of the third node B3, which becomes the conduction state and further becomes the output side of the inverter D1, drops, the seventh transistor Q7 having the gate connected to the third node B3 is turned off or is in a non-conductive state. The potential of the first node B1 drops to the ground level GND.

A sixth having a gate for receiving the input voltage VIN when the input voltage VIN is not lower than the voltage level VINT- | VTP | when VTP corresponds to the threshold voltages of the p-channel MOS field effect transistors. Transistor Q6 is turned off or in a non-conductive state, and when the potential of third node B3, which is the output side of inverter D1, drops to ground level GND, it has a gate connected to third node B3. The eighth transistor Q8 is turned on or in a conductive state, so that the potential of the second node B2 drops to approach the voltage level | VTP |. Since the gate of the second node B2 or the third transistor Q3 is conducted to the low power voltage line VBB having the low power voltage level VBB lower than the ground level GND, the second node B2 The driving capability of the eighth transistor Q8 for drawing the potential of or the potential of the gate of the third transistor Q3 is higher than in the first embodiment. The transition time to the non-conductive state or the off state of the third transistor Q3 is shortened, and the increase time of the output voltage VOUT is shortened.

When the potential or voltage level of the first node B1 does not become higher than the voltage level VINT-VTP, the first transistor Q1 is turned on or the third transistor Q3 is left in a conductive state or in an on state. State, and for this reason, the output voltage VOUT increases.

When the output voltage VOUT is not lower than the voltage level VBB + VTN, the fourth transistor Q4 is turned on or in a conductive state, and the potential or voltage level of the second node B2 is set to the voltage level VBB. Falls. As a result, the third and eighth transistors Q3 and Q8 are in the non-conductive state or the off state. At this time, the output voltage VOUT is increased to the voltage level VPP and the second transistor Q2 remains in the off state or the non-conductive state, while the first and fifth transistors Q1 and Q5 are in the on state or Maintain conduction.

Next, the lowering operation of the output voltage VOUT will be described.

When the input voltage VIN is at the voltage level VINT, the third node B3 at the output side of the inverter D1 has a ground level GND, while the first node B1 has a ground level GND. The second node B2 has a voltage level VBB and the output terminal VOUT has a voltage level VPP. Transistors Q2, Q3, Q6, Q7 and Q8 are either in the non-conductive state or in the off state, while the remaining transistors Q1, Q4 and Q5 are in the conducting or on state so that the individual nodes are connected to the power voltages. Connected.

When the input voltage VIN falls from the voltage level VINT to the ground level GND, the potential of the third node B3 is increased from the ground level GND to the voltage level VINT.

When the input voltage VIN does not become higher than the voltage level VINT- | VTP |, the sixth transistor Q6 having a gate that receives the input voltage VIN is turned on or in a conductive state and furthermore, the inverter D1. If the potential of the third node B3, which is the output side of the transistor, increases to the voltage level VINT, the eighth transistor Q8 having the gate connected to the third node B3 is turned off or is in a non-conductive state. The potential of the node B2 is increased to the voltage level VINT.

When the input voltage VIN is not higher than the voltage level VTN, the fifth transistor Q5 having the gate receiving the input voltage VIN is turned off or in a non-conductive state, and further, the inverter D1 is turned off. When the potential of the third node B3 on the output side is increased to the voltage level VINT, the seventh transistor Q7 having the gate connected to the third node B3 is turned on or in a conductive state, and thus the first node B1 is turned on. ) Is increased to approach the voltage level (VINT-VTN). The gate of the first node B1 or the first transistor Q1 is conducted to the high power voltage line VPP having the high power voltage level VPP higher than the internal power voltage level VINT, and thus, the first node B1. The driving ability of the seventh transistor Q7 to increase the potential of N or the gate of the first transistor Q1 becomes higher than in the first embodiment. The transition time of the first transistor Q1 to the conduction state or the on state is shortened, and the fall time of the output voltage VOUT is shortened.

When the potential or voltage level of the second node B2 is not lower than the voltage level VBB + VTN, the third transistor Q3 is turned on or in a conductive state.

When the output voltage VOUT does not become higher than the voltage level VPP- | VTP |, the second transistor Q2 is turned on or in a conductive state, and the potential or voltage level of the first node B1 is set to the voltage level ( VPP). As a result, the first and seventh transistors Q1 and Q7 are brought into a non-conductive state or turned off. At this time, the output voltage VOUT drops to the voltage level VBB and the fourth transistor Q4 remains in the off state or the non-conductive state, while the third and sixth transistors Q3 and Q6 are in the on state or in the conduction state. Will remain in the state.

In the novel level converter circuit shown in FIG. 6, the gate of the first transistor Q1 in the driver section is driven by a single transistor Q5 having a gate in the input section and receiving the input voltage VIN. On the other hand, the gate of the third transistor Q3 in the driver portion is driven by a single transistor Q6 having an input portion and having a gate for receiving the input voltage VIN, which is why the gate of the transistor in the driver portion is driven. The driving capability of the input transistor for the input is improved so that the level converter circuit can exhibit a high speed output voltage level converting operation.

(Third Embodiment)

A third embodiment according to the present invention will be described in detail with reference to Fig. 7, which is a circuit diagram showing a novel level converter circuit capable of exhibiting a high speed logic voltage level converting operation.

The novel level converter circuit has an input section and a driver section. The input section has an input terminal to which the input voltage VIN inputs there, and the driver section has an output terminal to which the output voltage VOUT outputs therefrom. The input unit and the driver unit are connected through the first and second nodes B1 and B2. The input unit has input logic gates biased between the internal power voltage VINT and the ground level GND. The driver unit has a driver circuit biased between the high power voltage VPP higher than the internal power voltage VINT and the low power voltage VBB lower than the ground level GND. The novel level converter circuit converts internal logic levels, for example, a high level such as the internal power voltage VINT and a low level such as the ground level GND, to a high power voltage VPP and a low power voltage VBB. Let's do it.

The circuit configuration of the driver section of the novel level converter circuit is the same as that of the existing level converter circuit described above. That is, the driver section of the novel level converter circuit has first and second p-channel MOS field effect transistors Q1 and Q2 and third and fourth n-channel MOS field effect transistors Q3 and Q4. The first p-channel MOS field effect transistor Q1 is connected in series between the high power voltage line VPP having the high power voltage VPP and the output terminal VOUT. The substrate of the first p-channel MOS field effect transistor Q1 is electrically connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. The gate of the first p-channel MOS field effect transistor Q1 is connected to the first node B1. The third n-channel MOS field effect transistor Q3 is connected in series between the low power voltage line VBB having the low power voltage VBB and the output terminal VOUT. The substrate of the third n-channel MOS field effect transistor Q3 is electrically connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the third n-channel MOS field effect transistor Q3 is connected to the second node B2. The second p-channel MOS field effect transistor Q2 is connected in series between the high power voltage line VPP having the high power voltage VPP and the first node B1. The substrate of the second p-channel MOS field effect transistor Q2 is electrically connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. The gate of the second p-channel MOS field effect transistor Q2 is connected to the output terminal VOUT. The fourth n-channel MOS field effect transistor Q4 is connected in series between the low power voltage line VBB having the low power voltage VBB and the second node B2. The substrate of the fourth n-channel MOS field effect transistor Q4 is electrically connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the fourth n-channel MOS field effect transistor Q4 is connected to the output terminal VOUT.

The input portion of the novel level converter circuit comprises an inverter D1, fifth and seventh n-channel MOS field effect transistors Q5 and Q7 and sixth and eighth p-channel MOS field effect transistors Q6 and Q8. do. The inverter D1 has an input side connected to the input terminal VIN and an output side connected to the third node B3. The fifth n-channel MOS field effect transistor Q5 is connected in series between the first node B1 and a ground line GND having a ground voltage GND. The substrate of the fifth n-channel MOS field effect transistor Q5 is connected to ground line GND such that the substrate has a ground voltage GND. A gate of the fifth n-channel MOS field effect transistor Q5 is connected to the input terminal VIN. The sixth p-channel MOS field effect transistor Q6 is connected in series between the second node B2 and an internal power voltage line VINT having an internal power voltage VINT. The substrate of the sixth p-channel MOS field effect transistor Q6 is connected to the internal power voltage line VINT such that the substrate has an internal power voltage VINT. The gate of the sixth p-channel MOS field effect transistor Q6 is connected to the input terminal VIN. The seventh n-channel MOS field effect transistor Q7 is connected in series between the first node B1 and the third node B3. The substrate of the seventh n-channel MOS field effect transistor Q7 is connected to ground line GND such that the substrate has a ground voltage GND. A gate of the seventh n-channel MOS field effect transistor Q7 is connected to the internal power voltage line VINT. The eighth p-channel MOS field effect transistor Q8 is connected in series between the second node B2 and the third node B3. The substrate of the eighth p-channel MOS field effect transistor Q8 is connected to the internal power voltage line VINT such that the substrate has an internal power voltage VINT. The gate of the eighth p-channel MOS field effect transistor Q8 is connected to the ground line GND. The fifth and seventh n-channel MOS field effect transistors Q5 and Q7 are connected in series between the third node B3 and the ground line GND. The sixth and eighth p-channel MOS field effect transistors Q6 and Q8 are also connected in series between the internal power voltage line VINT and the third node B3.

Compared with the existing level converter circuit, the transistors Q1, Q2, Q3, Q4, Q5 and Q6 of the new level converter circuit are the transistors Q1, Q2, Q3, Q4, Q5 and Q6 of the existing level converter circuit. Have the same size as). The remaining transistors Q7 and Q8 have the same size or smaller size than the transistors Q5 and Q6, respectively. The inverter D1 has a size capable of driving the transistors Q7 and Q8.

The timing waveform diagrams of the novel level converter circuit shown in FIG. 7 remain essentially unchanged from those shown in FIG.

First, the rising operation of the output voltage VOUT will be described.

When the input voltage VIN is at the ground level GND, the third node B3 at the output side of the inverter D1 has the voltage level VINT, while the first node B1 has the voltage level VPP. ), The second node B2 has a voltage level VINT, and the output terminal VOUT has a voltage level VBB. Transistors Q1, Q5, Q7 and Q4 remain in non-conductive states or off, while the remaining transistors Q6, Q2, Q3 and Q8 remain conductive or on, so that individual nodes Connected to the field.

When the input voltage VIN is increased from the ground level GND to the voltage level VINT, the potential of the third node B3 falls from the voltage level VINT to the ground level GND.

When the input voltage VIN is not lower than the voltage level VTN corresponding to the threshold voltages of the n-channel MOS field effect transistors, the fifth transistor Q5 having the gate receiving the input voltage VIN is turned on or When the potential of the third node B3, which is in the conduction state and further becomes the output side of the inverter D1, drops to the ground level GND, the seventh transistor Q7 connected to the third node B3 is turned ON or ON. The conduction state remains, so that the potential of the first node B1 falls to the ground level GND.

When the input voltage VIN is not lower than the voltage level VINT- | VTP | when the VTP corresponds to the threshold voltages of the p-channel MOS field effect transistors, the first gate having the gate for receiving the input voltage VIN is formed. The sixth transistor Q6 is turned off or is in a non-conductive state. Furthermore, when the potential of the third node B3, which is the output side of the inverter D1, drops to the ground level GND, the eighth connected to the third node B3 is closed. Transistor Q8 is turned on or in a conductive state, so that the potential of second node B2 drops to approach the voltage level | VTP |. At this time, since the source and drain voltages of the eighth transistor Q8 or the voltage applied across the second node B2 and the ground line GND are reduced, the driving capability of the eighth transistor Q8 is dropped and the second node (8) is reduced. The potential or voltage level of B2) gradually falls.

When the potential or voltage level of the first node B1 does not become higher than the voltage level VINT-VTP, the first transistor Q1 is turned on or the third transistor Q3 is left in a conductive state or in an on state. State, and for this reason, the output voltage VOUT gradually increases.

When the output voltage VOUT is not lower than the voltage level VBB + VTN, the fourth transistor Q4 is turned on or in a conductive state, and the potential or voltage level of the second node B2 is the voltage level VBB. Falls into. As a result, the third and eighth transistors Q3 and Q8 are brought into a non-conductive state or turned off. At this time, the output voltage VOUT is increased to the voltage level VPP and the second transistor Q2 remains in the off state or the non-conductive state, while the first and fifth transistors Q1 and Q5 are in the on state or It remains in a conductive state.

Next, the lowering operation of the output voltage VOUT will be described.

When the input voltage VIN is at the voltage level VINT, the third node B3 at the output side of the inverter D1 has a ground level GND, while the first node B1 has a ground level GND. The second node B2 has a voltage level VBB and the output terminal VOUT has a voltage level VPP. Transistors Q2, Q3, Q6 and Q8 are either in the non-conductive state or in the off state, while the remaining transistors Q1, Q4, Q5 and Q7 are in the conducting state or on state so that the individual nodes are connected to the power voltages. Connected.

When the input voltage VIN falls from the voltage level VINT to the ground level GND, the potential of the third node B3 is increased from the ground level GND to the voltage level VINT.

When the input voltage VIN does not become higher than the voltage level VINT- | VTP |, the sixth transistor Q6 having a gate that receives the input voltage VIN is turned on or in a conducting state and furthermore, the inverter D1. If the potential of the third node B3, which is the output side of the power source, increases to the voltage level VINT, the eighth transistor Q8 connected to the third node B3 is turned on or in a conducting state, so that the second node B2 The potential is increased to the voltage level VINT.

When the input voltage VIN is not higher than the voltage level VTN, the fifth transistor Q5 having the gate receiving the input voltage VIN is turned off or in a non-conductive state, and further, the inverter D1 is turned off. When the potential of the third node B3 on the output side is increased to the voltage level VITN, the seventh transistor Q7 connected to the third node B3 is turned on or in a conductive state, and thus the potential of the first node B1 is turned on. Is increased to approach the voltage level (VINT-VTN). In this case, since the source and drain voltages of the seventh transistor Q7 or the voltage applied across the first node B1 and the third node B3 are reduced, the driving capability of the seventh transistor Q7 is reduced to thereby reduce the first and second voltages. The potential or voltage level of the node B1 is gradually increased.

When the potential or voltage level of the second node B2 is not lower than the voltage level VBB + VTN, the third transistor Q3 is turned on or in a conductive state.

When the output voltage VOUT does not become higher than the voltage level VPP- | VTP |, the second transistor Q2 is turned on or in a conductive state, and the potential or voltage level of the first node B1 is set to the voltage level ( VPP). As a result, the first and seventh transistors Q1 and Q7 are brought into a non-conductive state or turned off. At this time, the output voltage VOUT drops to the voltage level VBB and the fourth transistor Q4 remains in the off state or the non-conductive state, while the third and sixth transistors Q3 and Q6 are in the on state or in the conduction state. Will remain in the state.

In the voltage raising operation of the novel level converter circuit shown in FIG. 7, the potential or voltage level of the first node B1 is increased by the parallel operation of the fifth and seventh transistors Q5 and Q7. As a result, the transition time to the ground level GND of the first node B1 is shortened, and the current driving capability of the first transistor Q1 is further improved. For this reason, the increase time of the output voltage VOUT is increased to the first node B1. It becomes short compared with an Example.

In the voltage drop operation of the novel level converter circuit shown in Fig. 7, the potential or voltage level of the second node B2 is increased by the parallel operation of the sixth and eighth transistors Q6 and Q8. As a result, the transition time of the second node B2 to the internal power voltage level VINT is shortened, and the current driving capability of the third transistor Q3 is further improved, and for this reason, the fall time of the output voltage VOUT is This becomes shorter than in the first embodiment.

(Example 4)

A fourth embodiment according to the present invention is described in detail with reference to Fig. 8, which is a circuit diagram showing a novel level converter circuit capable of exhibiting a high speed logic voltage level converting operation. The circuit configuration of the novel level converter circuit will be described below.

The novel level converter circuit has an input section and a driver section. The input section has an input terminal to which the input voltage VIN inputs there, and the driver section has an output terminal to which the output voltage VOUT outputs therefrom. The input unit and the driver unit are connected through the first and second nodes B1 and B2. The input unit has input logic gates biased between the internal power voltage VINT and the ground level GND. The driver unit has a driver circuit biased between the high power voltage VPP higher than the internal power voltage VINT and the low power voltage VBB lower than the ground level GND. The novel level converter circuit converts internal logic levels, for example, a high level such as the internal power voltage VINT and a low level such as the ground level GND, to a high power voltage VPP and a low power voltage VBB. Let's do it.

The circuit configuration of the driver section of the novel level converter circuit is the same as that of the existing level converter circuit described above. That is, the driver section of the novel level converter circuit has first and second p-channel MOS field effect transistors Q1 and Q2 and third and fourth n-channel MOS field effect transistors Q3 and Q4. The first p-channel MOS field effect transistor Q1 is connected in series between the high power voltage line VPP having the high power voltage VPP and the output terminal VOUT. The substrate of the first p-channel MOS field effect transistor Q1 is electrically connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. The gate of the first p-channel MOS field effect transistor Q1 is connected to the first node B1. The third n-channel MOS field effect transistor Q3 is connected in series between the low power voltage line VBB having the low power voltage VBB and the output terminal VOUT. The substrate of the third n-channel MOS field effect transistor Q3 is electrically connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the third n-channel MOS field effect transistor Q3 is connected to the second node B2. The second p-channel MOS field effect transistor Q2 is connected in series between the high power voltage line VPP having the high power voltage VPP and the first node B1. The substrate of the second p-channel MOS field effect transistor Q2 is electrically connected to the high power voltage line VPP such that the substrate has a high power voltage VPP. The gate of the second p-channel MOS field effect transistor Q2 is connected to the output terminal VOUT. The fourth n-channel MOS field effect transistor Q4 is connected in series between the low power voltage line VBB having the low power voltage VBB and the second node B2. The substrate of the fourth n-channel MOS field effect transistor Q4 is electrically connected to the low power voltage line VBB such that the substrate has a low power voltage VBB. The gate of the fourth n-channel MOS field effect transistor Q4 is connected to the output terminal VOUT.

The input of the novel level converter circuit is an inverter D1, fifth, eleventh and twelfth n-channel MOS field effect transistors Q5, Q11 and Q12 and sixth, ninth and tenth p-channel MOS field effect transistors. (Q6, Q9 and Q10). The fifth n-channel MOS field effect transistor Q5 is connected in series between the first node B1 and a ground line GND having a ground voltage GND. The substrate of the fifth n-channel MOS field effect transistor Q5 is connected to ground line GND such that the substrate has a ground voltage GND. A gate of the fifth n-channel MOS field effect transistor Q5 is connected to the input terminal VIN. The sixth p-channel MOS field effect transistor Q6 is connected in series between the second node B2 and an internal power voltage line VINT having an internal power voltage VINT. The substrate of the sixth p-channel MOS field effect transistor Q6 is connected to the internal power voltage line VINT such that the substrate has an internal power voltage VINT. The gate of the sixth p-channel MOS field effect transistor Q6 is connected to the input terminal VIN. The ninth and tenth p-channel MOS field effect transistors Q9 and Q10 are connected to the internal power voltage VINT while the ninth p-channel MOS field effect transistor Q9 is connected to the internal power voltage VINT. Q10) is connected in series between the first node B1 and the internal power voltage line VINT so that Q10 is connected to the first node B1. The substrate of the ninth p-channel MOS field effect transistor Q9 is connected to the internal power voltage line VINT such that the substrate has an internal power voltage VINT. The substrate of the tenth p-channel MOS field effect transistor Q10 is also connected to the internal power voltage line VINT such that the substrate has an internal power voltage VINT. A gate of the ninth p-channel MOS field effect transistor Q9 is connected to the tenth p-channel MOS field effect transistor Q10. A gate of the tenth p-channel MOS field effect transistor Q1 is connected to the input terminal VIN. The eleventh and twelfth n-channel MOS field effect transistors Q11 and Q12 are connected to the ground line GND while the eleventh n-channel MOS field effect transistor Q11 is connected to the ground line GND. ) Is connected in series between the second node (B2) and the ground line (GND) so that is connected to the second node (B2). The substrate of the eleventh n-channel MOS field effect transistor Q11 is connected to the ground line GND such that the substrate has a ground voltage GND. The substrate of the twelfth n-channel MOS field effect transistor Q12 is also connected to the ground line GND such that the substrate has a ground voltage GND. A gate of the eleventh n-channel MOS field effect transistor Q11 is connected to the twelfth n-channel MOS field effect transistor Q12. A gate of the 12th n-channel MOS field effect transistor Q12 is connected to the input terminal VIN.

The ninth and tenth transistors Q9 and Q10 have the same size as the sixth transistor Q6. The eleventh and twelfth transistors Q11 and Q12 have the same size as the fifth transistor Q5.

First, the rising operation of the output voltage VOUT will be described.

When the input voltage VIN is at the ground level GND, the first node B1 has the voltage level VPP, the second node B2 has the voltage level VINT, and the output terminal VOUT is Has a voltage level VBB. Transistors Q1, Q5, Q4 and Q12 are in non-conducting or off states, while the remaining transistors Q6, Q2, Q3 and Q10 are in conducting or on state so that individual nodes Connected to the field.

When the input voltage VIN is not lower than the voltage level VTN corresponding to the threshold voltages of the n-channel MOS field effect transistors, the fifth transistor Q5 having the gate receiving the input voltage VIN is turned on or In a conductive state, the potential or voltage level of the first node B1 falls to the ground level GND. When the input voltage VIN becomes the internal power voltage, the potential of the first node B1 is not higher than the voltage level (VINT + | VTP |) when VTP corresponds to the threshold voltage of the p-channel MOS field effect transistors. As a result, the tenth transistor Q10 having a gate receiving the input voltage VIN is turned off or is in a non-conductive state.

When the input voltage VIN is not lower than the voltage level VINT- | VTP | when VTP corresponds to the threshold voltage of the p-channel MOS field effect transistors, the gate voltage receiving the input voltage VIN is provided. The sixth transistor Q6 is turned off or in a non-conductive state. When the input voltage VIN becomes the voltage level VINT, the twelfth transistor Q12 having the gate connected to the input terminal VIN is turned on or in a conductive state, so that the potential of the second node B2 is dropped to the voltage level (VINT). VTP). At this time, since the source and drain voltages of the twelfth transistor Q12 are reduced, the driving capability of the twelfth transistor Q12 is reduced, and the potential or voltage level of the second node B2 is gradually decreased.

When the potential or voltage level of the first node B1 is not higher than the voltage level VINT- | VTP |, the first transistor Q1 is turned on or the third transistor Q3 is left in the conducting state or on state. The output voltage VOUT gradually increases.

When the output voltage VOUT is not lower than the voltage level VBB + VTN, the fourth transistor Q4 is turned on or in a conductive state, and the potential or voltage level of the second node B2 is the voltage level VBB. Falls into. As a result, the third transistor Q3 is brought into a nonconductive state or turned off. At this time, the output voltage VOUT is increased to the voltage level VPP and the second and tenth transistors Q2 and Q10 remain in the off state or the non-conductive state, while the first and fifth transistors Q1 and Q5) remains on or in the conduction state.

Next, the lowering operation of the output voltage VOUT will be described.

When the input voltage VIN is at the voltage level VINT, the first node B1 has a ground level GND, the second node B2 has a voltage level VBB, and the output terminal VOUT has a voltage. Level VPP. Transistors Q2, Q3, Q6 and Q10 are either in the non-conductive state or in the off state, while the remaining transistors Q1, Q4, Q5 and Q12 are in the conducting or on state so that the individual nodes are connected to the power voltages. Connected.

When the input voltage VIN does not become higher than the voltage level VINT- | VTP |, the sixth transistor Q6 having a gate that receives the input voltage VIN is turned on or in a conducting state, so that the second node ( The potential of B2) is increased to the voltage level VINT. When the input voltage VIN becomes the ground level GND and the potential of the second node B2 is not lower than the voltage level GND-VTN, the twelfth transistor Q12 is turned off or in a non-conductive state. .

When the input voltage VIN is not higher than the voltage level VTN, the fifth transistor Q5 having the gate receiving the input voltage VIN is turned off or in a non-conductive state, and furthermore, the input voltage VIN If the ground level GND is reached, the tenth transistor Q10 having the gate connected to the input voltage VIN is turned on or in a conductive state, so that the potential of the first node B1 is increased so that the voltage level VINT− | VTN | At this time, since the source and drain voltages of the tenth transistor Q10 are reduced, the driving capability of the tenth transistor Q10 is reduced, and the potential or voltage level of the first node B1 is gradually increased.

When the potential or voltage level of the second node B2 is not lower than the voltage level VBB + VTN, the third transistor Q3 is turned on or in a conductive state.

When the output voltage VOUT does not become higher than the voltage level VPP- | VTP |, the second transistor Q2 is turned on or in a conductive state, and the potential or voltage level of the first node B1 is set to the voltage level ( VPP). As a result, the first transistor Q1 is brought into a nonconductive state or turned off. At this time, the output voltage VOUT drops to the voltage level VBB and the fourth and twelfth transistors Q4 and Q12 remain in the off state or the non-conducting state, while the third and sixth transistors Q3 and Q6. ) Remains on or conducting.

In the novel level converter circuit shown in FIG. 8, the ninth transistor Q9 is provided to prevent conduction between the high power voltage line VPP and the internal power voltage line VINT. In addition, the eleventh transistor Q11 is provided to prevent conduction between the ground line GND and the low power voltage line VBB. As a result, the gate of the first transistor Q1 in the driver portion is controlled or driven by a CMOS inverter circuit including the fifth and tenth transistors Q5 and Q10. The gate of the third transistor Q3 in the driver portion is controlled or driven by another CMOS inverter circuit including the sixth and twelfth transistors Q6 and Q12. This circuit configuration causes high-speed changes in the potentials of the first and second nodes B1 and B2, so that the level converter circuit of this embodiment can execute a high speed voltage level converting operation.

Modifications of the invention will be apparent to those of ordinary skill in the art to which the invention pertains, and therefore, it is to be understood that the embodiments shown and illustrated are by no means intended to be considered in a limiting sense. will be. Accordingly, all modifications that come within the spirit and scope of the invention are intended to be completely covered by the claims.

Claims (12)

A voltage level converter circuit for converting a set of original logic voltage levels into a different set of converted voltage levels, different from the voltage levels, comprising: a driver portion and an input portion coupled to the driver portion; The unit has an output terminal from which an output signal is output therefrom, the input unit has an input terminal to which an input signal is input therein, the driver unit selectively supplies one of the converted voltage levels to the output terminal, and the input unit is Controlling the driver unit to selectively supply one of the converted voltage levels to the output terminal according to the input signal, and the gates of the driver side transistors provided to the driver unit and directly connected to the output terminal, Gates are driven by input transistors A voltage level converter circuit coupled to the input side transistors, the gate being provided to the input and having a gate connected directly to the input terminal to be driven directly. 2. The method of claim 1, wherein the high level of the converted voltage levels is higher than the high level of the original voltage levels and the low level of the converted voltage levels is low level of the original voltage levels. Lower, voltage level converter circuit. The apparatus of claim 1, wherein the input unit comprises: an inverter having an input side connected to the input terminal; And a gate provided between the high and low lines having a high voltage level and an original low voltage level and having gates connected to the input terminal and an output side of the inverter, the series driving the gates of the driver transistors in the driver section. A voltage level converter circuit comprising coupling transistors. The apparatus of claim 1, wherein the input unit comprises: an inverter having an input side connected to the input terminal; One of the driver transistors in the driver section having gates connected between the input terminal and the output side of the inverter and provided between the high and low voltage lines having a high converted voltage level and an original low voltage level, respectively First series connected transistors for driving said gate having; And gates connected between the high and low voltage lines having the original high voltage level and the converted voltage level of the low, respectively, and having gates connected to the input terminal and the output side of the inverter, wherein the other of the driver transistors in the driver section are provided. A voltage level converter circuit comprising second series connected transistors for driving the gate having one. The apparatus of claim 1, wherein the input unit comprises: an inverter having an input side connected to the input terminal; One of the driver transistors in the driver section having gates provided between the low voltage line having the original low voltage level and the output side of the inverter and connected to the input terminal and the high voltage line having the original high voltage level First series connected transistors for driving said gate having; And gates connected between the low voltage line having the original high voltage level and the output side of the inverter and connected to the input terminal and the low voltage line having the original low voltage level, wherein the other of the driver transistors in the driver section is provided. A voltage level converter circuit comprising second series connected transistors for driving the gate having one. The low voltage line of claim 1, wherein the input unit has gates connected to the input terminal and drives the gate of one of the driver transistors in the driver unit. A first CMOS inverter between transistors connected to a high voltage line having a high voltage; And a high voltage line having an original high voltage level and a low voltage line having an original low voltage, having gates connected to the input terminal, for driving the gate of one of the driver transistors in the driver portion. A voltage level converter circuit comprising a second CMOS inverter between transistors. The driver portion has an output stage from which an output signal is output therefrom, the input portion has an input stage from which an input signal is input therein, the driver portion selectively supplies one of the converted voltage levels to the output stage, and the input portion is Controlling the driver unit to selectively supply one of the converted voltage levels to the output terminal according to the input signal, Wherein the gates of the driver side transistors provided in the driver section and directly connected to the output stage are input side transistors having gates provided in the input section and directly connected to the input terminal such that the gates of drive side transistors are driven directly by input side transistors. Circuitry of an input portion connected to a driver portion in a voltage level converter circuit for converting a set of original logic voltage levels, which are connected to the circuit boards, into a set of converted voltage levels different from the voltage levels. 8. The method of claim 7, wherein the high level of the converted voltage levels is higher than the high level of the original voltage levels and the low level of the converted voltage levels is low level of the original voltage levels. Lower circuitry. 8. The apparatus of claim 7, wherein the input unit comprises: an inverter having an input side connected to the input terminal; A series connection provided between the high and low voltage lines having a high voltage level and an original low voltage level and having gates connected to the input terminal and an output side of the inverter, the series connection for driving the gates of the driver transistors in the driver section Circuit device comprising transistors. 8. The apparatus of claim 7, wherein the input unit comprises: an inverter having an input side connected to the input terminal; One of the driver transistors in the driver section having gates connected between the input terminal and the output side of the inverter and provided between the high and low voltage lines having a high converted voltage level and an original low level voltage, respectively, First series connected transistors for driving said gate having; And gates connected between the high and low voltage lines having the original high voltage level and the converted voltage level of the low, respectively, and having gates connected to the input terminal and the output side of the inverter, wherein the other of the driver transistors in the driver section are provided. And a second series connection transistor for driving the gate having one. 8. The apparatus of claim 7, wherein the input unit comprises: an inverter having an input side connected to the input terminal; One of the driver transistors in the driver section having gates provided between the low voltage line having the original low voltage level and the output side of the inverter and connected to the input terminal and the high voltage line having the original high voltage level First series connected transistors for driving said gate having; And gates connected between the original high voltage level and the output side of the inverter and connected to the low voltage line having the input terminal and the original low voltage level, wherein the other of the driver transistors in the driver section has the A circuit device comprising second series connected transistors for driving a gate. The low voltage line of claim 7, wherein the input unit has gates connected to the input terminal and drives the gate of one of the driver transistors in the driver unit. A first CMOS inverter between transistors connected to a high voltage line having a high voltage; And a high voltage line having an original high voltage level and a low voltage line having an original low voltage, having gates connected to the attraction end, and driving the gate of one of the driver transistors in the driver unit. A circuit device comprising a second CMOS inverter between connected transistors.