KR100299304B1 - Method for manufacturing semiconductor memory module - Google Patents

Method for manufacturing semiconductor memory module Download PDF

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Publication number
KR100299304B1
KR100299304B1 KR1019980018421A KR19980018421A KR100299304B1 KR 100299304 B1 KR100299304 B1 KR 100299304B1 KR 1019980018421 A KR1019980018421 A KR 1019980018421A KR 19980018421 A KR19980018421 A KR 19980018421A KR 100299304 B1 KR100299304 B1 KR 100299304B1
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KR
South Korea
Prior art keywords
semiconductor memory
chip
memory module
printed circuit
circuit board
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KR1019980018421A
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Korean (ko)
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KR19990068255A (en
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노길섭
남기환
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노길섭
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Priority to KR1019980018421A priority Critical patent/KR100299304B1/en
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Publication of KR100299304B1 publication Critical patent/KR100299304B1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

Abstract

PURPOSE: A method for manufacturing a semiconductor memory module is provided to obtain a minimized and thin film module by manufacturing the semiconductor memory module using a bonding, a molding and sealing processes after directly mounting a chip on a printed circuit substrate. CONSTITUTION: A printed circuit substrate(41) having a bonding position(44) is provided. A chip bonding pad(32) is formed on an individual chip(31). The bonding position(44) and the chip bonding pad(32) of the individual chip(31) are connected electrically using a wire bonding process. A protect layer is formed on the printed circuit substrate including the individual chip by using a molding and sealing processes, thereby forming a semiconductor memory module of a thin film and a small type.

Description

반도체 메모리 모듈 제조 방법Semiconductor memory module manufacturing method

본 발명은 반도체 메모리 모듈(memory module) 제조 방법에 관한 것으로, 특히 제조 공정의 개선을 통해 원가 절감, 생산성 향상, 소형화 및 박형화를 이룰 수 있는 반도체 메모리 모듈 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory module, and more particularly, to a method of manufacturing a semiconductor memory module capable of reducing costs, improving productivity, miniaturization, and thickness through improvement of a manufacturing process.

반도체 메모리 모듈은 규칙성과 분리성을 가진 몇 개의 부품 및 소자로 구성되며, 어떤 정해진 기능을 다하는 단일 부품 단위로 간주되는 조립회로이다. 이러한 반도체 메모리 모듈은 대부분의 전자기기에 적용되고 있다. 최근 전자기기의 소형화 및 박형화에 따라 반도체 메모리 모듈 역시 소형화 및 박형화가 요구되고 있으며, 또한 제조 업체간의 경쟁력 강화를 위해 생산성 향상 및 원가 절감이 필수적이다.A semiconductor memory module is composed of several parts and elements with regularity and separation, and is an assembly circuit regarded as a single part unit performing a predetermined function. Such semiconductor memory modules are applied to most electronic devices. With the recent miniaturization and thinning of electronic devices, semiconductor memory modules are also required to be miniaturized and thinned. In addition, productivity improvement and cost reduction are essential to enhance competitiveness among manufacturers.

도 1은 일반적인 패키지(package)의 단면도이고, 도 2는 도 1의 패키지가 인쇄회로기판에 설치된 종래 반도체 메모리 모듈의 사시도이다.1 is a cross-sectional view of a typical package, and FIG. 2 is a perspective view of a conventional semiconductor memory module in which the package of FIG. 1 is installed on a printed circuit board.

도 1을 참조하면, 패키지(10)는 웨이퍼 프로브 테스트(wafer probe test)후에 웨이퍼 마운팅(wafer mounting) 공정과 웨이퍼 절삭(wafer dicing saw) 공정을 통해 개별 칩(chip; 11)으로 분리시킨다. 이 개별 칩(11)은 칩 접착(chip attaching) 공정을 통해 칩 지지 패들(chip support paddle; 12)에 접착물질을 이용하여 리드 프레임(lead frame; 13)에 부착된다. 칩(11)에 형성된 칩 본딩 패드(chip bonding pad; 14)와 리드 프레임(13)간을 와이어 본딩(wire bonding) 공정을 통해 와이어(15)로 연결시킨다. 와이어 본딩 공정이 끝난 칩(11) 및 와이어(15)를 외부의 각종 손상(damage) 요인으로부터 보호하기 위해 몰딩(molding) 및 실링(sealing) 공정을 통해 칩 주변을 보호재로 봉지하고 성형하는 작업을 통해 보호막(16)을 형성시킨다. 이러한 공정을 진행한 후, 리드 프레임(13)의 모양을 규정된 모양에 따라 만들고 분리시켜 하나의 완전한 집적회로(IC)로서의 구실을 할 수 있도록, 물리/화학적 디플래쉬(mechanical/chemical deflash) 공정, 틴 플래팅(tin plating) 공정, 트림(trim) 공정, 폼/싱글레이션(form/singulation) 공정, 프리테스트(pretest) 공정, 번-인 테스트(burn-in test) 공정 및 포스트 테스트(post test) 공정 등을 통해 패키지(10) 제조가 완료된다.Referring to FIG. 1, the package 10 is separated into individual chips 11 through a wafer mounting process and a wafer dicing saw process after a wafer probe test. Each individual chip 11 is attached to a lead frame 13 using an adhesive material to a chip support paddle 12 through a chip attaching process. A chip bonding pad 14 formed on the chip 11 and the lead frame 13 are connected to each other by a wire 15 through a wire bonding process. In order to protect the chip 11 and the wire 15 which have been wire-bonded from various damage factors, the sealing and molding of the chip surroundings with a protective material is performed through a molding and sealing process. Through the protective film 16 is formed. After this process, the shape of the lead frame 13 is formed according to the prescribed shape and separated so as to serve as a complete integrated circuit (IC), a mechanical / chemical deflash process. , Tin plating process, trim process, form / singulation process, pretest process, burn-in test process and post test The test 10 process is completed to manufacture the package 10.

이와 같이 제조된 패키지(10)를 이용하여, 도 2에 도시된 바와 같이, 반도체 메모리 모듈(20)을 제작하게 된다. 반도체 메모리 모듈(20)의 제작은 먼저 회로 패턴이 인쇄된 다층 인쇄회로기판(21)이 제공되고, 솔더 플럭스(solder flux)를 스크린 프린팅(screen printing)하여 다층 인쇄회로기판(21)의 선택된 부분에 패키지(10)를 개별적으로 설치(mount)하고, 솔더 리플로우(solder reflow)를 200 내지 270℃에서 실시함에 의해 완료된다. 미설명 부호(22)는 아웃 리드(out lead)이다.Using the package 10 manufactured as described above, as shown in FIG. 2, the semiconductor memory module 20 is manufactured. The fabrication of the semiconductor memory module 20 is first provided with a multilayer printed circuit board 21 printed with a circuit pattern, and a selected portion of the multilayer printed circuit board 21 by screen printing solder flux. The packages 10 are individually mounted and solder reflow is performed at 200 to 270 ° C. Reference numeral 22 is an out lead.

상기한 바와 같이, 종래 반도체 메모리 모듈(20)은 패키지 공정 순서에 따라 패키지(10)를 형성하고, 이 패키지(10)를 개별적으로 다층 인쇄회로기판(20)에 설치하여 제작된다. 일반적으로 집적회로 패키지(ICPKC)는 표면 실장형 패키지, 삽입형 패키지 및 기타 유형의 패키지로 나눌 수 있으며, 종래 반도체 메모리 모듈(20)에 적용된 패키지(10)는 이들 유형중 하나이다.As described above, the conventional semiconductor memory module 20 is manufactured by forming the package 10 according to the package process sequence, and installing the package 10 individually on the multilayer printed circuit board 20. In general, an integrated circuit package (ICPKC) may be divided into a surface mount package, an insert package, and other types of packages, and the package 10 applied to the conventional semiconductor memory module 20 is one of these types.

종래 반도체 메모리 모듈(20)은 패키지(10)를 별도로 제조하기 위하여 수 내지 수십 단계의 공정을 거쳐야하기 때문에 제조 공정이 길어 생산 단가가 높아질 뿐만 아니라, 패키지(10)를 직접 인쇄회로기판(21)에 설치해야하기 때문에 모듈(20)의 소형화 및 박형화가 어려워 제조 업체간의 경쟁력 저하를 초래하게 된다. 또한, 개별 패키지(10)를 인쇄회로기판(21)에 설치하기 위하여 솔더 플럭스를 사용함에 따라 솔더 조인트(solder joint)의 신뢰성(reliability) 저하 등의 문제를 야기시킨다.Since the semiconductor memory module 20 has to go through several to several tens of steps to separately manufacture the package 10, the manufacturing process is long and the production cost increases, and the package 10 directly prints the printed circuit board 21. Because it must be installed in the module 20, it is difficult to miniaturize and thin, which leads to a decrease in competitiveness among manufacturers. In addition, the use of solder flux to install the individual package 10 on the printed circuit board 21 causes problems such as deterioration in reliability of solder joints.

따라서, 본 발명은 개별 칩으로 패키지 제작을 완료한 후에 이 패키지를 인쇄회로기판에 설치하지 않고, 칩을 직접 인쇄회로기판에 설치한 후에 와이어 본딩 공정, 몰딩/실링 공정 등의 단순 공정으로 반도체 메모리 모듈을 제조하므로써, 원가 절감 및 생산성 향상은 물론 모듈의 소형화 및 박형화를 이룰 수 있는 반도체 메모리 모듈 제조 방법을 제공함에 그 목적이 있다.Therefore, the present invention does not install the package on a printed circuit board after the package is completed with individual chips, and the semiconductor memory can be manufactured by a simple process such as a wire bonding process or a molding / sealing process after the chip is directly installed on a printed circuit board. It is an object of the present invention to provide a method for manufacturing a semiconductor memory module that can reduce costs and improve productivity, as well as miniaturization and thickness of modules.

이러한 목적을 달성하기 위한 본 발명의 반도체 메모리 모듈 제조 방법은 본딩 포지션을 갖는 인쇄회로 기판을 제작하는 단계; 개별 칩에 칩 본딩 패드를 형성하는 단계; 와이어 본딩 공정을 통해 상기 인쇄회로 기판의 본딩 포지션과 상기 개별 칩의 칩 본딩 패드를 전기적으로 연결하는 단계; 및 몰딩/실링 공정을 통해 상기 개별 칩을 포함한 상기 인쇄회로 기판상에 보호막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The semiconductor memory module manufacturing method of the present invention for achieving the above object comprises the steps of fabricating a printed circuit board having a bonding position; Forming chip bonding pads on individual chips; Electrically connecting a bonding position of the printed circuit board and a chip bonding pad of the individual chip through a wire bonding process; And forming a protective film on the printed circuit board including the individual chips through a molding / sealing process.

제1도는 일반적인 패키지의 단면도.1 is a cross-sectional view of a typical package.

제2도는 제1도의 패키지가 인쇄회로기판에 설치된 종래 반도체 메모리 모듈의 사시도.2 is a perspective view of a conventional semiconductor memory module in which the package of FIG. 1 is installed on a printed circuit board.

제3a도 내지 제3c도는 본 발명의 제 1 실시예에 따른 반도체 메모리 모듈의 제조 방법을 설명하기 위한 사시도.3A to 3C are perspective views illustrating a method of manufacturing a semiconductor memory module according to a first embodiment of the present invention.

제4도는 제3a도의 4-4선을 따라 절단한 확대 단면도.4 is an enlarged cross-sectional view taken along line 4-4 of FIG. 3A.

제5도는 제3c도의 5-5선을 따라 절단한 본 발명의 제 1 실시예에 따른 반도체 메모리 모듈의 단면도.FIG. 5 is a cross-sectional view of a semiconductor memory module according to a first embodiment of the present invention, taken along line 5-5 of FIG. 3C.

제6도는 본 발명의 제 2 실시예에 따른 반도체 메모리 모듈의 단면도.6 is a cross-sectional view of a semiconductor memory module according to a second embodiment of the present invention.

제7a도 내지 제7c도는 본 발명의 제 3 실시예에 따른 반도체 메모리 모듈의 제조 방법을 설명하기 위한 단면도.7A to 7C are cross-sectional views illustrating a method of manufacturing a semiconductor memory module in accordance with a third embodiment of the present invention.

제8도는 제7a도의 "A"부분을 확대한 도면.8 is an enlarged view of a portion “A” of FIG. 7A.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

10 : 패키지 11, 31, 71 : 칩10: package 11, 31, 71: chip

12 : 칩 지지 패들 13 : 리드 프레임12 chip support paddle 13 lead frame

14, 32, 72 : 칩 본딩 패드 15, 51, 91 : 와이어14, 32, 72: chip bonding pads 15, 51, 91: wire

16, 53, 93 : 보호막 20, 345, 600, 780 : 반도체 메모리 모듈16, 53, 93: protective film 20, 345, 600, 780: semiconductor memory module

21, 41, 61, 81 : 인쇄회로기판 22, 42 : 아웃 리드21, 41, 61, 81: printed circuit board 22, 42: out lead

43a, 43b, 43c, 43d, 83a, 83b, 83c, 83d : 회로 패턴Circuit pattern: 43a, 43b, 43c, 43d, 83a, 83b, 83c, 83d

44, 84 : 본딩 포지션44, 84: bonding position

45a, 45b, 45c, 45d, 85a, 85b, 85c, 85d : 기판45a, 45b, 45c, 45d, 85a, 85b, 85c, 85d: substrate

46, 86 : 솔더 레지스트 47 : 홈46, 86: solder resist 47: groove

52, 92 : 접착층 87 : 관통공52, 92: adhesive layer 87: through hole

94 : 실링층94: sealing layer

이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 3(a) 내지 3(c)는 본 발명의 제 1 실시예에 따른 반도체 메모리 모듈의 제조 방법을 설명하기 위한 사시도이고, 도 4는 도 3(a)의 4-4선을 따라 절단한 확대 단면도이며, 도 5는 도 3(c)의 5-5선을 따라 절단한 본 발명의 제 1 실시예에 따른 반도체 메모리 모듈의 단면도이다.3 (a) to 3 (c) are perspective views illustrating a method of manufacturing a semiconductor memory module according to a first embodiment of the present invention, and FIG. 4 is cut along line 4-4 of FIG. 3 (a). 5 is an enlarged cross-sectional view, and FIG. 5 is a cross-sectional view of the semiconductor memory module according to the first embodiment of the present invention taken along the line 5-5 of FIG.

도 3(a)를 참조하면, 다수의 홈(47)을 갖는 다층 인쇄회로기판(41)과 다수의 칩(31)이 각각 제공된다. 홈(47)의 저면에는 접착층(52)이 형성된다. 칩 접착(chip attaching) 공정을 통해 다층 인쇄회로기판(41)의 홈(47)내에 칩(31)을 부착한다.Referring to FIG. 3A, a multilayer printed circuit board 41 having a plurality of grooves 47 and a plurality of chips 31 are provided, respectively. An adhesive layer 52 is formed on the bottom of the groove 47. The chip 31 is attached to the groove 47 of the multilayer printed circuit board 41 through a chip attaching process.

상기에서, 칩(31)은 웨이퍼 프로브 테스트(wafer probe test)후에 웨이퍼 마운팅(wafer mounting) 공정과 웨이퍼 절삭(wafer dicing saw) 공정을 통해 개별 칩(31)으로 분리되고, 칩(31)의 상단면 가장자리에는 다수의 칩 본딩 패드(32)가 형성된다. 다층 인쇄회로기판(41)은, 도 4에 도시된 바와 같이, 다수의 기판(45a, 45b, 45c 및 45d) 각각의 상부에 회로 패턴(43a, 43b, 43c 및 43d)이 형성되어 적층을 이루고, 다수의 아웃 리드(42)가 형성되며, 칩(31)이 설치될 위치에 칩(31)이 내장될 수 있도록 다수의 홈(47)을 형성하여 제작된다. 홈(47) 주변의 제 1 회로 패턴(43a)의 일부가 노출되어 본딩 포지션(44)이 형성되도록, 다층 인쇄회로기판(41) 상부에 솔더 레지스트(solder resist; 46)를 도포 한다. 제 1 회로 패턴(43a)의 본딩 포지션(44)에는 금이나 은을 도금한다. 홈(47)은 제 1 회로 패턴(43a)과 제 1 기판(45a)으로 된 제 1 층만을 일부 제거하여 형성하거나, 제 2 회로 패턴(43b)과 제 2 기판(45b)으로 된 제 2 층까지 제거하여 형성할 수 있으며, 설계 규칙에 따라 그 깊이를 달리할 수 있다. 접착층(52)은 돗팅(dotting), 프린팅(printing) 또는 테이프(tape)에 의한 방식으로 형성된다.In the above, the chip 31 is separated into individual chips 31 through a wafer mounting process and a wafer dicing saw process after a wafer probe test, and an upper end of the chip 31. A plurality of chip bonding pads 32 are formed at the surface edges. As shown in FIG. 4, the multilayered printed circuit board 41 is stacked by forming circuit patterns 43a, 43b, 43c, and 43d on top of each of the plurality of substrates 45a, 45b, 45c, and 45d. A plurality of out leads 42 are formed, and a plurality of grooves 47 are formed so that the chips 31 may be embedded at the positions where the chips 31 are to be installed. A solder resist 46 is applied on the multilayer printed circuit board 41 so that a portion of the first circuit pattern 43a around the groove 47 is exposed to form a bonding position 44. The bonding position 44 of the first circuit pattern 43a is plated with gold or silver. The groove 47 is formed by partially removing only the first layer made of the first circuit pattern 43a and the first substrate 45a, or the second layer made of the second circuit pattern 43b and the second substrate 45b. It can be removed and formed, and its depth can be changed according to design rules. The adhesive layer 52 is formed in a manner by dotting, printing or tape.

도 3(b)를 참조하면, 와이어 본딩(wire bonding) 공정을 통해 칩(31)의 칩 본딩 패드(32)와 제 1 회로 패턴(43a)의 본딩 포지션(44)사이에 와이어(51)를 형성시킨다.Referring to FIG. 3B, the wire 51 is interposed between the chip bonding pad 32 of the chip 31 and the bonding position 44 of the first circuit pattern 43a through a wire bonding process. To form.

도 3(c)를 참조하면, 와이어 본딩 공정이 끝난 칩(31)과 와이어(51)를 외부의 각종 손상(damage) 요인으로부터 보호하기 위해 몰딩(molding) 및 실링(sealing) 공정을 통해 칩 주변을 보호재로 봉지하고 성형하는 작업을 통해 보호막(53)을 형성시켜 본 발명의 제 1 실시예에 따른 반도체 메모리 모듈(345)이 완성되며, 이의 단면이 도 5에 도시된다.Referring to FIG. 3 (c), the chip 31 and the wire 51 having finished the wire bonding process are protected around the chip through a molding and sealing process to protect the chip 31 and the wire 51 from external damage factors. Is formed by encapsulating and forming a protective film 53 to form a protective film 53, thereby completing the semiconductor memory module 345 according to the first embodiment of the present invention, the cross section of which is shown in FIG.

상기한 공정으로 제조된 제 1 실시예에 따른 반도체 메모리 모듈(345)은 다층 인쇄회로기판(41)에 홈(47)을 형성하여 홈(47)내에 칩(31)을 직접 내장시키고, 칩(31)이 내장된 다층 인쇄회로기판(41) 자체를 몰딩하므로써, 도 2에 도시된 종래 반도체 메모리 모듈(20)과 같이 패키지(10)를 다층 인쇄회로기판(21)에 직접 설치하는 것보다 소형화 및 박형화를 이룰 수 있고, 특히 본 발명의 반도체 메모리 모듈(345)에 적용되는 모든 칩(31)에는 도 1에 도시된 리드 프레임(13)의 설치가 필요 없기 때문에 더욱 소형화 및 박형화를 이룰 수 있다(종래 패키지는 패키지 유형에 따라 리드 프레임이 필요 없는 것도 있지만 도 1과 같이 필수적으로 리드 프레임을 설치해야 하는 것도 많음).In the semiconductor memory module 345 according to the first embodiment manufactured by the above process, the grooves 47 are formed in the multilayered printed circuit board 41 to directly embed the chips 31 in the grooves 47. The molding of the multilayered printed circuit board 41 itself, in which the 31 is embedded, can be made smaller than that of installing the package 10 directly on the multilayer printed circuit board 21 as in the conventional semiconductor memory module 20 shown in FIG. 2. And thinning, and in particular, since all the chips 31 applied to the semiconductor memory module 345 of the present invention do not need to install the lead frame 13 shown in FIG. 1, further miniaturization and thinning can be achieved. (A conventional package does not require a lead frame depending on the package type, but many require a lead frame as shown in FIG. 1).

또한, 본 발명의 제 1 실시예에 따른 반도체 메모리 모듈(345)은 칩(31)을 다층 인쇄회로기판(41)에 직접 설치한 후 몰딩하기 때문에, 도 2에 도시된 바와 같이 패키지(10) 제작후 이 패키지(10)를 인쇄회로기판(21)에 설치하는 것보다 공정적인 측면에서 단순화가 가능하여 생산성 향상 및 원가 절감을 이룰 수 있다.In addition, since the semiconductor memory module 345 according to the first embodiment of the present invention is molded after the chip 31 is directly installed on the multilayer printed circuit board 41, the package 10 as shown in FIG. 2. After fabrication, the package 10 can be simplified in terms of process rather than installing the package 10 on the printed circuit board 21, thereby improving productivity and reducing costs.

도 6은 본 발명의 제 2 실시예에 따른 반도체 메모리 모듈(600)의 단면도로서, 제 2 실시예에 따른 반도체 메모리 모듈(600)은 전술한 제 1 실시예에 따른 반도체 메모리 모듈(345)과 그 제조 공정은 동일하되, 단지 칩(31)을 내장할 수 있는 홈(47)이 형성되지 않은 다층 인쇄회로기판(61)상에 칩(31)을 직접 설치하여 제작된다. 홈(47)이 없는 다층 인쇄회로기판(61)이 적용된 제 2 실시예의 반도체 메모리 모듈(600)은 제 1 실시예의 반도체 메모리 모듈(345)과 비교하여 모듈의 박형화는 이룰 수는 없으나, 제조 공정은 제 1 실시예의 반도체 메모리 모듈(345)과 동일하기 때문에 종래 반도체 메모리 모듈(20)과 비교하여 소형화 및 박형화를 이룰 수 있을 뿐만 아니라 생산성 향상 및 원가 절감을 이룰 수 있다. 도 6의 지시 부호중 도 5의 지시 부호와 동일한 것은 동일한 명칭 및 부분임을 의미한다.FIG. 6 is a cross-sectional view of a semiconductor memory module 600 according to a second embodiment of the present invention. The semiconductor memory module 600 according to the second embodiment may include a semiconductor memory module 345 according to the first embodiment described above. The manufacturing process is the same, but is manufactured by directly installing the chip 31 on the multilayered printed circuit board 61 in which the groove 47 capable of embedding the chip 31 is not formed. The semiconductor memory module 600 of the second embodiment to which the multilayered printed circuit board 61 without the grooves 47 is applied cannot be made thinner than the semiconductor memory module 345 of the first embodiment. Since is the same as the semiconductor memory module 345 of the first embodiment, it is possible to achieve miniaturization and thickness as compared with the conventional semiconductor memory module 20, as well as to improve productivity and cost. The same reference numerals as those in FIG. 5 among the reference numerals in FIG. 6 mean the same names and parts.

도 7(a) 내지 7(c)는 본 발명의 제 3 실시예에 따른 반도체 메모리 모듈의 제조 방법을 설명하기 위한 단면도이고, 도 8은 도 7(a)의 "A"부분을 확대한 도면이다.7A to 7C are cross-sectional views illustrating a method of manufacturing a semiconductor memory module in accordance with a third embodiment of the present invention, and FIG. 8 is an enlarged view of portion “A” of FIG. 7A. to be.

도 7(a)를 참조하면, 다수의 관통공(87)을 갖는 다층 인쇄회로기판(81)과 다수의 칩(71)이 각각 제공된다. 관통공(87)의 후면 입구에는 접착층(92)이 형성된다. 관통공(87) 후면 입구의 접착층(92)에 의해 다층 인쇄회로기판(81)에 칩(71)이 직접 부착된다.Referring to FIG. 7A, a multilayer printed circuit board 81 having a plurality of through holes 87 and a plurality of chips 71 are provided, respectively. An adhesive layer 92 is formed at the rear inlet of the through hole 87. The chip 71 is directly attached to the multilayer printed circuit board 81 by the adhesive layer 92 at the rear inlet of the through hole 87.

상기에서, 칩(71)은 웨이퍼 프로브 테스트 후에 웨이퍼 마운팅 공정과 웨이퍼 절삭 공정을 통해 개별 칩(71)으로 분리되고, 칩(71)의 상단면 중앙부분에는 다수의 칩 본딩 패드(72)가 형성된다. 다층 인쇄회로기판(81)은, 도 8에 도시된 바와 같이, 다수의 기판(85a, 85b, 85c 및 85d) 각각의 상부에 회로 패턴(83a, 83b, 83c 및 83d)이 형성되어 적층을 이루고, 칩(71)이 설치될 위치에 다수의 관통공(87)을 형성하여 제작된다. 관통공(87) 앞면 주변의 제 1 회로 패턴(83a)의 일부가 노출되어 본딩 포지션(84)이 형성되도록, 다층 인쇄회로기판(81) 상부에 솔더 레지스트(86)를 도포 한다. 제 1 회로 패턴(83a)의 본딩 포지션(84)에는 금이나 은을 도금한다. 접착층(92)은 돗팅(dotting), 프린팅(printing) 또는 테이프(tape)에 의한 방식으로 관통공(87) 후면 입구에 형성된다.In the above, the chip 71 is separated into individual chips 71 through a wafer mounting process and a wafer cutting process after the wafer probe test, and a plurality of chip bonding pads 72 are formed at the center of the upper surface of the chip 71. do. 8, the multilayer printed circuit board 81 is stacked by forming circuit patterns 83a, 83b, 83c, and 83d on top of each of the plurality of substrates 85a, 85b, 85c, and 85d. The chip 71 is manufactured by forming a plurality of through holes 87 in the position where the chip 71 is to be installed. The solder resist 86 is coated on the multilayer printed circuit board 81 so that a portion of the first circuit pattern 83a around the front surface of the through hole 87 is exposed to form a bonding position 84. The bonding position 84 of the first circuit pattern 83a is plated with gold or silver. The adhesive layer 92 is formed at the back opening of the through hole 87 in a manner by dotting, printing or tape.

도 7(b)를 참조하면, 와이어 본딩 공정을 통해 칩(71)의 칩 본딩 패드(72)와 제 1 회로 패턴(83a)의 본딩 포지션(84)사이에 와이어(91)를 형성시킨다. 와이어(91)는 관통공(87)을 경유한다.Referring to FIG. 7B, a wire 91 is formed between the chip bonding pad 72 of the chip 71 and the bonding position 84 of the first circuit pattern 83a through a wire bonding process. The wire 91 passes through the through hole 87.

도 7(c)를 참조하면, 와이어 본딩 공정이 끝난 칩(71) 및 와이어(91)를 외부의 각종 손상 요인으로부터 보호하기 위해 몰딩 및 실링 공정을 통해 칩 주변을 보호재로 봉지하고 성형하는 작업을 통해 보호막(93) 및 실링층(94)을 형성시켜 본 발명의 제 3 실시예에 따른 반도체 메모리 모듈(780)이 완성된다. 제 3 실시예에 따른 반도체 메모리 모듈(780)은 리드 온 칩 타입(LOC type)이다.Referring to FIG. 7C, in order to protect the chip 71 and the wire 91 which have been finished with the wire bonding process from various damage factors from the outside, the operation of encapsulating and forming a chip around the chip with a protective material through a molding and sealing process is performed. The passivation layer 93 and the sealing layer 94 are formed through the semiconductor memory module 780 according to the third embodiment of the present invention. The semiconductor memory module 780 according to the third embodiment is a read on chip type (LOC type).

상기한 공정으로 제조된 제 3 실시예에 따른 반도체 메모리 모듈(780)은 전술한 제 1 및 2 실시예에 따른 반도체 메모리 모듈(345 및 600)과 제조 공정적인 측면에서 비교할 때, 제공된 다층 인쇄회로기판에 칩을 직접 설치하는 본 발명의 기본 원리와 동일하다. 따라서, 제 3 실시예에 따른 반도체 메모리 모듈(780) 역시 제공된 다층 인쇄회로기판에 패키지를 설치하는 종래 리드 온 칩 타입의 반도체 메모리 모듈과 비교하여 소형화 및 박형화를 이룰 수 있을 뿐만 아니라 생산성 향상 및 원가 절감을 이룰 수 있다.The semiconductor memory module 780 according to the third embodiment manufactured by the above process is a multilayer printed circuit provided when compared with the semiconductor memory modules 345 and 600 according to the first and second embodiments described above in terms of manufacturing process. It is the same as the basic principle of the present invention for directly installing a chip on a substrate. Accordingly, the semiconductor memory module 780 according to the third embodiment can also be made smaller and thinner than the conventional lead-on-chip type semiconductor memory module in which a package is installed on a multi-layer printed circuit board. Savings can be achieved.

전술한 본 발명의 제 1 및 2 실시예에 따른 반도체 메모리 모듈(345 및 600)은 몰딩 및 실링 공정을 통해 보호막을 일체형으로 형성하였으나, 제 3 실시예에 따른 반도체 메모리 모듈(780) 처럼 칩 각각에 보호막을 형성하는 분할형으로도 형성할 수 있다. 또한, 제 3 실시예에 따른 반도체 메모리 모듈(780)의 보호막 역시 일체형으로 형성할 수 있다.The semiconductor memory modules 345 and 600 according to the first and second embodiments of the present invention described above are integrally formed with a protective film through a molding and sealing process, but each of the chips is the same as the semiconductor memory module 780 according to the third embodiment. It can also be formed in a divided form in which a protective film is formed. In addition, the protective film of the semiconductor memory module 780 according to the third embodiment may also be integrally formed.

한편, 본 발명의 제 1, 2 및 3 실시예에 따른 반도체 메모리 모듈(345, 600 및 780)은 전자기기에 적용되는 다양한 반도체 메모리 모듈중 일부 유형을 실시예로하여 설명하였지만, 종래 반도체 메모리 모듈의 패키지 설치(package mount) 방식과는 달리 칩 설치(chip mount) 방식인 본 발명의 제조 원리를 이용하여 모든 유형의 반도체 메모리 모듈의 제조가 가능하다.Meanwhile, although the semiconductor memory modules 345, 600, and 780 according to the first, second, and third embodiments of the present invention have been described with some types of various semiconductor memory modules applied to electronic devices as embodiments, conventional semiconductor memory modules Unlike the package mount method of the present invention, all types of semiconductor memory modules can be manufactured using the manufacturing principle of the present invention, which is a chip mount method.

상술한 바와 같이, 본 발명은 개별 칩으로 패키지 제작을 완료한 후에 이 패키지를 인쇄회로기판에 설치하지 않고, 칩을 직접 인쇄회로기판에 설치한 후에 와이어 본딩 공정, 몰딩/실링 공정으로 반도체 메모리 모듈을 제조하므로써, 공정의 단순화를 통해 원가 절감 및 생산성 향상을 이룰 수 있고, 칩이 직접 인쇄회로기판에 설치되기 때문에 모듈의 소형화 및 박형화를 이룰 수 있어, 제조 업체간의 경쟁력을 높일 수 있다.As described above, the present invention does not install the package on the printed circuit board after the package is completed with the individual chips, and the semiconductor memory module is used in the wire bonding process and the molding / sealing process after the chip is directly installed on the printed circuit board. By reducing the cost, productivity can be reduced by simplifying the process, and productivity can be improved. Since the chip is directly installed on the printed circuit board, the module can be miniaturized and thinned, thereby increasing the competitiveness among manufacturers.

Claims (1)

본딩 포지션을 갖는 인쇄회로 기판을 제작하는 단계; 개별 칩에 칩 본딩 패드를 형성하는 단계; 와이어 본딩 공정을 통해 상기 인쇄회로 기판의 본딩 포지션과 상기 개별 칩의 칩 본딩 패드를 전기적으로 연결하는 단계; 및 몰딩/실링 공정을 통해 상기 개별 칩을 포함한 상기 인쇄회로 기판상에 보호막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 메모리 모듈 제조 방법.Fabricating a printed circuit board having a bonding position; Forming chip bonding pads on individual chips; Electrically connecting a bonding position of the printed circuit board and a chip bonding pad of the individual chip through a wire bonding process; And forming a protective film on the printed circuit board including the individual chips through a molding / sealing process.
KR1019980018421A 1998-05-21 1998-05-21 Method for manufacturing semiconductor memory module KR100299304B1 (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8498130B2 (en) 2009-04-10 2013-07-30 Samsung Electronics Co., Ltd. Solid state drive, structure for supporting solid state drives and scalable information processing system including a plurality of solid state drives
US8741665B2 (en) 2011-02-01 2014-06-03 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970003909Y1 (en) * 1994-04-08 1997-04-24 유태우 Diagnostic apparatus of acupuncture needle for surgical operation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970003909Y1 (en) * 1994-04-08 1997-04-24 유태우 Diagnostic apparatus of acupuncture needle for surgical operation

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8498130B2 (en) 2009-04-10 2013-07-30 Samsung Electronics Co., Ltd. Solid state drive, structure for supporting solid state drives and scalable information processing system including a plurality of solid state drives
US8741665B2 (en) 2011-02-01 2014-06-03 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor module

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