KR100298287B1 - Apparatus and Method of Managing Messages in a System Bus - Google Patents

Abstract

The present invention relates to an apparatus and method for processing a message on a system bus, and more particularly, to an apparatus and method for processing a message on a system bus in which a time division scheme is applied to the system bus so that buses having different transmission rates can be connected to the same bus structure. will be.

An apparatus according to the present invention includes a buffer unit for transmitting and receiving a message with another board; A memory unit having a reception buffer memory and a transmission buffer memory which are subdivided into a buffer unit composed of a maximum message size that can be transmitted, and which store received messages and transmitted messages, respectively; The input of the valid reception message is confirmed through the buffer unit, and the data is written to the memory unit according to the value of the reception input / output pointer, and the transmission message is written to the memory unit according to the value of the transmission input / output pointer, and then read and output to the buffer unit. And a bus logic unit configured to store input valid cell data in a memory address corresponding to a value of a received input pointer as a received message; Increasing the value of the received input pointer when all of the received messages have been stored; Checking and reading a received message stored in a memory; Increasing a value of a reception output pointer when all of the received messages are read; Reading the destination address area of the message to be transmitted and analyzing which self is the message to be sent; Recording a value of a transmission input pointer in a transmission service queue corresponding to the self; Storing the transmission message in a memory address corresponding to the value of the transmission input pointer; Increasing the value of the transmission input pointer when all the transmission messages have been stored; Reading and transmitting the transmission message using a value of a transmission input pointer recorded in the transmission service queue according to the transmission and reception enable clock signal assigned to the self; And increasing the value of the transmission output pointer when all the transmission messages have been transmitted.

Description

Apparatus and Method of Managing Messages in a System Bus

The present invention relates to an apparatus and method for processing a message on a system bus, and more particularly, to an apparatus and method for processing a message on a system bus in which a time division scheme is applied to the system bus so that buses having different transmission rates can be connected to the same bus structure. will be.

A conventional system bus configured in a time division scheme uses a time division scheme in transmitting a message, but is basically configured in a form that is too dependent on hardware timing.

1 is a view for explaining a message processing process of the time-division structure configured in the prior, the system is composed of a main control board (Main Control Board; 10) and a plurality of Local Board (20, 30), The main control board 10 includes an LMC (Local Message Controller) 11 and an MMC (Main Message Controller) 12, and the corresponding local boards 20 and 30 include LMCs 21 and 22, respectively. Here, each of the LMC (21, 31) is formed in a structure that processes the messages transmitted from each local board (20, 30) mounted in a maximum of 16 slots (mount) mounted in one self, respectively The LMCs 21 and 31 are connected to the corresponding MMCs 12 and are configured to transmit the corresponding messages to the main control board 10. At this time, the method used is designed based on the system based on the processor of 8 (ms) standard that is mainly used in the exchange used in the system.

Looking at the operation of the configuration as described above, each LMC (21, 31) is transmitted from the local board (20, 30) corresponding to its self for a time of 2 (ms) as shown in the timing diagram of FIG. The operation is performed by sending and receiving a message. Here, the corresponding '/ TREC' indicates a transmit / receive enable clock signal.

At this time, the LMC (21, 31) uses a distributed control method, a message that can be performed in the LMC (21, 31) itself is processed and transmitted to each local board (20, 30) and the main control board ( The information necessary for 10) is reprocessed and sent to the MMC 12.

The LMC 21 and 31 time-division allocates up to 16 slots to each of the local boards 20 and 30 during the 2 (ms) time allocated to the LMCs 21 and 31, and transmits a message in hardware during the 2 (ms) time. After processing, it operates by analyzing message for the remaining 6 (ms) time. At this time, all the operating programs should be operated by interrupt method of 8 (ms) cycle in order to execute in this way.

3 is a diagram illustrating allocating time in the form of time division to up to 16 slots connected to the LMCs 21 and 31. Here, 'Sx' represents a slot number. That is, the local boards 20 and 30 mounted in each slot operate the bus in the form of occupying the bus for message transmission only during the time of 'Sx' period.

However, in the above-described method, the LMC must be configured at every self in order to control the message bus when the system is expanded, and the MMC must always be used for message transmission with the LMC on the main control board side. This causes the system to be unable to use resources efficiently. In addition, the processor should always generate an interrupt periodically to process the message and process the message. The message buffer that can be stored in the LMC is always structured so that a new message can be input every 8 (ms). Even if there is no message sent, it has a disadvantage of reading and processing the message buffer.

In addition, when a service different from the existing local board is introduced into the system due to another problem, the above-described method may cause a problem in the message transmission rate. That is, the current time division method should provide a method for improving the speed, but there is a disadvantage that there is no method for changing the transmission rate of the message in the existing buffer form.

In order to solve the above problems and disadvantages, the present invention provides a system bus structure in which low-speed messages are transmitted to each other. SUMMARY OF THE INVENTION An object of the present invention is to provide an apparatus and method for processing a message in a system bus that enables efficient control of resources limited to message transmission between control blocks in a system having a message size.

It is also an object of the present invention to provide an apparatus and method for processing a message on a system bus suitable for a case where a large number of modules are connected to the bus and a large amount of messages are transmitted, but a large number of connected modules are frequently used.

Alternatively, the present invention provides a system bus that allows a bus having a different transmission rate to be connected to the same bus structure so that a board using an existing bus and a board providing a new service can be simultaneously configured as a single bus. In the present invention, there is provided an apparatus and a method for processing a message.

1 is a block diagram illustrating a message processing process of a time division structure previously configured.

FIG. 2 is a timing diagram of a transmit and receive enable clock signal of a local message controller (LMC) in FIG. 1; FIG.

FIG. 3 is a diagram illustrating allocating time in the form of time division to up to 16 slots connected to the LMC in FIG. 1; FIG.

4 is a block diagram illustrating a message processing apparatus in a system bus according to an embodiment of the present invention.

FIG. 5 is a diagram showing the configuration of a memory unit in FIG. 4; FIG.

FIG. 6 is a view for explaining a detailed function allocated during the time of 'Sx' in FIG.

Explanation of symbols on the main parts of the drawings

40: bus logic section 41: Up Interface

42: Control Registers

43: memory control block 44: message receiving control block

45: message transmission control block 46: transmission service queue

47: hardware timing block 50: memory section

60: buffer part

Message processing apparatus in the system bus of the present invention for achieving the above object is a buffer unit for transmitting and receiving messages with other boards; A memory unit having a reception buffer memory and a transmission buffer memory which are subdivided into a buffer unit composed of a maximum message size that can be transmitted, and storing the received message and the transmitted message, respectively; The input of the valid reception message is confirmed through the buffer unit, and the data is written to the memory unit according to the value of the reception input / output pointer, and the transmission message is written to the memory unit according to the value of the transmission input / output pointer, and then read and output to the buffer unit. Characterized in that it comprises a bus logic unit. Here, the pointer is used to designate a start address when the message is recorded, the reception input pointer indicates the number of valid received messages recorded, and the reception output pointer indicates the number of read received messages, and the transmission input pointer is The number of recorded transmission messages, wherein the transmission output pointer indicates the number of read transmission messages, wherein the bus logic unit comprises: an up interface for interfacing with a CPU; A control register having a reception state, a transmission state, a reception input / output pointer and a transmission input / output pointer, a reception buffer, and a transmission buffer to transmit and receive a message through the up interface; A message reception control block which checks input of valid cell data through the buffer unit and applies only input valid cell data; A hardware timing generation block for generating a transmit / receive enable clock signal assigned to each self; A transmission service queue that stores a transmission input pointer value of a memory address where a transmission message is recorded; A message transmission control block for applying a transmission message to the buffer unit using a value of a transmission input pointer stored in the transmission service queue according to the transmission / reception enable clock signal generated by the hardware timing generation block; And a memory control block for controlling memory operations of the control register, the transmission service queue and the memory unit according to the control of the message reception control block and the message transmission control block.

On the other hand, the message processing method in the system bus of the present invention for achieving the above object comprises the steps of storing the input valid cell data as a received message in a memory address corresponding to the value of the received input pointer; Increasing the value of the received input pointer when all of the received messages have been stored; Checking and reading a received message stored in a memory; Increasing a value of a reception output pointer when all of the received messages are read; Reading the destination address area of the message to be transmitted and analyzing which self is the message to be sent; Recording a value of a transmission input pointer in a transmission service queue corresponding to the self; Storing the transmission message in a memory address corresponding to the value of the transmission input pointer; Increasing the value of the transmission input pointer when all the transmission messages have been stored; Reading and transmitting the transmission message using a value of a transmission input pointer recorded in the transmission service queue according to the transmission and reception enable clock signal assigned to the self; And increasing the value of the transmission output pointer when all the transmission messages have been transmitted. The checking and reading of the received message stored in the memory may include periodically reading a value of a reception input pointer and a value of the reception output pointer; Comparing a value of the receive input pointer with a value of the receive output pointer; Generating an interrupt and requesting reading of the received message when there is a difference between the received input pointer value and the received output pointer value; And reading the received message stored in the memory according to the request, wherein the area used as the destination address in the header of the message is 4 bits and the remaining bits are transmitted in different units. It is used to distinguish the messages of the case.

Alternatively, the message processing method in the system bus of the present invention for achieving the above object comprises the steps of storing at the memory address corresponding to the value of the increased received input pointer upon input of new valid cell data; And storing a memory address corresponding to the value of the increased transmission input pointer when there is a new message to be transmitted.

Basically, the time division method used to control the local board having a low message transfer rate can be basically configured in a simple manner. The present invention improves the bus structure of the corresponding time division method and applies it to the system bus only when there are actually transmitted messages. Instead of having the processor read and process the message and periodically retrieve the message, it generates an interrupt only when the message is entered, allowing the message to be read from the internally configured buffer, allowing for efficient resource management.

In addition, the present invention uses a message processing routine that is dualized and processed by the LMC and MMC in a way that is processed in a single main control processor to reconfigure to take full advantage of the speed of the processor is accelerated, the configuration of the internal buffer memory Is formed using the Queue method. Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

As shown in FIG. 4, a message processing apparatus in a system bus according to an exemplary embodiment of the present invention includes a bus logic unit 40, a memory unit 50, and a buffer unit 60. Basically, the message is transmitted to the local board through the buffer unit 60 to perform the operation in the same structure as the conventional method, so that the resources of the conventionally configured system can be used as it is. This is done in a way that accommodates changes in transmission speed. That is, since the method of generating timing in hardware is configured in the same manner as the conventional method, the existing local board has the structure that can be used in the same way. The transmit / receive enable clock signals / TREC0 to / TREC2 have the same meaning as the transmit / receive enable clock signals / TREC3 shown in FIG. 2, but the present invention is a modification of the system of FIG. Three transmit and receive enable clock signals (/ TREC0 to / TREC2) are used.

The bus logic unit 40 checks the input of the valid reception message through the buffer unit 40, writes the data to the memory unit 50 according to the value of the reception input / output pointer, reads the value, and transmits the transmission message to the value of the transmission input / output pointer. The memory module 50 writes the data to the memory unit 50 and outputs the data to the buffer unit 40. The up interface 41, the control registers 42, and the memory control are controlled. A block 43, a message reception control block 44, a message transmission control block 45, a plurality of transmission service queues 46-1 to 46-3, and a hardware timing generation block 47 Is done. Here, the up interface 41 serves as an interface with the CPU. The control register 42 is provided with an area for storing a reception state, a transmission state, a reception input / output pointer, and a transmission input / output pointer, a reception buffer, and a transmission buffer, and according to the control of the memory control block 43, Messages are transmitted and received via the up interface 41. Then, the memory control block 43 is the control register 42, the transmission service queue 46 and the memory unit 50 in accordance with the input control of the message reception control block 44 and the message transmission control block 45. To control the operation of the memory, the cell data input from the message reception control block 44 is stored in the memory address of the memory unit 50 corresponding to the reception input pointer value of the control register 42 to complete the storage Increases the value of the corresponding reception input pointer by one, reads the corresponding reception message, writes it to the reception buffer of the control register 42, and increments the value of the corresponding reception output pointer by one upon completion of reading. Reads the destination address area of the transmission message recorded in the transmission buffer of the) and analyzes the message to be sent to which shelf. Records the value of the transmission input pointer in the bis queues 46-1 to 46-3, stores the transmission message in the memory address of the memory unit 50, and increases the corresponding transmission input pointer value by one upon completion of storage. The transmission message is read and applied to the message transmission control block 45 to increase the value of the transmission output pointer by one at the completion of reading. The message reception control block 44 checks the input of valid cell data through the buffer unit 60 and applies the input valid cell data to the memory control block 43. Then, the message transmission control block 45 enters the transmission service queues 46-1 to 46-3 according to the transmission / reception enable clock signals / TREC0 to / TREC2 generated by the hardware timing generation block 47. By using the value of the stored transmission input pointer, the memory control block 43 requests the transmission of the transmission message so that the transmission message is received and transmitted to the local board through the buffer unit 60. The transmission service queues 46-1 to 46-3 are associated with the message transmission control block 45, and store transmission transmission pointer values applied from the memory control block 43. The hardware timing generation block 47 generates the transmit / receive enable clock signals / TREC0 to / TREC2 assigned to each self.

As shown in FIG. 5, the memory unit 50 is largely divided into a reception buffer memory that is an area for storing a reception message and a transmission buffer memory that is an area for storing a transmission message. Here, each of the regions is subdivided into a buffer unit consisting of the maximum message size (e.g., 16 (Bytes)) that can be transmitted. That is, the corresponding receive buffer memory includes a plurality of receive buffers, and the corresponding transmit buffer memories It consists of two transmission buffers. The region designated by the receiving input / output pointer and the transmitting input / output pointer configured in the control register 42 provided in the bus logic section 40 takes a memory configuration in the form of designating the starting address of each buffer. Internally, 16 (Byte) messages are accessed.

The buffer unit 60 transmits and receives cell data with another local board.

6 is a view for explaining a detailed function allocated during the time of 'Sx' allocated to one slot configured in the shelf, it can be seen that the given time is made by allocating each time for message transmission and message reception. .

The operation of the message processing apparatus in the system bus according to the embodiment of the present invention configured as described above is as follows.

First, the reception I / O pointer and the transmission I / O pointer configured in the control register 42 provided in the bus logic section 40 are operated in a form in which hardware and software manage each corresponding register. Then, look at what each pointer means as follows.

Defined by the corresponding input pointer, it marks the message that has entered the buffer on both the sending and receiving side of the message. In other words, in the case of the reception input pointer, it indicates that there is a valid message actually received in the current block. In the case of the reception output pointer, the number of reception messages stored in the current memory buffer is indicated by the program. Similarly, when there is a message to be sent by the sender, it is stored first in the memory. The meaning of the transmission input pointer is the number of transmission messages written to the memory to transmit the message, The transmission output pointer is the number of messages.

The pointer is used to designate the start address of the buffer configured in the buffer that stores the message, and each buffer is designated as the maximum message size that can be transmitted.

Accordingly, when the message reception control block 44 provided in the bus logic unit 40 senses an input of valid cell data during the time of the reception section Rx shown in FIG. 5 through the buffer unit 60, The message receiving control block 44 applies the input valid cell data to the memory control block 43 provided in the bus logic unit 40.

The memory control block 43 receives valid cell data from the message reception control block 44 and is recorded in the current reception input pointer of the control register 42 provided in the bus logic unit 40. The value is read, and the valid cell data is stored as a received message in a memory address of the memory unit 50 corresponding to the read value of the received input pointer. In this case, it checks the case where all the received messages are stored, and increases the value of the corresponding received input pointer by one hardware to prepare for use in storing the next valid cell data. That is, when a new message is input, the new message is stored in the memory address corresponding to the increased value of the received input pointer.

Herein, the configuration of the memory unit 50 used to store the received or transmitted message is as shown in FIG. 5, which is stored in the memory unit 50 only when the valid cell data is input and the reception input is performed. The received message can be stored by increasing the value of the pointer by one.

Then, the method of actually reading the received message stored in the memory unit 50 by the program compares the values of the reception input pointer and the reception output pointer in hardware and generates an interrupt in the corresponding program when the difference is different. Since a new receive message is currently stored in memory, it is requested to read and process it, and that the program periodically reads the value of the receive input pointer and checks whether it is the same as the value of the receive output pointer. If the received message is not equal to the received output pointer value, the received message is present in the memory, and thus the received message is continuously read to process the received message. Here, the difference between the corresponding received input pointer value and the received output pointer value indicates the number of received messages currently stored in the memory.

At this time, when the program reads all of the received messages, the program increases the value of the receive output pointer by one to inform the hardware that the received message has been read.

Next, we will look at the case of sending a message to the other board.

If there is a message to be transmitted to another board, the transmission message is written in software to the transmission buffer FE0400 configured in the control register 42 through the up interface 41.

At this time, the memory control block 43 reads the first byte (i.e., the destination address area) of the transmission message recorded in the transmission buffer to determine which of the three shelves currently configured for the transmission message. Analyze In this case, the first byte of the transmission message usually configures a message type to designate a destination address, but is not limited thereto.

The memory control block 43 transmits a start service (ie, a value of a transmission input pointer) of the memory address in which the transmission message is recorded for the current transmission in the bus logic unit 40. Record in the queues 46-1 to 46-3.

At this time, the operation of the transmission input pointer is operated in the same manner as the reception input pointer as described above, and after the memory control block 43 has written all the transmission messages in the memory buffer of the memory unit 50, the transmission is performed. Increment the value of the input pointer so that the next new transmission message is stored in the next location in the currently stored memory buffer.

In the above, the transmission service queues 46-1 to 46-3 corresponding to each self are separately configured to use the same memory buffer configured for the current transmission, but the messages to be sent to each self are different. Therefore, only the transmission message corresponding to the self is transmitted.The value of the transmission input pointer stored in the corresponding transmission service queue 46-1 to 46-3 for the time allocated to each self (that is, / TREC0 to / TREC2). Use to process the message to be sent to the self.

Next, referring to a method of operating the transmission service queues 46-1 to 46-3, the operation of the transmission service queues 46-1 to 46-3 is hardware provided in the bus logic unit 40. The transmission / reception enable clock signal / TREC generated by the timing generation block 47 is correlated with each other.

That is, in the message transmission control block 45 provided in the bus logic unit 40 during the time of the first transmit / receive enable clock signal / TREC0 (in the conventional case, the time when the LMC of the first self operates). Request transmission of a transmission message to the memory control block 43 by using a value of a transmission input pointer stored in the first transmission service queue 46-1, and the memory control block 43 transmits a transmission currently stored in a memory. The message is read and applied to the corresponding message transmission control block 45 to be transmitted to the local board through the buffer unit 60.

Similarly, during the time of the second transmit / receive enable clock signal / TREC1 (in the conventional case, the time when the LMC of the second self operates), the value of the transmit input pointer stored in the second transmit service queue 46-2 is applied. If there is a corresponding transmission message to be processed, it is read and processed. In addition, during the time of the third transmit / receive enable clock signal / TREC2 (in the conventional case, the time when the third self LMC operates), the message transmission control block 45 performs the third transmission service queue 46-3. Perform the same operation with the value of the send input pointer stored in).

Accordingly, in all three cases, when the transmission of all transmission messages is completed, the value of the transmission output pointer is increased by one in hardware. In this case, the transmission output pointer is not particularly performed internally, but may be usefully used when measuring the total number of transmission messages by software.

By performing the operation as described above, when a large number of local boards are commonly connected to one bus and the amount of messages on the local boards is not very large, the time division method is applied and the memory unit is managed in the form of a queue buffer, so that all the time Since only a valid message is inputted without reading the message buffer corresponding to the slot, even if one control block is configured, the message can be processed more efficiently than the conventional LMC and MMC.

In addition, when the size of the memory buffer is expanded from the current 16 (Byte) to 64 (Byte) by performing the above-described operation, the local board transmitting the 16 (Byte) message processing local board and the 64 (Byte) unit Because it is possible to simultaneously accommodate the structure, even if a service that requires high-speed message transmission is applied, it can be easily configured. In addition, since message header is composed of 1 (Byte) and only 4 (Bit) is used in the area used as the actual destination address, the remaining 4 (Bit) is transmitted in units of 64 (Byte) and 16 (Byte). It can be easily distinguished by using to distinguish the message when transmitting in units.

As described above, according to the present invention, the actual program can process the message even in the base task state without processing in real time at the time of message transmission, thereby improving the overall program performance and dramatically expanding the system capacity accommodated in the same hardware configuration. It is possible to configure the system more efficiently by configuring the system bus more efficiently, especially since local boards with different transmission speeds are configured in the same system by using the same bus. Both boards and high-speed message transmissions can be accommodated.

Claims (6)

A buffer unit for transmitting and receiving messages with another board; A memory unit having a reception buffer memory and a transmission buffer memory which are subdivided into a buffer unit composed of a maximum message size that can be transmitted, and which store received messages and transmitted messages, respectively; The input of the valid reception message is confirmed through the buffer unit, and the data is written to the memory unit according to the value of the reception input / output pointer, and the transmission message is written to the memory unit according to the value of the transmission input / output pointer, and then read and output to the buffer unit. Message processing apparatus in the system bus, characterized in that comprises a bus logic unit. The method of claim 1, The pointer is used to designate a start address when the message is written, the reception input pointer indicates the number of valid received messages recorded and the reception output pointer indicates the number of read received messages and the transmission input pointer indicates the recorded transmission. And the transmission output pointer indicates the number of read transmission messages. The method of claim 1, An up interface for interfacing with the CPU; A control register having a reception state, a transmission state, a reception input / output pointer and a transmission input / output pointer, a reception buffer, and a transmission buffer to transmit and receive a message through the up interface; A message reception control block which checks input of valid cell data through the buffer unit and applies only input valid cell data; A hardware timing generation block for generating a transmit / receive enable clock signal assigned to each self; A transmission service queue that stores a transmission input pointer value of a memory address where a transmission message is recorded; A message transmission control block for applying a transmission message to the buffer unit using a value of a transmission input pointer stored in the transmission service queue according to the transmission / reception enable clock signal generated by the hardware timing generation block; And a memory control block for controlling memory operations of the control register, the transmission service queue, and the memory unit under control of the message reception control block and the message transmission control block. Storing the input valid cell data as a received message at a memory address corresponding to the value of the received input pointer; Increasing the value of the received input pointer when all of the received messages have been stored; Checking and reading a received message stored in a memory; Increasing a value of a reception output pointer when all of the received messages are read; Reading the destination address area of the message to be transmitted and analyzing which self is the message to be sent; Recording a value of a transmission input pointer in a transmission service queue corresponding to the self; Storing the transmission message in a memory address corresponding to the value of the transmission input pointer; Increasing the value of the transmission input pointer when all the transmission messages have been stored; Reading and transmitting the transmission message using a value of a transmission input pointer recorded in the transmission service queue according to the transmission and reception enable clock signal assigned to the self; And increasing a value of a transmission output pointer when all of the transmission messages have been transmitted. The method of claim 4, wherein Storing at a memory address corresponding to the increased value of the received input pointer when new valid cell data is input; And storing the memory address corresponding to the value of the increased transmission input pointer when there is a new message to be transmitted. The method of claim 4, wherein Identifying and reading a received message stored in the memory may include periodically reading a value of a reception input pointer and a value of a reception output pointer; Comparing a value of the receive input pointer with a value of the receive output pointer; Generating an interrupt and requesting reading of the received message when there is a difference between the received input pointer value and the received output pointer value; And reading the received message stored in the memory in response to the request.