KR100296638B1 - Teletext receiving data detection circuit and method thereof - Google Patents

Abstract

PURPOSE: A circuit and a method for detecting teletext receiving data are provided to detect TTX data by using a data slice circuit operating adaptively to input TTX data states and a phase synchronization loop circuit, thereby detecting original data without any distortion even for TTX signals mixed with interference or changed in the phase. CONSTITUTION: A circuit for detecting teletext receiving data includes a TTX data detection part(200) for producing a data slice level varying according to the change of input TTX data and detecting TTX data values with reference to the produced slice level, a phase compensation part(300) for obtaining and compensating a phase error of a data detected from the TTX data detection part, and a decoding part(100) for setting a TTX clock of a next line according to the obtained phase error.

Description

Text Multiple Broadcast Receiving Data Detection Circuit and Detection Method

The present invention relates to a circuit and a detection method for detecting received data of Teletext (hereinafter abbreviated as "TTX").

More specifically, even if a disturbance is applied to the received TTX data or the phase of the TTX signal is changed, the data slice circuit and the phase synchronization loop circuit which operate in accordance with the state of the received data are implemented to be independent of the disturbance or phase change. The present invention relates to a TTX reception data detection circuit and a detection method capable of cleanly detecting original TTX data.

Currently, TTX is one of the essential information service methods for daily life that can be obtained through television broadcasting in Europe or the United States.

The TTX converts image information consisting of characters and figures into digital signals and transmits them superimposed on a television video signal. The TTX adapter or TTX decoder (eg, news, business, weather forecast, stock, entertainment, shopping) Or a television receiver equipped with a " TTX adapter, etc. "

In order to achieve the above object, a circuit for detecting TTX data received on a television video signal is required, and current circuits use original TTX data for TTX signals received with disturbance or phase change. It is often detected distorted.

FIG. 1 is a waveform diagram illustrating a phenomenon in which original TTX data is detected distorted, and is a case where disturbance is mixed with a TTX signal.

As shown, waveform A is an ideally received TTX signal without disturbance mixing and contains information of the original TTX data. Waveform B, however, is a TTX signal received with disturbance mixed.

The slice level is a level used as a reference for dividing the amplitude of the input waveform transmitted from the receiving side into two levels in the transmission of digital data in the form of pulse waveform. In FIG. 1, the received TTX signal Is a signal level arbitrarily determined to divide the signal into a high level signal (1) and a low level signal (0) to convert it into original digital TTX data.

That is, if the amplitude of the received signal is greater than the slice level, 1 is detected at a predetermined detection time point (the rising edge of the clock pulse in FIG. 1), and 0 is detected if the amplitude of the received signal is small.

In this detection method, since the slice level is fixed at a predetermined level in the related art, when received with a disturbance such as waveform B, the original TTX data value is distorted to another value as in time points t1, t2, and t3. This allows characters or figures to appear broken on the screen of the television set.

Although FIG. 1 illustrates the received TTX signal with the disturbances mixed, the same phenomenon may occur even when the phase of the received signal is out of phase. There was a problem that it is not delivered correctly.

Accordingly, it is an object of the present invention to detect TTX data using a data slicing circuit and a phase-locked loop circuit adapted to the received data state so that even if the received TTX signal contains disturbance or is out of phase, It is an object of the present invention to provide a reception data detection circuit and a detection method for character multiplexing broadcast that can accurately detect TTX data.

1 is a waveform diagram illustrating a phenomenon in which original TTX data is detected distorted;

2 is a block diagram showing a TTX received data detection circuit of the present invention;

3 is a waveform diagram showing a TTX signal carried in a video signal;

4 is a waveform diagram illustrating a principle of obtaining first and second reference levels from the high level and low level trigger point parts of FIG.

5 is a waveform diagram illustrating high level interpolation performed by the high level interpolation unit of FIG. 2;

6 is a waveform diagram illustrating low level interpolation performed by the low level interpolation unit of FIG. 2;

7 is a block diagram illustrating an embodiment of a zero crossing unit of FIG. 2;

8 is a waveform diagram illustrating a variable slice level, first data, and a zero crossing point obtained in FIG. 7;

9 is a waveform diagram illustrating a principle of obtaining a first trigger point from the first trigger point detector of FIG. 2;

10 is a waveform diagram illustrating an example of obtaining a first trigger point according to FIG. 9;

11 is a waveform diagram illustrating a process of obtaining a phase error in the phase-locked loop of FIG. 2;

12 is a block diagram illustrating an embodiment of the phase locked loop of FIG. 2;

13 is a flowchart illustrating an embodiment of a TTX received data detection method of the present invention;

14 is a flowchart illustrating an embodiment of a variable slice level generation process of FIG. 13.

15 is a flowchart illustrating an embodiment of a process of detecting text multicast data value of FIG. 13;

FIG. 16 is a flowchart illustrating an embodiment of a first trigger point detection process of FIG. 13.

Explanation of symbols on the main parts of the drawings

100: decoding unit 200: TTX data detection unit

300: phase compensation unit

210: high level trigger point portion (HTPB) 220: high level interpolation portion (HAB)

230: low level trigger point portion (LTPB) 240: low level interpolation portion (LAB)

250: zero crossing portion (ZCB) 260: first delay portion

310: first trigger point detection unit (FTPB) 320: phase locked loop unit (PLL)

A feature of the TTX reception data detection circuit according to the present invention for achieving the above object is to generate a data slice level that varies according to the change of the input TTX data, and to detect the TTX data value based on the generated slice level. The detector includes a phase compensator for obtaining and compensating for a phase error of data detected by the TTX data detector, and a decoder for setting the TTX clock of the next line according to the phase error obtained from the phase compensator.

A characteristic of the TTX received data detection method according to the present invention is a TTX data input determination process for determining whether or not TTX data is input, and a slice level generated by generating a data slice level that is variable according to a change in the input TTX data. TTX data and zero crossing point detection process for detecting TTX data value and zero crossing point, and phase error of the data detected during TTX data and zero crossing point detection process are compensated for, and outputs the final detection clock. It consists of a TTX clock setting process of setting the TTX clock of the next line according to the synchronization process and the phase error obtained in the phase synchronization process.

Hereinafter, a preferred embodiment of the TTX reception data detection circuit and detection method according to the present invention will be described in detail with reference to FIGS. 2 to 16.

2 is a block diagram showing a TTX received data detection circuit of the present invention.

As shown, the TTX received data detection circuit of the present invention includes a TTX data detector 200, a phase compensator 300, and a decoder 100. The operation of each component is as follows.

The TTX data detector 200 generates a data slice level that varies according to a change in input TTX data (Data in), and detects a TTX data value based on the generated slice level.

The signal waveform of the TTX data carried on the video signal is shown in FIG. 3, and the present invention relates to a circuit and a method for more accurately detecting the TTX data carried on the horizontal sync signal and the color burst signal.

The phase compensator 300 obtains and compensates the phase error of the data detected by the TTX data detector 200, and the decoder 100 receives the phase error obtained by the phase compensator 300 for one line with an adder. After the addition, the TTX clock is added to the TTX clock of the next line and supplied to the phase compensator 300.

The decoding unit 100 also supplies a counter pulse for operating the circuit of the present invention to the above-described components, which is convenient to implement having the same frequency as the system clock.

Here, the TTX data detection unit 200 having the above-described operation again calculates the first reference level and outputs only the TTX input data larger than the calculated level (HTPB) 210 and the high level trigger point unit ( A low level trigger point portion (LTPB) 230 for calculating a second reference level smaller than the first reference level of the HTPB) 210 and outputting only TTX input data smaller than the calculated level, and a high level trigger point portion (HTPB) ( High level interpolation unit (HAB) 220 for interpolating the output data of 210 and low level interpolation unit (LAB) (LAB) for interpolating the output data of the low level trigger point unit (LTPB) 230. And delays the TTX input data input for the time processed by the high level and low level trigger point portion (HTPB) (LTPB) 210 and 230 and the high level and low level interpolation portion (HAB) (LAB) 220 and 240. First delay unit 260 for outputting According to the output data (HA interpolation signal) (LA interpolation signal) of the bell interpolation unit HAB (LAB) 220 and 240 and the output data DMdata of the first delay unit 260, And a zero crossing portion (ZCB) 250 for determining the first Ddata and the zero crossing point.

The phase compensator 300 detects the first trigger point detector (FTPB) 310 and the first trigger point detector (FTPB) 310 to detect the first trigger point of the input TTX data (Data in). The phase synchronization loop unit (PLL) 320 obtains and compensates a phase error of the TTX data (first Ddata) detected by the TTX data detector 200 based on the first trigger point.

The TTX received data detection circuit of the present invention having such a component detects TTX data in the following manner.

FIG. 13 is a flowchart illustrating an embodiment of a method for detecting TTX received data according to an embodiment of the present invention. The TTX data input determination process (S100), the TTX data and zero crossing point detection process (S200), the phase synchronization process (S300), and the TTX clock are shown in FIG. It consists of a setting process (S400), the execution order is as follows.

First, after determining whether TTX data is input in the TTX data input determination process (S100), and generating a data slice level that varies according to the change of the TTX data and the TTX data input in the zero crossing point detection process (S200). The TTX data value and the zero crossing point are detected based on the generated slice level.

In the phase synchronization process (S300), the phase error of the TTX data and the data detected in the zero crossing point detection process (S200) is calculated and compensated, and the final detection clock is output. In the TTX clock setting process (S400), the phase synchronization process (S300) is performed. Set the TTX clock for the next line according to the phase error found in.

The TTX reception data detection circuit and the detection method according to the present invention performed as described above will be described in more detail as follows.

First, the TTX data and zero crossing point detection process S200 is performed again by the variable slice level generation process S210, the TTX data value detection process S220, and the zero crossing point determination process performed by the TTX data detection unit 200 of FIG. 1. S230 and the final detection data output process S240 performed by the phase-locked loop unit 320 of FIG. 1.

Here, the variable slice level generation process (S210) generates a data slice level that varies according to the change of the input TTX data, which is illustrated in FIG. 14 and described with reference to FIGS. 4 to 7.

FIG. 14 is a flowchart illustrating an embodiment of a variable slice level generation process in the TTX received data detection method of FIG. 13, and FIG. 4 is a high level interpolator (HAB) 220 and a low level interpolator (LAB). In the TTX reception data detection circuit of the present invention shown in FIG. 2 as a preliminary operation for performing interpolation at the 240), the high level trigger point unit (HTPB) 210 and the low level trigger point unit (LTPB) 230 are used. It is a waveform diagram showing the principle of obtaining the first reference level Hth and the second reference level Lth.

First, in the first process S211 of FIG. 14, the first sample data Hssf having a predetermined level between the first initial level and the input data is determined at a time point of the input data larger than the first initial level, and the determined For the input data larger than the level of the first sample data Hssf, the level and position of another first sample data Hssf are determined in order as shown in Equation 1 below, Determine second sample data Lssf having a predetermined level between the second initial level and the input data at a time point of the input data smaller than this for any other second initial level, and determine the level of the determined second sample data Lssf. For smaller input data, the level and position of another second sample data Lssf are determined in order as shown in Equation 2 below.

[Equation 1]

Here, the N th first sample data level is a first sample data level for the N th input data nN among the TTX input data larger than the first initial level.

[Equation 2]

Here, the M th second sample data level is the second sample data level for the M th input data mM among the TTX input data smaller than the second initial level.

In a second process S212, a second reference level Hth between the first and second sample data Hssf and Lssf levels determined in the first process S211 and a second smaller than the first reference level Hth are included. The reference level Lth is calculated as in Equations 3 and 4 below at the same time point.

[Equation 3]

[Equation 4]

Here, the first process S211 and the second process S212 described above are performed by the high level trigger point unit HTPB 210 and the low level trigger point unit LTPB 230 of FIG. 2, respectively.

That is, the high level trigger point portion (HTPB) 210 and the low level trigger point portion (LTPB) 230 have a predetermined level between the first initial level and the input data at the point of time of the input data that is greater than any first initial level. Determine the first sample data Hssf, and determine in order the level and position of another first sample data Hssf for input data that is greater than the determined level of the first sample data Hssf, and the first initial Determine another sample data Lssf having a predetermined level between the second initial level and the input data at the time of the input data smaller than this for another second initial level determined to be smaller than the level, and determine the determined second sample data. For the input data smaller than the level of Lssf, the level and position of another second sample data Lssf are determined in order, and the determined first sample data Hssf and the second sample data Lssf are determined in order. ) Calculates another first reference level (Hth) and a second reference level (Lth) smaller than the first reference level (Hth) between levels so that input data larger than the first reference level (Hth) is transferred to the high level interpolator. The input data smaller than the second reference level Lth is output to the low level interpolator.

Meanwhile, in the third process S213 of FIG. 14 performed by the high level interpolation unit HAB 220 and the low level interpolation unit LAB 240 of FIG. 2, the first reference level calculated in the second process S212. High level interpolation is performed on input data larger than (Hth), and low level interpolation is performed on input data smaller than the second reference level (Lth), where the high level and low level interpolation may be interpolated according to the system clock.

5 and 6 illustrate the low level interpolation performed by the high level interpolation unit (HAB) 220 and the low level interpolation unit (LAB) 240 of the TTX received data detection circuit of the present invention shown in FIG. 2. The waveform diagram shown.

In the fourth process S214 of FIG. 14, the variable slice level is generated using the results of the high level and low level interpolation performed in the third process S213, which is calculated as in Equation 5 below.

[Equation 5]

Here, the high level interpolation level is a level resulting from high level interpolation, and the low level interpolation level is a level resulting from low level interpolation.

In the TTX data value detection process (S220) of FIG. 13, the TTX data value is detected by comparing the TTX data delayed by the time when the variable slice level generated in the variable slice level generation process (S210) is generated. One embodiment of is as shown in FIG.

That is, the TTX data value detection process S220 may be performed by comparing the size of the TTX data delayed by the time when the variable slice level and the variable slice level are generated, and the TTX data as a result of the determination of the first process S221. Outputting “1” when the size of the variable is greater than the variable slice level, and outputting “0” when the size of the TTX data is smaller than the variable slice level as a result of the determination of the first process (S221). It is performed in the order of three processes (S223).

In the zero crossing point determination process S230 of FIG. 13, the zero crossing point is determined from the data value detected in the TTX data value detection process S220.

The above-described fourth process S214 of FIG. 14, the TTX data value detection process S220 of FIG. 13, and the zero crossing point determination process S230 of FIG. 14 are performed in the zero crossing unit 250 of FIG. 2. 2 is a block diagram showing an embodiment of a zero crossing unit ZCB of the TTX received data detection circuit of the present invention shown in FIG.

That is, the zero crossing unit ZCB includes an adder 251 that adds output data (HA interpolation signal) (LA interpolation signal) of the high level interpolation unit HAB 220 and the low level interpolation unit LAB 240, and an adder. Comparing the output data DMdata and the variable slice level ASL of the divider 252 which generates the variable slice level ASL by arithmetically averaging the output data of 251, the TTX A first comparator 253 for determining a detection value (first Ddata) of data, and a zero crossing detector 254 for determining a zero crossing point whenever the output data value of the first comparator 253 changes.

Here, the first delay unit 260 may be configured as a flip-flop, a latch, or the like as a temporary memory device, and includes a high level and low level trigger point unit (HTPB) (LTPB) 210 and 230 and a high level and low level interpolator (HAB). Any memory device can be utilized as long as it can maintain the input TTX input data for a predetermined time in order to match the time and the time delay processed by the (LAB) 220 and 240.

FIG. 8 is a waveform diagram illustrating a variable slice level ASL obtained by the zero crossing unit ZCB shown in FIG. 7, detection values (first Ddata), and zero crossing points of TTX data.

The phase synchronization process S300 of FIG. 13 is performed by the phase compensator 300 of FIG. 2. The first trigger point detection process S310 for detecting the first trigger point of the input TTX data and the first trigger point detection are performed. A phase error determination step (S320) for determining a phase error of the TTX data and the data detected in the zero crossing point detection step (S200) based on the first trigger point detected at step S310, and a phase error determination step A phase compensation process (S330) for compensating by returning the phase error determined in (S320) and a final detection clock output process (S340) for outputting the final detection clock from the phase error compensated in the phase compensation process (S330).

Here, a flowchart illustrating an embodiment of the first trigger point detection process S310 is illustrated in FIG. 16.

FIG. 9 is a waveform diagram illustrating a principle of obtaining a first trigger point from a first trigger point detection unit (FTPB) of the TTX received data detection circuit of the present invention shown in FIG. 2.

As shown in FIG. 16, the first trigger point detection process S310 determines a reference pixel by comparing the TTX data input in the first process S311 with a predetermined level of an image signal, wherein the reference pixel is an image signal. It is determined as the first data of the TTX input data that is larger than a predetermined level larger than the front porch of and having a level higher than the data input before or after it.

In a second process S312, a first slice level is obtained from Equation 6 below from the reference pixel determined in the first process S311 and the front porch of the image signal.

[Equation 6]

In the third process S313, two pixels are determined by comparing the TTX data input before the reference pixel determined in the first process S311 with the first slice level obtained in the second process S312, wherein the two pixels are determined. Is determined as two pixels closest to the first slice level and smaller than the first slice level among the TTX data input before the reference pixel.

In the fourth process S314, the first detection clock is calculated by the following equation 7 according to the level and position of the two pixels determined in the third process S313 and the first slice level obtained in the second process S312. do.

[Equation 7]

Here, the constant is the number of sections divided when the pixel is divided into two sections.

In a fifth process (S315), the first trigger point, which is a reference for phase synchronization, is calculated according to Equation 8 according to the first detection clock calculated in the fourth process (S314), before the calculated first trigger point. The data is considered to be disturbance and ignored.

[Equation 8]

Here, the TTX clock is supplied from the decoding unit 100 of FIG. 2 as a reference clock of TTX data.

10 is a waveform diagram illustrating an example of obtaining a first trigger point by the first trigger point detector FTPB shown in FIG. 9.

According to FIG. 10, the reference pixel obtained in the first process S311 of FIG. 16 described above has a TTX input having a level greater than that of data input before or after the TTX data carried in the video signal to facilitate detection of the TTX data. Choose a pixel that is at least 32 pixels larger than the front porch level.

In general, when the magnitude of the overall amplitude of the video signal is divided into predetermined steps such that the front porch level is 72, the reference pixel is n5 (= 200).

The first slice level obtained in the second process S312 is 136, which is an average level of the reference pixel level and the front porch level according to Equation 6 described above.

The two pixels according to the third process S313 become n2 (= 120) and n3 (= 150). In the fourth process S314, the relationship of n3-n2: constant = first slice level: first detection clock The first detection clock is obtained at.

Finally, in the fifth process S315 of FIG. 16, the first trigger point may be obtained according to Equation 8 by using the first detection clock obtained as described above and the TTX clock input from the decoding unit 100 of FIG. 2. have.

FIG. 11 is a waveform diagram illustrating a process of obtaining a phase error in a phase locked loop (PLL) 320 among the TTX received data detection circuits of FIG. 2. In the phase error determination process S320 of FIG. The phase error to be determined is determined by the following equation (9).

[Equation 9]

Herein, N is an integer, TTX clock is a reference clock of TTX data, and Nth phase error is a phase error with respect to the Nth TTX clock.

In FIG. 11, first, phase error 1 is obtained by subtracting ref1 (first trigger point + TTX clock) and xpos1 (zero crossing point 1 + TTX clock / 2), and then phase error 1 is applied to ref2 (ref1 + TTX clock). Add it.

This compensates for the phase of the final detection clock (Dclock).

Subsequently, the effect of digital phase-locked loop (PLL) can be obtained in the same processing sequence as obtaining phase error 2 by subtracting ref2 and xpos2 (zero crossing point 2 + TTX clock / 2), where ref2 and xpos2 are ref1 and xpos1 are values generated as a result of feedback in FIG. 12 to be described later.

In FIG. 12, ref1 is an initial value of the D flip-flop 322, which is determined as (the first trigger point + TTX clock) by controlling the multiplexer 321 as an initialization value, and is determined by feedback from ref2.

FIG. 12 is a block diagram showing an embodiment of a phase locked loop (PLL) 320 in the TTX received data detecting circuit of the present invention shown in FIG. 2, which is described in detail from a zero crossing point, a first trigger point, and a TTX clock. A multiplexer 321, a D flip-flop 322, a divider 323 and a plurality of adders are included to calculate the phase error as shown in Equation (9). The divider 324 may be included.

As described above, after calculating the phase error, feedback is performed to perform phase compensation. The final detection clock Dclock is obtained by using the second comparator 325 from the compensated phase error Dclkcomp, and the zero crossing unit (see FIG. The TTX data value (first Ddata) obtained by the first comparator (253 of FIG. 7) of 250 is delayed by the second delay unit 326 by a time delayed for executing the above-described phase compensation. do.

Here, the final detection clock Dclock is generated and output in the final detection clock output process S340 of FIG. 13. When the position of the compensated phase error and the value of the counter are the same, one final detection clock Dclock is generated. .

The final output Ddata of the TTX data is performed in the final detection data output process S240 of FIG. 13.

As described above, the second delay unit 326, like the first delay unit 260 of FIG. 2, may be configured as a flip-flop or a latch as a temporary memory element, and the time and time required to perform phase compensation. Any memory device may be utilized as long as the input TTX data value (first Ddata) can be maintained for a predetermined time to match the delay.

As described above, according to the reception data detection circuit and the detection method of the character multi-broadcast according to the present invention, the character multi-broadcast data is detected by using a data slice circuit and a phase synchronization loop circuit operated according to the state of input TTX data. By doing so, it is possible to detect the original data without distortion, even for a signal of a character multi-broadcast signal received with disturbance or phase change.

Claims (37)

A TTX data detector configured to generate a data slice level that varies according to a change in the input TTX data, and detect a TTX data value based on the generated slice level; A phase compensator for obtaining and compensating for a phase error of data detected by the TTX data detector; And And a decoding unit for setting the TTX clock of the next line according to the phase error obtained by the phase compensator. The apparatus of claim 1, wherein the TTX data detector; A high level trigger point unit for calculating a first reference level and outputting only TTX input data larger than the calculated level; A low level trigger point unit for calculating a second reference level smaller than a first reference level of the high level trigger point unit and outputting only TTX input data smaller than the calculated level; A high level interpolation unit which interpolates the output data of the high level trigger point unit; A low level interpolation unit which interpolates the output data of the low level trigger point unit; A first delay unit delaying and outputting the TTX input data input for the time processed by the high level and low level trigger point unit and the high level and low level interpolation unit; And And a zero crossing section for determining a detection value of the TTX data and a zero crossing point according to the output data of the high level and low level interpolation section and the output data of the first delay section. The method of claim 2, wherein the high level trigger point unit and the low level trigger point unit; Determine first sample data having a predetermined level between the first initial level and the input data at a point in time of the input data that is greater than any first initial level, and for another input data that is greater than the determined level of the first sample data Determine the level and position of the first sample data in order, Determine another sample data having a predetermined level between the second initial level and the input data at a point in time of the input data smaller than that for another optional second initial level smaller than the first initial level, and determine the determined second sample data Determine, in order, the level and position of another second sample data for input data smaller than the level of Calculating another first reference level between the determined first sample data and the second sample data level and a second reference level smaller than the first reference level, And outputting input data larger than the first reference level to the high level interpolation unit, and outputting input data smaller than the second reference level to the low level interpolation unit. 4. The apparatus of claim 2 or 3, wherein the high level interpolation unit; And receiving the output data of the high level trigger point unit, interpolating and outputting the data according to a system clock. 4. The apparatus of claim 2 or 3, wherein the low level interpolation unit; And receiving the output data of the low level trigger point unit to interpolate and output the data according to a system clock. The method of claim 2, wherein the first delay unit; And a temporary memory device capable of maintaining an input TTX data value for a predetermined time. The method of claim 2, wherein the zero crossing portion; An adder for adding output data of the high level interpolation unit and the low level interpolation unit; A divider for generating a variable slice level by arithmetically averaging the output data of the adder; A first comparator comparing the output data of the first delay unit with a variable slice level to determine a detection value of TTX data; And And a zero crossing detection unit for determining a zero crossing point whenever the output data value of the first comparator changes. The apparatus of claim 1, wherein the phase compensator; A first trigger point detector for detecting an initial trigger point of input TTX data; And And a phase synchronous loop unit configured to obtain and compensate a phase error of the TTX data detected by the TTX data detector based on the first trigger point detected by the first trigger point detector. 9. The apparatus of claim 8, wherein the first trigger point detector; The reference pixel is obtained by comparing the input TTX data with a predetermined level of the video signal. A first slice level is obtained from the front porch of the reference pixel and the video signal. Two pixels are obtained by comparing the first slice level with the TTX data input before the reference pixel. And a first trigger point as a reference for phase synchronization from the obtained two pixel levels and positions and the first slice level. The method of claim 9, wherein the reference pixel; A character multi-broadcast reception data detection circuit, characterized in that it is determined as the first of TTX input data larger than a predetermined level larger than a front porch of a video signal and having a level higher than data input before or after. 10. The method of claim 9, wherein the first slice level comprises: Characterized multiple broadcast reception data detection circuit characterized by the following equation. [Equation] 10. The apparatus of claim 9, wherein the two pixels are selected from the group consisting of; And two pixels closest to a first slice level and smaller than the first slice level among the TTX data input before the reference pixel. The method of claim 9, wherein the first trigger point is selected from the group consisting of: After obtaining the first detection clock by the following equation 1 from the level and position of the two pixels and the first slice level, Character multiplex broadcast receiving data detection circuit characterized by the following equation (2). [Equation 1] Here, the constant is the number of sections divided when the pixel is divided into two sections. [Equation 2] Here, the TTX clock is a reference clock of TTX data. The method of claim 8, wherein the phase locked loop portion; After calculating the phase error from the zero crossing point, the first trigger point and the TTX clock, feedback is performed to perform phase compensation. Obtaining a final detection clock from the compensated phase error, And delaying the TTX data value obtained by the first comparator of the zero crossing unit by the second delay unit by a time delayed for executing phase compensation, and finally outputting the TTX data value. 15. The method of claim 14, wherein the phase error is; Characterized multiple broadcast reception data detection circuit characterized by the following equation. [Equation] Herein, N is an integer, TTX clock is a reference clock of TTX data, and Nth phase error is a phase error with respect to the Nth TTX clock. 15. The apparatus of claim 14, wherein the final detection clock is selected from the group consisting of: a; And a final detection clock is generated when the position of the compensated phase error is equal to the value of the counter. 15. The method of claim 14, wherein the second delay unit; And a temporary memory device capable of maintaining an input data value for a predetermined time. The apparatus of claim 1, wherein the decoding unit; And adding a phase error detected by the phase compensator for one line with an adder and adding the TTX clock to a reference clock of the next line. A TTX data input determination process for determining whether or not TTX data is input; TTX data and zero crossing point detection process of generating a data slice level that is variable according to the change of the input TTX data, and detecting the TTX data value and the zero crossing point based on the generated slice level; A phase synchronization process of calculating and compensating a phase error of the data detected in the TTX data and the zero crossing point detection process, and outputting a final detection clock; And And a TTX clock setting step of setting a TTX clock of a next line according to the phase error obtained in the phase synchronization process. 20. The method of claim 19, wherein detecting the TTX data and the zero crossing point; A variable slice level generation step of generating a data slice level that varies according to a change in input TTX data; A TTX data value detection step of detecting a TTX data value by comparing the variable slice level generated in the variable slice level generation process and the TTX data delayed by the time when the variable slice level is generated; A zero crossing point determination step of determining a zero crossing point from the data value detected in the TTX data value detection process; And And a final detection data output process of delaying and outputting the data value detected in the TTX data value detection process by a delay time while performing the phase synchronization process. 21. The method of claim 20, wherein the variable slice level generation step; Determine first sample data having a predetermined level between the first initial level and the input data at a point in time of the input data that is greater than any first initial level and perform another method for the input data that is greater than the determined level of the first sample data. Determine the level and position of one sample data in order, and having a predetermined level between the second initial level and the input data at the time of the input data smaller than this for another optional second initial level smaller than the first initial level. A first process of determining second sample data and sequentially determining a level and position of another second sample data for input data that is smaller than the determined level of second sample data; A second step of calculating a first reference level between the first and second sample data levels determined in the first step and a second reference level smaller than the first reference level; A third step of performing high level interpolation on input data larger than a first reference level calculated in the second step and performing low level interpolation on input data smaller than a second reference level; And And a fourth step of generating a variable slice level by using the result of the high level and low level interpolation performed in the third step. The method of claim 21, wherein the level of the first sample data of the first process; Character multiplex broadcast receiving data detection method characterized by the following equation. [Equation] Here, the N th first sample data level is a first sample data level for the N th input data among the TTX input data larger than the first initial level. The method of claim 21, wherein the level of the second sample data of the first process; Character multiplex broadcast receiving data detection method characterized by the following equation. [Equation] Here, the M th second sample data level is the second sample data level for the M th input data among the TTX input data smaller than the second initial level. The method of claim 21, wherein the first reference level of the second process; Character multiplex broadcast receiving data detection method characterized by the following equation. [Equation] The method of claim 21, wherein the second reference level of the second process; Character multiplex broadcast receiving data detection method characterized by the following equation. [Equation] 22. The method of claim 21, wherein the high level and low level interpolation of the third process comprises; Characterized multiplex reception data detection method characterized in that interpolation according to the system clock. 22. The method of claim 21, wherein the variable slice level of the fourth process comprises: Character multiplex broadcast receiving data detection method characterized by the following equation. [Equation] Here, the high level interpolation level is a level resulting from high level interpolation, and the low level interpolation level is a level resulting from low level interpolation. 21. The method of claim 20, wherein detecting the TTX data value comprises: A first step of comparing the size of the TTX data delayed by the time at which the variable slice level and the variable slice level are generated; A second step of outputting “1” when the size of the TTX data is larger than the variable slice level as a result of the determination of the first step; And And a third process of outputting “0” when the size of the TTX data is smaller than the variable slice level as a result of the determination of the first process. The method of claim 19, wherein the phase synchronization process; Detecting a first trigger point of the input TTX data; Determining a phase error of the TTX data and the data detected in the zero crossing point detection process based on the first trigger point detected in the first trigger point detection process; A phase compensation process for compensating by feedbacking the phase error determined in the phase error determination process; And And a final detection clock output step of outputting a final detection clock from the phase error compensated in the phase compensation process. 30. The method of claim 29, wherein the first trigger point detection process comprises: a; A first step of determining a reference pixel by comparing input TTX data with a predetermined level of an image signal; A second step of obtaining a first slice level from a front porch of the reference pixel and the image signal determined in the first step; A third step of determining two pixels by comparing the TTX data input before the reference pixel determined in the first step with the first slice level obtained in the second step; A fourth step of calculating a first detection clock according to the level and position of the two pixels determined in the third step and the first slice level obtained in the second step; And And a fifth process of calculating a first trigger point, which is a reference for phase synchronization, according to the first detection clock calculated in the fourth process. The method of claim 30, wherein the reference pixel of the first process; A character multicast reception data detection method, characterized in that it is determined as the first of TTX input data larger than a predetermined level larger than a front porch of a video signal and having a level higher than data input before or after. 31. The method of claim 30, wherein the first slice level of the second process comprises: Character multiplex broadcast receiving data detection method characterized by the following equation. [Equation] 31. The method of claim 30, wherein the two pixels of the third process are; And two pixels that are closest to a first slice level and smaller than a first slice level among the TTX data input before the reference pixel. The method of claim 30, wherein the first detection clock of the fourth process; Character multiplex broadcast receiving data detection method characterized by the following equation. [Equation] Here, the constant is the number of sections divided when the pixel is divided into two sections. 31. The method of claim 30, wherein the first trigger point of the fifth process comprises; Character multiplex broadcast receiving data detection method characterized by the following equation. [Equation] Here, the TTX clock is a reference clock of TTX data. The method of claim 29, wherein the phase error is; Characterized by the following equation according to the zero crossing point determined in the first trigger point and the zero crossing point detection method characterized in that the character multiplexing received data detection method. [Equation] Herein, N is an integer, TTX clock is a reference clock of TTX data, and Nth phase error is a phase error with respect to the Nth TTX clock. 30. The system of claim 29, wherein the final detection clock is selected from the group consisting of: a; And a single final detection clock is generated when the position of the compensated phase error is the same as the value of the counter.