JP3179144B2 - Digital arithmetic unit for television signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital arithmetic unit for television signals, and more particularly to an NTSC system and MUSE.
The present invention relates to a digital arithmetic unit for a television signal applied to high-speed digital processing of a television signal including a system.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional digital arithmetic unit for a television signal inputs a clock signal 12 synchronized with a data signal 11 to a delay circuit 2, and outputs a clock signal 16 delayed by the delay circuit 2. The operation output signal 13 is obtained by inputting the data signal 11 to the clock input 14 of the operation circuit 1 and the data signal 11 to the data input 15. The delay amount of the delay circuit is provided so that the transition point of the data signal does not coincide with the transition point of the clock signal.

[0003]

Generally, a digitized television signal has a different sampling frequency depending on the system. When the sampling frequency changes, the optimum delay amount of the delay circuit 2 in FIG. 2 changes. For this reason, it has been necessary to readjust the delay amount every time the arithmetic unit of FIG. 2 is used in a different manner from the conventional one.

Further, if the arithmetic unit shown in FIG. 2 is used for a television signal of a different system in a time-division manner, it becomes difficult to readjust the delay amount itself. In addition, a plurality of arithmetic units which differ only in the delay amount of the delay circuit 2 are required.

[0005] Another problem is that the operation is interrupted if the clock signal is abnormal.

[0006]

SUMMARY OF THE INVENTION A digital arithmetic unit for a television signal according to the present invention has a data signal input and a clock signal input for inputting a signal obtained by digitally encoding a television signal. In a digital signal processing device for a television signal which calculates in synchronization with the clock signal at a certain timing, a plurality of delay circuits connected to the clock signal; a frequency determination circuit connected to the clock signal; A first selector for selecting and outputting only one output of the plurality of delay circuits by a control output of a circuit, and an arithmetic circuit for performing an arithmetic operation by receiving an output signal of the first selector and the data signal; Automatically selecting the timing of the data signal and the clock signal according to the frequency of the clock signal; Characterized in that the can be computed corresponding to each of a plurality of different television signals.

Further, the present invention further comprises a clock generator, wherein when the frequency of the clock signal does not correspond to the sampling frequency of any type of television signal to be calculated, or when the clock signal cannot be detected, The output of the clock generator is selected by the first selector by the control output of the frequency discriminating circuit and input to the arithmetic circuit, or the second to select either the clock signal or the output of the oscillator. A selector for controlling the clock generation by the control output of the frequency discrimination circuit when the frequency of the clock signal does not correspond to the sampling frequency of any television signal to be calculated or when the clock signal cannot be detected; The calculation is not interrupted by selecting the output of the It is possible to provide a digital operation unit for television signals, characterized in.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing one embodiment of the present invention.
The clock signal 12 is input to the frequency determination circuit 4. The frequency discriminating circuit 4 monitors the frequency of the clock signal 12 and outputs the control signal 19 when the frequency is f1 to the control signal 19 when the frequency is f1, and to the control signal 19 when the frequency is f2. An abnormal state is output to the control output 20.

The clock signal 12 is supplied to delay circuits 2-3.
, And the delayed clock signals 17 to 18 as their outputs are input to the selector 5. Further, a clock generator 6 is connected to the selector 5. The selector 5 selects the clock signal 17 in the case of the A system, the clock signal 18 in the case of the B system, and the output of the clock generator 6 in the case of an abnormal clock state, based on the control signals 19 and 20 of the frequency discriminating circuit 4. , To the clock input 14 of the arithmetic circuit 1. The operation output signal 13 is obtained from the operation circuit 1 by inputting the data signal 11 to the data input 15.

FIG. 2 is a block diagram showing a second embodiment of the present invention. The frequency discriminating circuit 4 operates in the same manner as in FIG. 1 and obtains control signals 19 and 20. The clock signal 12 is input to the selector 7, and when the control signal 20 does not indicate the abnormal clock state, the selector 7 selects the clock signal 12, and when the control signal 20 indicates the abnormal clock state, the other of the selector 7 is selected. An output signal of the clock generator 6 connected to the input is selected and output. Next, the output of the selector 7 is input to the delay circuits 2 and 3, and the delayed clock signals 17 and 18, which are their outputs, are input to the selector 5. The selector 5 selects the clock signal 17 in the case of the A system and the clock signal 18 in the case of the B system according to the control signal 19 of the frequency discriminating circuit 4 and inputs the clock signal 18 to the clock input 14 of the arithmetic circuit 1. Data signal 11 is applied to data input 15
To the operation output signal 1 from the operation circuit 1.
I got 3.

[0011]

As described above, according to the present invention, since a function of automatically switching the delay amount of the clock signal according to the frequency of the clock signal is added, digital operation is performed on each of a plurality of different types of television signals. enable. Further, when the clock frequency is abnormal, the clock signal is switched to the output of the internal clock generator, so that the operation is not interrupted.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional digital operation device.

[Explanation of symbols]

 Reference Signs List 1 arithmetic circuit 2-3 delay circuit 4 frequency discriminating circuit 5, 7 selector 6 clock generator 11 data signal 12 clock signal 13 arithmetic output signal 14 clock input 15 data input 16-18 clock signal 19, 20 control signal

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuhiro Hashimoto 2-2-1 Jinnan, Shibuya-ku, Tokyo Japan Transport Association (72) Inventor Yoshio Tachioka 2-2-1 Jinnan, Shibuya-ku, Tokyo Japan Within the Japan Broadcasting Corporation (72) Inventor Makoto Ishii 2-2-1 Jinnan, Shibuya-ku, Tokyo Japan Broadcasting Corporation (56) References JP-A-59-23994 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H04N 5/00-5/217 H04N 7/24 H04N 9/00 H04N 9/44-9/78

Claims (3)

(57) [Claims] 1. A data signal input terminal for inputting a signal obtained by digitally encoding a television signal, and a clock signal input terminal. When a data signal and a clock signal have a certain timing, an operation is performed in synchronization with the clock signal. A plurality of delay circuits connected to the clock signal input terminal, a frequency discrimination circuit connected to the clock signal input terminal, and the plurality of delay circuits output by the frequency discrimination circuit. A digital signal processing device for a television signal, comprising: a first selector for selecting and outputting one output of a circuit; and a calculation circuit for receiving and calculating an output signal of the first selector and the data signal. 2. The digital signal processing device according to claim 1, further comprising a clock generator, wherein the frequency of the clock signal does not correspond to any of predetermined frequencies, or the clock signal cannot be detected. In this case, the digital selector for a television signal is characterized in that the output of the clock generator is selected by the first selector according to the control output of the frequency discriminating circuit and is input to the arithmetic circuit. 3. The digital arithmetic device for a television signal according to claim 1, wherein a second one of the clock signal and the output of the clock generator is selected by a control output of the clock generator and the frequency discriminating circuit. Selector, and when the frequency of the clock signal does not correspond to any of the predetermined sampling frequencies, or when the clock signal cannot be detected, the output of the clock generator is controlled by the control output of the frequency determination circuit. A digital signal processing device for a television signal, wherein the digital signal is selected by the second selector.