KR100294692B1 - Device isolation layer of semiconductor device and formation method thereof - Google Patents
Device isolation layer of semiconductor device and formation method thereof Download PDFInfo
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- KR100294692B1 KR100294692B1 KR1019980038740A KR19980038740A KR100294692B1 KR 100294692 B1 KR100294692 B1 KR 100294692B1 KR 1019980038740 A KR1019980038740 A KR 1019980038740A KR 19980038740 A KR19980038740 A KR 19980038740A KR 100294692 B1 KR100294692 B1 KR 100294692B1
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
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- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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Abstract
본 발명은 접합 누설 현상의 발생을 억제하여 리프레쉬 동작이 요구되는 메모리 소자의 동작 특성을 향상시키는데 적당하도록한 반도체 소자의 소자 격리층 및 그의 형성 방법에 관한 것으로 그 구조는 반도체 기판의 소자 격리 영역에 일부가 매립되고 하부로 갈수록 그 너비가 점차 넓어져 상단부의 너비보다 큰 너비로 하단부가 구성되는 소자 격리층과,소자 격리층의 상단부보다 수평 높이가 낮은 높이를 갖고 형성되는 활성 영역과,상기 활성 영역상에 형성되는 게이트 절연막과, 게이트 절연막상의 게이트 전극과,게이트 전극의 양측 활성 영역의 표면내에 형성되는 소오스/드레인(24)영역을 포함하여 구성된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation layer of a semiconductor device and a method of forming the same, which is suitable for suppressing the occurrence of a junction leakage phenomenon so as to improve operating characteristics of a memory device requiring a refresh operation. A part is buried and the width gradually increases toward the bottom, and the device isolation layer having a lower portion having a width greater than the width of the upper portion, an active region formed with a height lower than a horizontal height than the upper portion of the device isolation layer, and the active portion A gate insulating film formed on the region, a gate electrode on the gate insulating film, and a source / drain 24 region formed in the surfaces of both active regions of the gate electrode.
Description
본 발명은 반도체 소자의 소자 격리층에 관한 것으로, 특히 접합 누설 현상의 발생을 억제하여 리프레쉬 동작이 요구되는 메모리 소자의 동작 특성을 향상시키는데 적당하도록한 반도체 소자의 소자 격리층 및 그의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation layer of a semiconductor device, and more particularly to a device isolation layer of a semiconductor device and a method of forming the same, which are suitable for suppressing the occurrence of a junction leakage phenomenon and improving operating characteristics of a memory device requiring a refresh operation. will be.
일반적으로 셀과 셀들을 격리하기 위한 소자 격리 영역의 형성 공정은 반도체 소자의 미세화 기술에서 중요한 기술로 대두되어 그에 대한 연구가 활발하게 진행되고 있다.In general, a process of forming a device isolation region for isolating cells and cells has emerged as an important technology in the miniaturization technology of semiconductor devices, and research on them is being actively conducted.
대용량 메모리에서는 소자 격리 영역의 너비가 전체 메모리 소자의 크기를 결정하는 커다란 요인이 되고 있다.In large-capacity memories, the width of the device isolation region is a major factor in determining the size of the entire memory device.
현재, 소자 격리 영역 형성 기술로 많이 사용되고 있는 것이 선택 산화법(Local Oxidation of Silicon)이다.Currently, a selective oxidation method (Local Oxidation of Silicon) is widely used as a device isolation region forming technology.
상기의 선택 산화법은 그 공정상의 특징으로 하여 버즈빅이라는 현상이 발생하여 소자의 신뢰성을 저하시키기도 한다.The selective oxidation method described above is characterized in its process, and a phenomenon called buzz big occurs, which may lower the reliability of the device.
이와 같은 이유로하여 상기의 선택 산화법을 개량하는 연구가 진행되고 있다. 그 대표적인 것이 SWAMI(Side WAll Masked Isolation),SEPOX(Selective Polysilicon Oxidation)이다.For this reason, researches to improve the selective oxidation method have been conducted. Typical examples are Side WAll Masked Isolation (SWAMI) and Selective Polysilicon Oxidation (SEPOX).
그리고 또다른 방법으로 제시되고 있는 것이 기판에 홈을 형성하고 절연물을 매입하는 방법이며 대표적인 것이 STI(Shallow Trench Isolation)이다.Another method being proposed is to form grooves in the substrate and to insulate the substrate, and representatively, shallow trench isolation (STI).
이하, 첨부된 도면을 참고하여 종래 기술의 반도체 소자의 소자 격리층에 관하여 설명하면 다음과 같다.Hereinafter, a device isolation layer of a semiconductor device of the prior art will be described with reference to the accompanying drawings.
도 1은 종래 기술의 반도체 소자의 소자 격리층의 구조 단면도이다.1 is a structural cross-sectional view of a device isolation layer of a semiconductor device of the prior art.
도 1은 DRAM(Dynamic Random Access Memory)에서의 셀 트랜지스터의 형성 영역의 단면 구조를 나타낸 것이다.1 illustrates a cross-sectional structure of a region in which a cell transistor is formed in a dynamic random access memory (DRAM).
소자의 격리 특성을 높이기 위하여 다음과 같은 구조로 소자 격리층이 구성된다.In order to increase the isolation characteristics of the device, the device isolation layer is formed as follows.
먼저, 반도체 기판(1)의 소자 격리 영역에 매립 형성되는 STI층(2)과, 상기 STI층(2)에 의해 정의된 활성 영역에 형성되는 게이트 산화막(4),게이트 전극(5)과 상기 게이트 전극(5)의 양측 반도체 기판(1)의 표면내에 형성되는 소오스/드레인 영역(3)으로 셀 트랜지스터가 구성된다.First, an STI layer 2 embedded in an element isolation region of the semiconductor substrate 1, a gate oxide film 4, a gate electrode 5, and the gate oxide film formed in an active region defined by the STI layer 2. The cell transistor is composed of the source / drain regions 3 formed in the surface of the semiconductor substrate 1 on both sides of the gate electrode 5.
STI방식은 기판에 트렌치를 형성하고 절연 물질을 매립하여 소자 격리층을 형성하는 것으로, 초기에는 대부분 플라즈마 산화막 또는 APCVD(Atmospheric Pressure Chemical Vapour Deposition)에 의한 USG(Undoped Silicate Glass)막을 사용하여 트렌치를 매립하였다.In the STI method, a trench is formed in a substrate and an insulating material is buried to form an isolation layer. In the initial stage, the trench is buried using a USG (Undoped Silicate Glass) film by plasma oxide film or APCVD (Atmospheric Pressure Chemical Vapor Deposition). It was.
그러나 소자의 패턴 치수가 더욱 감소하면서 HDPCVD(High Density Plasma Chemical Vapour Deposition)산화막을 이용하여 트렌치를 매립하는 방법이 제시되고 있다.However, as the pattern dimension of the device is further reduced, a method of filling a trench using an HDPCVD (High Density Plasma Chemical Vapor Deposition) oxide film has been proposed.
이와 같은 종래 기술의 STI 소자 격리층은 반도체 기판(1)의 소자 격리 영역을 선택적으로 식각하여 트렌치를 형성하고 산화막을 채워 넣어야 하므로 그 구조가 하단부로 갈수록 좁아지는 형태로 구성된다.The STI device isolation layer of the related art has to form a trench by selectively etching the device isolation region of the semiconductor substrate 1 and fill the oxide layer, so that the structure becomes narrower toward the lower end.
즉, 트렌치 형성 공정에서 식각 프로파일이 수직하게 형성하는 것이 어려워 트렌치의 하단부로 갈수록 그 너비가 좁아진다.That is, in the trench forming process, it is difficult to form the etching profile vertically, and the width thereof becomes narrower toward the lower end of the trench.
이와 같이 트렌치의 구조가 하단부로 갈수록 좁아져 소자의 데이터 입출력 동작에서 다음과 같은 특성을 나타낸다.As described above, the trench structure becomes narrower toward the lower end thereof, thereby exhibiting the following characteristics in the data input / output operation of the device.
DRAM에서는 스토리지 노드가 콘택 플러그를 통하여 기판 불순물 영역(소오스/드레인)에 콘택되는데, 이와 같이 스토리지 노드가 콘택되는 것에 의해 스토리지 노드+유전체+플레이트 노드로 구성된 커패시터에 충전된 차지가 소모될 수 있다.In a DRAM, a storage node is contacted to a substrate impurity region (source / drain) through a contact plug. As such, the storage node contacts may consume a charge charged in a capacitor composed of a storage node, a dielectric, and a plate node.
이는 스토리지 노드 콘택 영역의 접합 면적에 따라 차지 소모 속도가 빠르게 나타난다.This speeds up charge consumption depending on the junction area of the storage node contact area.
이와 같은 차지 소모를 보충하기 위하여 주기적으로 커패시터에 재충전을 하게되는데 이를 리프레쉬 동작이라 한다.To compensate for this charge consumption, the capacitor is periodically recharged. This is called a refresh operation.
종래 기술에서와 같이 STI 소자 격리층이 하부로 갈수록 너비가 좁아지면 스토리지 노드의 접합 면적이 커져 스토리지 노드 접합 누설(Storage node Junction Leakage)이 커진다.As in the prior art, the narrower the width of the STI device isolation layer toward the bottom, the larger the junction area of the storage node is, the greater the storage node junction leakage.
이와 같은 종래 기술의 DRAM에서는 STI 소자 격리층의 구조가 하부로 갈수록 좁아져 스토리지 노드의 접합 면적이 커지므로 차지 소모가 빠르게 일어나 다음과 같은 문제가 있다.In such a conventional DRAM, since the structure of the STI device isolation layer becomes smaller toward the bottom, the junction area of the storage node becomes larger, so that charge consumption occurs quickly, resulting in the following problems.
즉, 빠른 속도로 소모된 차지를 재충전하기 위하여 리프레쉬 타임이 짧아진다.That is, the refresh time is shortened to recharge the consumed charge at a high speed.
그러므로 소자의 데이터 유지 측면, 메모리 소자의 운용 측면에서 불리하다.Therefore, it is disadvantageous in terms of data retention of the device and operation of the memory device.
본 발명은 이와 같은 종래 기술의 반도체 소자의 소자 격리층 및 그의 형성 공정의 문제를 해결하기 위하여 안출한 것으로, 접합 누설 현상의 발생을 억제하여 리프레쉬 동작이 요구되는 메모리 소자의 동작 특성을 향상시키는데 적당하도록한 반도체 소자의 소자 격리층 및 그의 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem of the device isolation layer of the prior art semiconductor device and its formation process, and is suitable for improving the operation characteristics of a memory device requiring a refresh operation by suppressing the occurrence of junction leakage. It is an object of the present invention to provide a device isolation layer of a semiconductor device and a method of forming the same.
도 1은 종래 기술의 반도체 소자의 소자 격리층의 구조 단면도1 is a structural cross-sectional view of a device isolation layer of a semiconductor device of the prior art
도 2는 본 발명에 따른 반도체 소자의 소자 격리층의 구조 단면도2 is a structural cross-sectional view of a device isolation layer of a semiconductor device according to the present invention.
도 3a내지 도 3d는 본 발명에 따른 소자 격리층의 공정 단면도3A-3D are cross sectional views of a device isolation layer in accordance with the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
21. 반도체 기판 22a. 산화막21. Semiconductor substrate 22a. Oxide film
22b. 소자 격리층 23a. 에피택셜층22b. Device isolation layer 23a. Epitaxial layer
23b. p-웰 영역 24. 소오스/드레인23b. p-well region 24. Source / drain
25. 게이트 절연막 26. 게이트 전극25. Gate insulating film 26. Gate electrode
접합 누설 현상의 발생을 억제하여 리프레쉬 동작이 요구되는 메모리 소자의 동작 특성을 향상시키는데 적당하도록한 본 발명의 반도체 소자의 소자 격리층은 반도체 기판의 소자 격리 영역에 일부가 매립되고 하부로 갈수록 그 너비가 점차 넓어져 상단부의 너비보다 큰 너비로 하단부가 구성되는 소자 격리층과,소자 격리층의 상단부보다 수평 높이가 낮은 높이를 갖고 형성되는 활성 영역과,상기 활성 영역상에 형성되는 게이트 절연막과,게이트 절연막상의 게이트 전극과,게이트 전극의 양측 활성 영역의 표면내에 형성되는 소오스/드레인(24)영역을 포함하여 구성되는 것을 특징으로 하고, 본 발명에 따른 반도체 소자의 소자 격리층 형성 방법은 반도체 기판상에 산화막층을 형성하는 공정;상기 산화막을 반도체 기판이 노출되도록 선택적으로 식각하여 하단부로 갈수록 점차 너비가 넓어지는 소자 격리층을 형성하는 공정;에피택셜 성장 공정으로 상기 노출된 반도체 기판 표면에 에피택셜층을 형성하는 공정;상기 에피택셜층에 불순물 이온 주입 공정을 하여 웰 영역을 형성하고 그 상측에 셀 트랜지스터를 형성하는 공정을 포함하여 이루어지는 것을 특징으로 한다.The device isolation layer of the semiconductor device of the present invention, which suppresses the occurrence of junction leakage and is suitable for improving the operating characteristics of a memory device requiring a refresh operation, is partially embedded in the device isolation region of the semiconductor substrate and has a width thereof downward. Is gradually wider than the width of the upper portion of the device isolation layer having a lower portion, the active region is formed having a height lower than the horizontal height than the upper end of the device isolation layer, the gate insulating film formed on the active region, And a source / drain 24 region formed in the surface of both active regions of the gate electrode and the gate electrode on the gate insulating film. The method of forming a device isolation layer of a semiconductor device according to the present invention comprises a semiconductor substrate. Forming an oxide film layer on the substrate; selectively converting the oxide film to expose a semiconductor substrate Forming a device isolation layer having a width gradually increasing toward the bottom thereof; forming an epitaxial layer on the exposed surface of the semiconductor substrate by an epitaxial growth process; implanting an impurity ion into the epitaxial layer to a well region And forming a cell transistor thereon.
이하,첨부된 도면을 참고하여 본 발명에 따른 반도체 소자의 소자 격리층 및 그의 형성 방법에 관하여 상세히 설명하면 다음과 같다.Hereinafter, a device isolation layer of a semiconductor device and a method of forming the same will be described in detail with reference to the accompanying drawings.
도 2는 본 발명에 따른 반도체 소자의 소자 격리층의 구조 단면도이다.2 is a structural cross-sectional view of the device isolation layer of the semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 소자 격리층은 하부로 갈수록 그 너비가 넓어지는 STI 구조로 형성한 것으로 그 상세 구조는 다음과 같다.The device isolation layer of the semiconductor device according to the present invention is formed in an STI structure in which the width thereof becomes wider toward the bottom thereof.
먼저, 반도체 기판(21)의 소자 격리 영역에 일부가 매립되고 하부로 갈수록 그 너비가 점차 넓어져 상단부의 너비보다 큰 너비로 하단부가 구성되는 소자 격리층(22b)과, 소자 격리층(22b)의 상단부보다 수평 높이가 낮은 높이를 갖고 형성되는 활성 영역과, 상기 활성 영역상에 형성되는 게이트 절연막(25)과, 게이트 절연막(25)상의 게이트 전극(26)과, 게이트 전극(26)의 양측 활성 영역의 표면내에 형성되는 소오스/드레인(24)영역을 포함하여 구성된다.First, the device isolation layer 22b and the device isolation layer 22b in which a portion is embedded in the device isolation region of the semiconductor substrate 21 and the width thereof gradually increases toward the lower portion, and the lower portion is formed with a width larger than the width of the upper portion. An active region formed with a height lower than an upper end of the active region, a gate insulating film 25 formed on the active region, a gate electrode 26 on the gate insulating film 25, and both sides of the gate electrode 26. And a source / drain 24 region formed within the surface of the active region.
이때, 게이트 전극(26) 하측 및 소오스/드레인(24) 영역의 일부 하측에는 소자 격리층(22b)이 형성되지 않는다.In this case, the device isolation layer 22b is not formed below the gate electrode 26 and partially below the source / drain 24 region.
즉, 소자 격리층(22b)의 너비가 하단부로 갈수록 계속 넓어지는 형태이나 서로 상응하는 소자 격리층(22b)이 완전히 맞닿지는 않는다.That is, the width of the device isolation layer 22b continues to widen toward the lower end, but the device isolation layers 22b corresponding to each other do not completely contact each other.
그리고 상기 셀 트랜지스터의 하측 N형 반도체 기판(21)에는 기판과 반대 도전형 즉,p-웰 영역(23b)이 형성된다.In the lower N-type semiconductor substrate 21 of the cell transistor, a conductive type opposite to the substrate, that is, a p-well region 23b is formed.
이와 같은 구조를 갖는 본 발명에 따른 반도체 소자의 소자 격리층의 형성 공정은 다음과 같다.The process of forming the device isolation layer of the semiconductor device according to the present invention having such a structure is as follows.
도 3a내지 도 3d는 본 발명에 따른 소자 격리층의 공정 단면도이다.3A-3D are cross-sectional views of a device isolation layer in accordance with the present invention.
본 발명의 반도체 소자의 소자 격리층 형성 공정은 DRAM 셀의 스토리지 노드의 접합 면적을 줄이기위하여 소자 격리층의 형성 너비를 하단부로 갈수록 넓힌 것으로 소자 격리층의 엣지 각도를 예각이 아닌 둔각으로 형성한 것이다.In the device isolation layer forming process of the semiconductor device of the present invention, in order to reduce the junction area of the storage node of the DRAM cell, the width of the device isolation layer is increased toward the lower end, and the edge angle of the device isolation layer is formed at an obtuse angle rather than an acute angle. .
먼저, 도 3a에서와 같이, N형의 반도체 기판(21)상에 충분히 두꺼운 두께로 산화막(22a)층을 형성한다.First, as shown in FIG. 3A, an oxide film 22a layer is formed on the N-type semiconductor substrate 21 with a sufficiently thick thickness.
이어, 도 3b 에서와 같이, 상기 산화막(22a)을 선택적으로 식각하여 상단부의 너비가 하단부의 너비보다 넓고 하부로 갈수록 점차 너비가 좁아지는 트렌치를 형성하여 소자 격리층(22b)를 형성한다.Next, as shown in FIG. 3B, the oxide layer 22a is selectively etched to form a trench in which the width of the upper portion is wider than the width of the lower portion and gradually narrows toward the lower portion to form the device isolation layer 22b.
그리고 도 3c에서와 같이, 에피택셜 성장 공정으로 상기 노출된 반도체 기판(21)표면에 에피택셜층(23a)을 형성한다.As shown in FIG. 3C, an epitaxial layer 23a is formed on the exposed surface of the semiconductor substrate 21 by an epitaxial growth process.
이때, 에피택셜층(23a)은 상기 소자 격리층(22b)의 상단부 수평 높이 보다 낮게 형성한다.At this time, the epitaxial layer 23a is formed to be lower than the horizontal height of the upper end of the device isolation layer 22b.
이는 셀 트랜지스터 형성시에 실리콘층과 소자 격리층(22b)과의 계면에서 게이트 산화막이 충분히 성장되지 않는 문제를 해결하기 위한것이다.This is to solve the problem that the gate oxide film is not sufficiently grown at the interface between the silicon layer and the device isolation layer 22b when forming the cell transistor.
이어, 도 3d에서와 같이, 상기 에피택셜층(23a)에 불순물 이온 주입 공정을 하여 p-웰 영역(23b)을 형성한다.Subsequently, as shown in FIG. 3D, an impurity ion implantation process is performed on the epitaxial layer 23a to form the p-well region 23b.
그리고 게이트 절연막(25),게이트 전극(26)을 형성하고 게이트 전극(26)의 양측 p-웰 영역(23b)에 불순물을 주입하여 소오스/드레인(24) 영역을 형성하여 셀 트랜지스터를 형성한다.The gate insulating layer 25 and the gate electrode 26 are formed, and impurities are injected into both p-well regions 23b of the gate electrode 26 to form a source / drain 24 region to form a cell transistor.
이와 같은 본 발명에 따른 반도체 소자의 소자 격리층 및 그의 형성 방법은 소자 격리층(22b)이 하단부로 갈수록 그 너비가 넓어져 스토리지 노드의 접합 면적을 줄이게 된다.In the device isolation layer and the method of forming the semiconductor device according to the present invention as described above, the width of the device isolation layer 22b toward the bottom thereof becomes wider to reduce the junction area of the storage node.
이와 같은 본 발명에 따른 반도체 소자의 소자 격리층 및 그의 형성 방법은 소자 격리층이 하단부로 갈수록 그 너비가 넓어져 스토리지 노드의 접합 면적을 줄이게 되어 다음과 같은 효과가 있다.The device isolation layer and the method of forming the semiconductor device according to the present invention as described above have the following effects as the device isolation layer becomes wider toward the lower end thereof, thereby reducing the junction area of the storage node.
첫째, 스토리지 노드가 콘택되는 접합 면적이 줄어들어 셀 커패시터에 충전된 차지가 방전되는 속도를 줄일 수 있다.First, the junction area at which the storage node contacts may be reduced, thereby reducing the rate at which the charge charged in the cell capacitor is discharged.
이는 소자의 리프레쉬 타임을 줄여 소자의 데이터 유지 및 입출력 동작의특성을 향상시키는 효과가 있다.This reduces the refresh time of the device, thereby improving the data retention and input / output characteristics of the device.
둘째, 스토리지 노드가 콘택되는 불순물 영역의 타측에 콘택되는 비트라인 접합 면적 역시 줄어들어 비트라인에 의한 기생 커패시턴스를 줄이는 효과가 있다.Second, the bit line junction area contacted to the other side of the impurity region to which the storage node contacts is also reduced, thereby reducing parasitic capacitance caused by the bit line.
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