KR100290661B1 - Method for testing call route in full electronic exchange - Google Patents

Abstract

The present invention provides a method for testing a call path of an electronic switch in which a processor tests an internal path of a time switch, a switch call path consisting of a time switch-space switch-time switch, and a path connected to devices connected to the time switch. According to the call path test method of an electronic switch according to the present invention, two channels of writing and reading test data for a test of a currency path to a time switch of the electronic switch are divided into odd and even channels. In this case, one test channel can test the internal path of the time switch and one channel can test the time switch-space switch-time switch path. There is an outstanding effect that the path test can be performed at the same time.

Description

Currency path test method of electronic exchanger {METHOD FOR TESTING CALL ROUTE IN FULL ELECTRONIC EXCHANGE}

The present invention provides a method for testing a call path of an electronic switch in which a processor tests an internal path of a time switch, a switch call path consisting of a time switch-space switch-time switch, and a path connected to devices connected to the time switch. It is about.

Conventionally, the processor inserts 64Kbps test data into one idle channel in a time switch multiplexer to test a switch call path composed of a time switch-space switch-time switch in an electronic switch, and the internal or time switch- of the time switch. The test path was established by finding the idle channel of the space switch-time switch, and then tested by calling the demultiplexer of the receiving time switch.

In addition, the time switch-space switch-time switch path test can be tested only by an operator's command. This is because only one test data could be produced by the time switch device.

However, since both the time switch internal path test and the time switch-space switch-time switch path test cannot be performed automatically, noise or silence occurs to the subscriber due to the path failure of the time switch-space switch-time switch. Even if there was a problem that can not be found before the operator's test or subscriber's report.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to provide a processor for automatically performing a time switch internal path test and a time switch-space switch-time switch path test at the same time. To provide a method for testing the currency path of

In order to achieve the above object, a method of testing an internal path of a time switch in a call path test method of an electronic switch according to an embodiment of the present invention includes a memory of a matrix memory time switching circuit pack, wherein the time switch and the link control processor are used. A first step of setting an idle channel (even channel) path to be tested in the unit; multiplexing and demultiplexing circuit packs and multiplexing of the matrix memory time switch circuit packs multiplex the test data; A second step of storing and then time slot-changing the data; and a demultiplexing unit of the multiplexing and demultiplexing circuit pack and the matrix memory time switching circuit pack to receive and convert the time slot-exchanged test data into serial test data. Step 3, the time switch matching section of the matrix memory time switching circuit pack Receiving a test data, the receiving test data selecting unit of the time switch matching unit receiving the serial test data and selecting one of the serial test data by an output signal of an 8-bit latch unit; 8-bit serial / parallel A fifth step of the converter latching the serial test data at 2048 변환 and converting the serial test data into parallel test data; and the parallel 8-bit receiving test data latch unit selecting a reception test data channel from the parallel test data from the 8-bit serial / parallel converter. A sixth step of latching and transmitting the test channel data to be read to the processor according to a negative control signal; and comparing the transmission / reception test data by the time switch and the link control processor to determine whether there is an abnormality in the internal time switch of the time switch. Characterized in that the seventh step of outputting the result to the terminal.

In order to achieve the above object, a method of testing a time switch-space switch-time switch path among the path test methods of an electronic switch according to an embodiment of the present invention may be performed after the space switch and the link control processor determine a test cycle. A first step of transmitting a test message including idle channel data in a space switch to a time switch and a link control processor; and the time switch and link control processor receiving a test message from the space switch and a link control processor to stop the subscriber. A second step of determining a channel (odd channel), writing test data to a first time switch and a link block, setting a path to an idle channel inside the space switch, and transmitting the path result to the space switch and the link control processor; The space switch and the link control processor Receives the routing result from the switch and link control processor and if the path setting is normal, controls the space switch and link block to set the path, and if the routing result is normal, the space switch is internal to the time switch and link control processor. A third step of transmitting a test message including idle channel data, and after the time switch and link control processor receives a test message from the space switch and link control processor to determine a subscriber idle channel (odd channel) A fourth step of setting a path by controlling the position and the link block and time slot exchange of the idle channel inside the space switch, reading test data, and transmitting the test data to the space switch and the link control processor 42; and the space switch and the link control. The processor is connected to the time switch and link Receive the routing result and test data from the processor, and if it is normal, compare the transmit / receive test data to determine whether the time switch-space switch-time switch path is normal, and then output the result to the terminal. Characterized in that made.

1 is a block diagram of a time switch-space switch-time switch system of an exchanger according to the present invention;

2 is a detailed block diagram of the time switch of FIG. 1;

3 is a block diagram of test data transmission / reception in the time switch matching unit of FIG. 2;

4 is an operation flowchart illustrating a time switch internal path test method of a call path test method of an electronic switching system according to an embodiment of the present invention;

5 is an operation flowchart illustrating a time switch-space switch-time switch path test method of a call path test method of an electronic switch according to an embodiment of the present invention;

FIG. 6 is a table illustrating a test path for redundancy of the time switch-space switch-time switch in the call path test method of the all-electronic exchange of FIG. 5;

<Explanation of symbols for main parts of the drawings>

10: first time switch and link block 11, 12: time switch

13, 14: Local link 20: Space switch and link block

21, 22, 23, 24: center link 25, 26: space switch

30: second time switch and link block 31, 32: local link

33, 34: time switch 41, 43: time switch and link control processor

42: space switch and link control processor

Hereinafter, with reference to the accompanying drawings for the currency path test method of the electronic switching system according to an embodiment of the present invention will be described in detail.

1 is a time switch-space switch-time switch system block diagram of an exchanger according to the present invention, wherein the first time switch and link block 10, the space switch and link block 20, and the second time switch and link block are shown. It consists of 30.

The first and second time switches and link blocks 10 and 30 are matched with a subscriber matching unit or a relay line matching device using subhighways (RS 422 DIFFERENTIAL LEVEL, serial 2 Mbps, 64 Kbps 32 channels), and 64 sub highways are connected to one channel. Multiplexed by highway (8-bit parallel 16.384Mbps), time switch (11, 12, 33, 34) to demultiplex into 64 sub-highway, and the space switch and link block 20 is connected to the optical link And regional links 13, 14, 31, and 32 for providing a communication path.

The space switch and the link block 20 may include space switches 25 and 26 for spatially switching subscriber data input from the first and second time switches and the link blocks 10 and 30 for each channel, and the local link 13. , 14, 31, 32 and a central link (21, 22, 23, 24) providing a communication path and a communication path.

Reference numerals 41 and 43 denote time switches and link control processors to control the time slot exchange operations of the first and second time switches and the link blocks 10 and 30, and the redundancy control and alarm state management function of the blocks. To play a role.

Reference numeral 42 serves as a space switch and a link control processor to control the space division exchange operation of the space switch and the link block 20, and to perform redundancy control and alarm state management functions of the block.

In addition, the first and second time switches and link blocks 10 and 30 and the space switch and link block 20 are configured with redundancy (A and B), and the regional links 13, 14, 31, 32 and The central link (21, 22, 23, 24) is a point-to-point redundancy, the time switch (11, 12, 33, 34), regional link (13, 14, 31, 32), space switch (25, 26) And central links 21, 22, 23 and 24 operate in active / standby mode.

FIG. 2 is a detailed block diagram of the time switch of FIG. 1, which is composed of multiplexing and demultiplexing circuit packs 50 and 60 and a matrix memory time switching circuit pack 70. As shown in FIG.

The multiplexing and demultiplexing circuit packs 50 and 60 receive up to 64 2048 channel data of sub-highway from a subscriber matching section or a trunk line matching device, and multiplex them into highway data (8-bit parallel 16.384 Mbps) to perform the matrix memory time switching circuit. While transmitting to the pack 70, it receives the highway data from the matrix memory time switching circuit pack 70 and demultiplexes the data into 64 subhighway data.

The matrix memory time switching circuit pack 70 transmits / receives the two multiplexing and demultiplexing circuit packs 50 and 60 and highway data, and transmits regional links 13, 14, 31, 32 and highway data. It receives / receives, matches with signal services and test devices into 32 subhighways, and plays a role of multiplexing and demultiplexing.

The matrix memory time switching circuit pack 70 includes a memory unit 72, a transmit / receive buffer unit 71, a local link matching unit 73, a multiplexer 74, a demultiplexer 75, and a time switch match. It consists of a part 76 and a subhighway matching part 77.

The memory unit 72 is composed of four buffer memories consisting of dual-port S-RAM, 4 × 4 call memories, four control memories, and a memory for PCM code conversion consisting of four PROMs. After storing the input highway data, the test device and the processor can read and write the data. More specifically, the two highway data received from the two multiplexing and demultiplexing circuit packs 50 and 60, One highway data received from the local link and one highway data received from the multiplexer 74 are continuously written to the communication memory after frame synchronization is performed by four buffer memories, and the time switch and link control processor 41, The channel data of the corresponding communication memory is read by the time slot exchange control data written by 43) into the four control memories. Slot exchange is made. The time slot exchanged data is transcoded by the PROM and transmitted to the local link, or the demultiplexer 53 or 63 of the multiplexing and demultiplexing circuit packs 50 and 60 or the matrix memory time switching circuit pack 70. Is transmitted by the demultiplexer 75 to the signal service and test apparatus.

The transmission / reception buffer unit 71 transmits / receives the multiplexing and demultiplexing circuit packs 50 and 60 and the highway data, and the regional link matching unit 73 transmits the regional link and the highway data. Receives role.

The subhighway matching unit 77 serves to match the signal service and the test apparatus with the subhighway, and the multiplexer 74 and the demultiplexer 75 are the subhighway matching unit 77 and the memory unit ( Multiplexing and demultiplexing the data between the 72 to the memory unit 72 and the signal service and the test device to serve to exchange data with each other.

The time switch matching unit 76 serves to match the memory unit 72 with the time switches and the link control processors 41 and 43, and more specifically, from the time switches and the link control processors 41 and 43. The received mode / address and data are serially / parallel converted and decoded, the switching data is written and read in the memory unit 72, and the failure state and redundancy control in the block are performed. Then, the system clock selection received from the regional link through the regional link matching unit 73 is controlled, divided into counters, and the write and read addresses of the memory are sent to the memory unit 72, and the test data control to write or read the test data. It creates a signal and performs serial / parallel conversion and parallel / serial conversion of test data written by the processor.

3 is a block diagram designed to read and write test data and to generate test data control signals by the time switch and link control processors 41 and 43 located in the time switch matching unit 76 of FIG.

When the time switch matching unit 76 receives the mode address and the test data from the processors 41 and 43 to designate the read and write channels, the time switch matching unit 76 decodes the mode addresses by serial / parallel conversion. The 8-bit address is latched by the 8-bit latch unit 100, and the 8-bit address is latched by the 8-bit latch unit 101 when the odd channel test data write operation is performed, and the 8-bit address when the channel test data read operation is performed. Is latched in the 8-bit latch section 102.

The counter unit 108 divides the 16.38 MHz clock received from the local link and the 2048 MHz clock divided by the frame pulse, and divides the signal into 1024 Hz, 512 Hz, 256 Hz, 128 Hz, 64 Hz, 32 Hz, 16 Hz and 8 Hz. Serves to create.

The 5-bit comparators 103, 104, and 105 are 5 bits that designate a channel in the 8-bit latch units 100, 101, and 102, and 128 kHz, 64 kHz, and 32 ㎑16 divided by the counter 108. By comparing the 8 and 8 clocks, a signal having a state of 1 and an otherwise 0 is generated and sent to the control signal decoder 106 and the pattern data reception test data channel selector 109.

The control signal decoder 106 decodes and outputs the upper three bits of the outputs of the 5-bit comparators 103 and 104 and the outputs of the 8-bit latch units 100 and 101 by a constant logic expression. The control signal latch unit 107 latches and outputs a 3-bit signal output from the control signal decoder unit 106 at 2048 kHz, which is a subhighway data rate.

The parallel 8-bit transmission test data latching units 113 and 114 latch the 8-bit pattern data to be written into the test paths by the processors 41 and 43. 113 is latched for the even channel and 114 is latched for the odd channel.

The 8-bit parallel / serial conversion sections 115 and 116 convert the output signals from the parallel 8-bit transmission test data latch sections 113 and 114 to 2048 kHz in parallel / serial conversion, respectively.

The test data channel selection transmitter 117 latches the information of the even and odd channels from the 8-bit latch units 100 and 101 at 2048 ms, the output signal of the control signal latch unit 107, and the 8 signal. It functions to logically output the output signals from the bit parallel / serial converters 115 and 116 by a predetermined equation.

The output signal from the test data channel select transmitter 117 is test pattern data.

With reference to the accompanying drawings, a method for testing the currency path of the electronic switch according to an embodiment of the present invention made in the electronic switch having the above configuration will be described.

Test methods can be broadly classified into the method of testing the time switch path and the method of testing the time switch-space switch-time switch path.

First, the method of testing the time switch path will be described.

4 is an operation flowchart for explaining the time switch internal path test method, where S means step (STEP).

First, when the time switch and link control processors 41 and 43 set the idle channel (eg, even channel) path to be tested in the memory unit 72 of the matrix memory time switching circuit pack 70 (S1), the test is performed. Data is multiplexed in the multiplexing unit 52, 62, 74 of the multiplexing and demultiplexing circuit packs 50, 60 and the matrix memory time switch circuit pack 70 (S2), so that the matrix memory time switching circuit pack 70 After being stored in the memory unit 72, timeslots are exchanged in the memory unit 72 (S3).

Subsequently, the timeslot-exchanged test data is input to the demultiplexers 53, 63, 75 of the multiplexing and demultiplexing circuit packs 50 and 60 and the matrix memory time switching circuit pack 70.

At this time, the demultiplexing unit 53, 63, 75 converts the time slot-exchanged test data into serial test data (S4), and the serial data is converted into a time switch matching unit of the matrix memory time switching circuit pack 70. 76) (S5).

Subsequently, the serial test data is input to the reception test data selection unit 110 of the time switch matching unit 76, where the reception test data selection unit 110 is applied to the output signal of the 8-bit latch unit 102. By selecting one of the serial test data (S6), the 8-bit serial / parallel conversion section 111 is latched to 2048 kHz and converted into parallel test data (S7).

Thereafter, the parallel 8-bit reception test data latching unit 112 reads the test channel according to the control signal of the reception test data channel selection unit 109 among the parallel test data from the 8-bit serial / parallel conversion unit 111. The data is latched and transmitted to the processors 41 and 43 (S8).

At this time, the processor 41, 43 compares the transmission / reception test data, determines whether there is an abnormality of the internal time switch, and outputs the result to the terminal (S9).

Next, a method of testing the time switch-space switch-time switch path will be described.

FIG. 5 is an operational flowchart for explaining a test method of a time switch-space switch-time switch path, where S denotes a step.

First, the space switch and the link control processor 42 determine the test period (S1 '), and then, transmit a test message including the idle channel data inside the space switch to the time switch and the link control processor 41 (S2'). .

Accordingly, the time switch and link control processor 41 receives the test message from the space switch and the link control processor 42 to determine the idle channel (eg, the odd channel) of the subscriber, and then the first time switch and the link block 10. The test data is written in the path 1), the path is set to the idle channel inside the space switch, and the path result is transmitted to the space switch and the link control processor 42 (S3 ').

Subsequently, the space switch and the link control processor 42 receive the routing result from the time switch and the link control processor 41 and output the result to the terminal if there is no response or the routing is abnormal, while the routing is normal. The rear side controls the space switch and the link block 20 to establish a path. At this time, if the path setting result of the space switch and the link block 20 is abnormal, the result is output to the terminal. If the path setting result is normal, the idle channel data in the space switch is transmitted to the time switch and the link control processor 43. Transmit the included test message (S4 ')

Accordingly, the time switch and link control processor 43 receives a test message from the space switch and link control processor 42 to determine the idle channel (odd channel) of the subscriber, and then selects the second time switch and link block 30. By controlling, the idle channel in the space switch is exchanged for time slots to establish a path, and the test data is read and transmitted to the space switch and the link control processor 42 (S5).

Subsequently, the space switch and the link control processor 42 receive the routing result and the test data from the time switch and the link control processor 43, and output FAULT information to the terminal if there is no response or the routing is abnormal, and if it is normal, Compare the received test data to determine whether the time switch-space switch-time switch path is normal, and output the result to the terminal (S6 ').

On the other hand, after the step (S6 ') to wait for a predetermined test period for the multi-path test after changing the test data and the time switch connected to the space switch (S7') proceeds to the step (S1 ').

In addition, after the step S7 ', the redundancy state of the time switch or the space switch is changed as shown in the table shown in FIG. 6 for the redundancy test (S8'), and the process proceeds to the step S1 '.

As described above, according to the call path test method of an electronic switch according to the present invention, two-channel writing and reading of test data for a test of a currency path on a time switch of the electronic switch is performed, that is, writing and reading are divided into odd and even channels. In this case, one test channel can test the internal path of the time switch and one channel can test the time switch-space switch-time switch path. There is an outstanding effect that the path test can be performed at the same time.

Claims (6)

In the method of testing the path inside the time switch of the path test method of the electronic exchanger, A first step in which the time switch and the link control processor set the idle channel (even channel) path to be tested in the memory unit 72 of the matrix memory time switching circuit pack; Multiplexing and demultiplexing circuit packs and multiplexing units (52, 62, 74) of the matrix memory time switch circuit pack multiplex test data, and the memory unit (72) stores the multiplexed test data and then exchanges time slots. The second step, A third step of the demultiplexing unit (53, 63, 75) of the multiplexing and demultiplexing circuit pack and the matrix memory time switching circuit pack receiving the time slot-exchanged test data and converting the test data into serial test data; When the time switch matching unit 76 of the matrix memory time switching circuit pack receives the serial test data, the reception test data selecting unit 110 of the time switch matching unit receives the serial test data to receive an 8-bit latch unit ( A fourth step of selecting one of the serial test data according to the output signal of 102; A fifth step of converting the serial test data into parallel test data by latching the serial test data at 2048 가 by the 8-bit serial / parallel converter 111; The parallel 8-bit reception test data latch unit 112 reads test channel data to be read according to the control signal of the reception test data channel selection unit 109 among the parallel test data from the 8-bit serial / parallel conversion unit 111. Latching and transmitting to the processors 41 and 43; The seventh step of the time switch and the link control processor compares the transmission and reception test data to determine whether there is an abnormality of the internal path of the time switch and outputs the result to the terminal. . In the method of testing the time switch-space switch-time switch path of the path test method of the electronic switch, A first step of, after the space switch and the link control processor 42 determine the test period, transmitting a test message including the idle channel data in the space switch to the time switch and the link control processor 41; The time switch and link control processor 41 receives a test message from the space switch and the link control processor 42 to determine the idle channel (odd channel) of the subscriber, and then tests the first time switch and the link block 10. A second step of writing data, setting a path to an idle channel inside the space switch, and transmitting the path result to the space switch and the link control processor 42; After the space switch and the link control processor 42 receive the path setting result from the time switch and the link control processor 41, and if the path setting is normal, the space switch and the link control processor control the space switch and the link block 20 to set the path. A third step of transmitting a test message including idle channel data in a space switch to the time switch and the link control processor 43 if the routing result is normal; The time switch and link control processor 43 receives the test message from the space switch and the link control processor 42 to determine the idle channel (odd channel) of the subscriber, and then controls the second time switch and the link block 30. Setting a path by time slot exchange of the idle channel in the space switch, reading test data, and transmitting the test data to the space switch and the link control processor 42; The space switch and the link control processor 42 receive the routing result and the test data from the time switch and the link control processor 43, and compare the transmission / reception test data with the time switch and the space switch-time switch. 5. The method of testing a call path of an electronic switching system, comprising a fifth step of determining whether the path is normal and outputting the result to the terminal. The method of claim 2, If the routing of the time switch or the space switch is abnormal in the third step, the space switch and the link control processor 42 output the result through the terminal. The method of claim 2, If the path setting of the time switch is abnormal in the fifth step, the space switch and the link control processor output FAULT information through the terminal. The method of claim 2, After the fifth step, after waiting for a predetermined test period for the multi-path test, after changing the test data and changing the time switch connected to the space switch, a sixth step proceeding to the first step is added. Currency path test method of electronic exchange. The method of claim 5, After the sixth step to change the duplication state of the time switch or the space switch for the redundancy test, the call path test method of the electronic switchboard, characterized in that the seventh step proceeds to the first step is added.