KR100299853B1 - Time switch/maintenance repair circuit pack in mobile telecommunica-tion exchange - Google Patents

Abstract

PURPOSE: A time switch/maintenance circuit pack in an MSC(Mobile Switching Center) is provided to execute a 32-subhighway multiplexing/demultiplexing function, a 2K time slot interchange function and a maintenance function by integrating a 1K multiplexing/demultiplexing circuit pack and a 1K time switch circuit pack into one. CONSTITUTION: A time switch module(100) receives 16.384Mbps 8-bit parallel data through a subhighway access and multiplexing/demultiplexing module(200) and input control latches(601,603) from a multiplexing/demultiplexing circuit pack and an optical access circuit pack. Also the time switch module(100) receives 2.048Mbps subhighway data through the subhighway access and multiplexing/demultiplexing module(200) and an input control latch(602) from a signal service system, an announcement system and a conference call system. If a maximum of 32-subhighway 2.048Mbps data are received, a multiplexer(201) multiplexes the received data into 16.384Mbps 8-bit parallel data and outputs them to the time switch module(100) through the input control latch(602). The 16.384Mbps 8-bit parallel data inputted from the multiplexer(201) are inputted to a 3x3 SM matrix circuit part through 3 buffer memories(BM0-BM2) and 9 voice memories(SM00-SM02,SM10-SM12,SM20-SM22). The 3x3 SM matrix circuit part is composed of 9 4Kx8-bit dual port RAMs.

Description

Time switch / maintenance repair circuit pack in mobile telecommunica-tion exchange}

The present invention provides an exchange of a mobile communication system (MOBILE TELECOMMUNICATION SYSTEM) that uses a CDMA (CODE DIVISION MULTIPLE ACCESS) method or a TDMA (TIME DIVISION MULTIPLE ACCESS) method. In particular, a single 1K multiplexing / demultiplexing circuit pack of a conventional all-electronic exchanger and a 1K time switching circuit pack of 1 sheet are designed to provide a single sub-highway (SUB-HIGHWAY). It has multiplexing and demultiplexing functions and 2K capacity time slot interchange (INTERCHANGE), and has a maintenance function.

As is well known, a mobile communication system is a communication system for a mobile device such as a person, a car, a ship, a train, an aircraft, and includes a mobile phone (mobile phone, a vehicle phone), a port phone, an aircraft phone, a mobile public phone ( Trains, cruise ships, express buses), radio calling, radiotelephony, satellite mobile communication, amateur radio, and fishing service ships.

Such mobile communication includes an AMPS (ADVANCED MOBILE PHONE SERVICE) system using an analog method, a CDMA system using a DIGITAL method, a TDMA system, and a FDMA (FREQUENCY DIVISION MULTIPLE ACCESS: frequency division multiple access) system.

As shown in FIG. 1, the CDMA system selectively or simultaneously supports the services of the AMPS system and the services of the CDMA system, thereby being a terminal device that enables a subscriber to communicate through a mobile communication network. (1); A base station (BASE TRANSCEIVER SUBSYSTEM) 2 for communicating with the terminal 1 using a protocol defined in IS-95 in a wireless section; A base station controller (3) which controls the radio link and the wired link and performs a handoff function for maintaining the continuity of the call even when the subscriber is moving; A switching station (MOBILE SWITCHING CENTER) 4 which constitutes a subscriber's call path and performs a connection with another communication network; Subscriber information is entered, consisting of a home location register (HOMEE LOCATION REGISTER) (5) and the like to exchange signals with the switching center (4), the terminal through the base station (2) and the control station (3) and the switching station (4) It is an apparatus which realizes the call of (1). Here, the home location register 5 is a system for storing subscriber information.

In addition, the switching center connecting the subscribers is composed of a CS (CONTROL SUB-SYSTEM), an IS (INTERCONNECTION SUBSYSTEM) and an SS (SWITCHING SUBSYSTEM).

Here, the CS is a subsystem (SUBSYSTEM) that performs the operation and maintenance of the switching center and the access (ACCESS), registration, cancellation and change processing of the mobile subscribers, and maintains, tests and measures, statistics, and disk control management at the system level. It performs various input / output statement control functions with the operator. In addition, CS performs an alarm panel, a video display terminal, a magnetic tape device, an optical disk device, and a disk device in order to perform the above functions. It has matching function with input / output device and operation maintenance center.

In other words, the mobile communication switchboard of the mobile switching center performs the operation and maintenance functions of the main processor (MAIN PRO-CESSOR), the peripheral processor (PERIPHERAL PROCESSOR), which controls the peripheral device through the control of the main processor, and the switch. It consists of an operation maintenance processor (OPERATION AND MAINTENANCE PROCESSOR) and the like, each processor performs a unique role assigned to realize the communication of the terminal (1).

That is, the caller terminal is connected to the mobile communication network (e.g., CDMA network, PSND (PUBLIC SWITCHED DATA NETWORK, etc.)) through the base station 2, the control station 3, and the switching station 4 to realize a connection with the called party terminal. Device.

On the other hand, the time switch circuit pack mounted and operated in the conventional all-electronic exchange has no subhighway matching function, multiplexing and demultiplexing functions, and can only perform a 1S capacity time slot interchange function.

Therefore, when a 1K × 1K time switch function is performed, a single 1K multiplexing and demultiplexing circuit pack performing a multiplexing and demultiplexing function and a subhighway matching function matches a subscriber device or a trunk line device, and a signal service device. And one other matching with a recording guide device or conference call device, and one time number position circuit pack performing a time slot interchange function.

Therefore, when the capacity of the system is increased due to the increase of subscribers, when designing the time switch capacity as 2K × 2K, four multiplex and demultiplex circuit packs (eight including redundancy) and two time switch circuit packs (four including redundancy) Each).

However, the conventional time switch circuit pack as described above has four multiplexing and demultiplexing circuit packs and two time switch circuitpacks when switching channel data of 2K capacity (multiplexing and demultiplexing circuit packs, considering the redundant structure). The use of multiple circuit packs such as 8 sheets and 4 timeswitch circuit packs) has made it difficult to maintain and operate the equipment, and has a large amount of space, which makes it uneconomical in terms of rack operation of the exchanger.

An object of the present invention is to solve the above-mentioned conventional problems, and in particular, by designing one 1K multiplexing / demultiplexing circuit pack and one 1K capacity time switch circuit pack into one, It is to provide "timeswitch / maintenance circuit pack of mobile communication exchange" that can perform highway multiplexing and demultiplexing function, 2K capacity time slot interchange function and maintenance function.

In order to achieve the above object, the present invention " time switch / maintenance circuit pack " of a mobile communication exchange includes a multiplexing and demultiplexing circuit pack, a signal service device or a recording guide device, and an optical matching circuit pack. A time switch module comprising a plurality of buffer memories, a control memory and a voice memory for time slot interchange of 8 Mbps parallel data; An FPGA module designed as a 304-pin FPGA to perform a test function using a TD-BUS matching function and its own call, output a sequential address , and perform fault collection and redundancy control; Receives the switch clock from the optical connection circuit pack, divides the subhighway clock from the received clock, and distributes it to the multiplexing / demultiplexing circuit pack, the signal service device, the recording guide device, and the conference call device, A clock control module for monitoring a clock; A subhighway matching and multiplexing / demultiplexing module for matching a signal service device, a recording guide device, a conference call device with 32 subhighways, and multiplexing or demultiplexing the matched 32 subhighways ; It includes a u / AA / u conversion module that converts the output data that performs the time slot exchange function of the 3 × 3 matrix structure into the u / A format or the A / u format in time slot units. It is characterized by the configuration.

In addition, the time switch module uses 9 4K × 8 bit DRAMs to form a 3 × 3 SM matrix, and uses three buffer memories in front of the 3 × 3 SM matrix in order to perform 2K time switching. By matching the operation frames (FRAME) of each of the nine voice memories, and dividing the voice memory into two areas, the data read process and the write process alternately occur once every 4 KHz. It is characterized by guaranteeing (DELAY).

The time switch module may use a clock of 16.384 MHz as a switching clock for performing a time slot interchange function in a 3 × 3 SM matrix circuit.

In addition, the FPGA module decodes the serial data and the address data of the four-line parallel type received from the time switch processor to read its own memory and TD-BUS cable test READ AFTER WRITE function, and checks the state of the memory. The control memory read function and the control memory write function to write the switching related information into the memory, collect the status of each circuit pack, perform the redundancy control, and test the own channel. The TD-BUS matching circuit section enables the circuit pack to send the ready signal and the output data by selectively performing the test function through its own currency and selecting the circuit pack of the 16-bit address data and the subhighway and the channel number. ; A sequential address output circuit section for outputting a 3x3 SM matrix, a sequential address of a buffer memory and a control memory, and providing a 4.096 MHz subhighway clock and an 8KHz synchronous clock to a subhighway matching and multiplexing / demultiplexing module; A fault collection and redundancy control circuit unit which collects a signal of each circuit pack and a fault signal of a power pack in the time switch device and outputs the fault information collected on request of the time switch processor; It is characterized in that it comprises a test circuit section of its own call to test the own call path of the time switch device under the control of the time switch processor.

In addition, the subhighway matching and multiplexing / demultiplexing module, the signal service device, the recording guide device and the conference call device to match the 32 sub-highway, by multiplexing or demultiplexing the matched 32 sub-highway, multiplexing / demultiplexing circuit And to perform a pack function and a time slot interchange function.

1 is a block diagram schematically showing a configuration of a mobile communication system;

2 is a circuit block diagram showing the configuration of a "time switch / maintenance circuit pack of a mobile communication exchange" of the present invention;

3 is a circuit block diagram showing the configuration of the FPGA module of the present invention "time switch / maintenance circuit pack of the mobile communication exchange".

<Explanation of symbols for important parts of the drawing>

100: time switch module

200: subhighway matching and multiplexing / demultiplexing module

300: FPGA module 400: clock control module

500: u / A-A / u conversion module

Hereinafter, with reference to the accompanying drawings, the configuration, operation and operation effects for an embodiment according to the technical idea of the present invention "time switch / maintenance circuit pack of the mobile communication switch" configured as described above are as follows.

<Example>

In this embodiment, a 3K3 SM matrix voice memory, a control memory, and an FPGA were designed to design a 2K time slot interchange function, and Z- can accommodate up to 525 pins in the size of a conventional electronic switch circuit pack. Using the PACK connector, it is possible to perform the matching function of 32 sub highways. In addition, it enables multiplexing and demultiplexing of 2K channel data.

In addition, the performance of the time slot interchange function, which is the original function of the time switch circuit pack of the conventional electronic switchboard, is increased to 2K capacity, which is twice the capacity, and the 1K capacity subhighway matching function of the multiplexing and demultiplexing circuit pack in addition to the 2K time slot interchange function is also provided. Accommodate functionality and multiplexing and demultiplexing capabilities reduce the number of timeswitches and maintenance circuit packs when designing 2K × 2K capacitive time switch units, as well as matching signal service units with announcements and conference call units It was configured to perform the function.

Hereinafter, the configuration, operation and effects of the present embodiment will be described in detail with reference to FIGS. 2 and 3.

Figure 2 is a block diagram showing one configuration according to the technical idea of the "time switch / maintenance circuit pack of the mobile communication exchange" of the present invention.

In FIG. 2, the time switch module 100 sub-highway matching and multiplexing / demultiplexing module 200 and an input tube latch for 16.384 Mbps of 8-bit parallel data input from the multiplexing / demultiplexing circuit pack and the optical matching circuit pack. Receives through the sub-highway matching and multiplexing / demultiplexing module 200 and the input enema latch 602 from the signal service device, the recording guide device and the conference call device (601, 603). .

In addition, receiving up to 32 sub-highway 2.048 Mbps data from signaling service units, recording announcements, and conference call devices allows for formats such as 16.384 Mbps of 8-bit parallel data from multiplexing / demultiplexing circuit packs and optical matching circuit packs. The multiplexer 201 multiplexes the 8 bit parallel data of 16.384 Mbps and outputs it to the time switch module 100 through the input enema latch 602.

Three buffer memories BM0, for time slot interchange of multiplex / demultiplex circuit packs, local data link circuit packs, and 16.384 Mbps 8-bit T parallel data input from the multiplexer 201 of the circuit pack according to the present invention. The BM1 and BM2 are input to a 3x3 SM matrix circuit section consisting of nine voice memories SM01, SM02, SM10, SM11, SM12, SM20, SM21 and SM22.

The 3x3 SM matrix circuit section consists of nine 4Kx8-bit dual port RAMs. Three buffer memories are used at the front of each 3x3 SM matrix to match the operation frame of each voice memory. By dividing the memory into two areas, the data storage and reading process takes place alternately at 4KHz intervals, ensuring the same switching delay.

Therefore, the three buffer memories BM0, BM1 and BM2 use the same 2048 timeslot sequential write address.

The 3x3 SM matrix performs time slot interchange functions under the control of three control memories (CM0, CM1, CM2) to perform time slot exchange, and each data is output-controlled latches (611, 612, 613) and u / AA / Through the conversion module 500, 8-bit parallel data of 16.384 Mbps is transmitted to the multiplexer / demultiplexer circuit pack, the local data link circuit pack, or the demultiplexer 203 of the circuit pack according to the present invention.

The demultiplexer 203 transmits the received 16.384 Mbps of 8-bit parallel data to the signal service device, the recording guide device, and the conference call device through the demultiplexer subhighway matching and multiplexing / demultiplexing module 200.

The FPGA module 300, which is designed as a 304-pin FPGA in FIG. 2, includes a TD-BUS matching circuit section 301, a sequential address output circuit section 302, a fault collection and redundancy control circuit section 303, and a test circuit section 304 of its own communication path. 2 shows a block diagram of the FPGA module 300.

In Fig. 3, the TD-BUS matching circuit section 301 decodes the four-line parallel mode mode and address data received from the time switch processor to read and write the read after write function, which is a test of its own memory and TD-BUS cable, and the state of the memory. Control memory read function for inspection, control memory write function to write switching related information into memory, and maintenance own currency test to collect the status of each circuit pack, perform redundancy control and test its own channel Four modes are available to perform the function, and 16BIT of address data allows circuit pack selection and subhighway and channel number selection, allowing the circuit pack to send ready signals and output data.

In addition, the sequential address output circuit unit 302 outputs a sequential address of a 3x3 SM matrix, a buffer memory, and a control memory, and outputs a signal service device, a recording guide device, a conference call device, a multiplexing / demultiplexing circuit pack, and the like. The subhighway matching and multiplexing / demultiplexing module 200 accommodates a 4.096MHz subhighway clock and an 8KHz synchronous clock.

In addition, the fault collection and redundancy control circuit unit 303 collects fault signals of each circuit pack and power pack in the time switch device and provides fault information collected through the TD-BUS matching circuit unit 301 upon request of the time switch processor. do.

In addition, the own circuit path test circuit 304 may test its own channel of the time switch device under the control of the time switch processor, and the paths to these channels can be freely connected by a 3 × 3 matrix structure.

The test data generated in the circuit pack according to the present invention can be assigned an arbitrary channel of the multiplexing / demultiplexing circuit pack or the multiplexer 201 input subhighway 63 inside the circuit pack according to the present invention and is arbitrarily tested by a time switch processor. You can set the data value.

Meanwhile, in FIG. 2, the subhighway matching and multiplexing / demultiplexing module 200 receives up to 32 subhighways input from a signal service device, a recording guide device, and a conference call device, and receives an input enema latch 602 through a multiplexing circuit. The time slot interchange is performed in the time switch module 100 through the SB.

In addition, randomly extracted 16.384 Mbps of data is latched by the output enema latch 612, and the latched 16.384 Mbps of parallel 8-bit data is passed through the u / AA / u conversion module 500 to subhighway matching and multiplexing / reversing. It is transmitted to the multiplexing module 200.

De-multiplexer 203 of subhighway matching and multiplexing / demultiplexing module 200 converts the signal into serial 8-bit data of 2.048 Mbps and outputs the signal service device and recording guidance through the DIFFEREN-TIAL LINE output circuit. Are sent to the device and conference call device.

In addition, the clock control module 400 receives a 16.384 MHz switching clock and an 8 KHz synchronous clock and a redundant signal from an optical connection circuit pack, selects and uses a switching clock and a synchronous clock according to the redundant signal, divides the switching clock, and divides the 8 KHz. A clock reception and distribution circuit unit 401 and a subhighway matching function of generating a 4.096 MHz subhighway clock and an 8KHz subhighway synchronous clock using the synchronous clock to distribute the subhighway matching and multiplexing / demultiplexing module 200. And a latch clock used in the multiplexer / demultiplexer module 200, a latch clock used in the demultiplexer 202, a TD-BUS clock received from a time switch processor, and a power alarm output from a power pack. Thus, the clock monitoring circuits 402 and 403 allow redundant switching in the event of a failure.

In addition, the u / AA / u conversion module 500 performs u / A format or A / u format conversion on a time slot basis with respect to the output data on which the time switch module 100 performs time slot interchange. .

Therefore, the multiplexing and demultiplexing functions of the 32 subhighways, the time slot interchange function and the maintenance function of 2K capacity can be performed.

As described above, the "time switch / maintenance circuit pack of the mobile communication exchange" of the present invention, in particular, performs a multiplexing and demultiplexing function of 32 subhighways and a time slot interchange function of 2K capacity and has a maintenance function. Designing a circuit pack eliminates the need for a separate multiplexing and demultiplexing circuit pack that performs matching between the signal service device, the recording guidance device, and the conference call device. Since the slot interchange function can be performed, the number of circuit packs used in the 2K capacity time switch device of the conventional all-electronic exchanger is reduced to 1/2, and the maintenance and management can be easily performed.

Claims (5)

It consists of multiplexing and demultiplexing circuit packs, a signal service device or a recording guide device, and a plurality of buffer memories, control memory and voice memory for time slot interchange of 16.384Mbps 8-bit parallel data applied from the optical matching circuit pack. A time switch module; Pin 304 is designed as a FPGA FPGA module to the TD-BUS Interface Function and performs the testing function to call itself, and outputting a sequential address, control and fault collection and redundancy; Receives the switch clock from the optical access circuit pack, divides the subhighway clock from the received clock, and distributes it to the multiplexing / demultiplexing circuit pack, the signal service device, the recording guide device and the conference call device, and the various clocks in the circuit pack. A clock control module for monitoring the; A sub-highway matching and multiplexing / demultiplexing module for matching the signal service apparatus, the recording guide apparatus, the conference call apparatus into 32 subhighways, and multiplexing or demultiplexing the matched 32 subhighways; A mobile communication comprising a u / AA / u conversion module for converting output data that performs a time slot exchange function having a 3 × 3 matrix structure into a u / A format or an A / u format on a time slot basis. Time switch / maintenance circuit pack for the exchange. The time switch module according to claim 1, wherein the time switch module uses nine 4K × 8-bit DRAMs to perform time switching of 2K capacity, and forms a 3 × 3 SM matrix, and three buffers in front of the 3 × 3SM matrix. The memory is matched with the operation frames of each of the nine voice memories, and the voice memory is divided into two regions, and the data read and write processes alternately occur once at 4 KHz intervals, thereby ensuring the same switching delay. Time switch / maintenance circuit pack for mobile switching center. The time switch / maintenance circuit of a mobile communication exchange according to claim 1, wherein the time switch module uses a clock of 16.384 MHz as a switching clock for performing a time slot interchange function in a 3x3 SM matrix circuit unit. pack. 4. The FPGA module of claim 1, wherein the FPGA module decodes the serial data and the address data of the 4-wire parallel type received from the time switch processor to perform a read after write function which is a test of its own memory and TD-BUS cable, and a state check of the memory. The control memory read function to write the control memory read function and switching related information to the memory, and to collect the status of each circuit pack, to perform the redundant control and to test the own channel A TD-BUS matching circuit unit for enabling circuit pack selection and subhighway and channel number selection of 16-bit address data so that the corresponding circuit pack can send ready signals and output data; A sequential address output circuit section for outputting a 3x3 SM matrix, a sequential address of a buffer memory and a control memory, and providing a 4.096 MHz subhighway clock and an 8KHz synchronous clock as a subhighway matching and multiplexing / demultiplexing module; A fault collection and redundancy control circuit unit which collects a signal of each circuit pack and a fault signal of a power pack in the time switch device and outputs the fault information collected on request of the time switch processor; A time switch / maintenance circuit pack of a mobile communication exchange, characterized in that it comprises a self test path test circuit unit for testing a self-routing path of a time switch device under the control of a time switch processor. The method of claim 1, wherein the subhighway matching and multiplexing / demultiplexing module is configured to match the signal service device, the recording guide device, and the conference call device to 32 subhighways, and by multiplexing or demultiplexing the matched 32 subhighways. A time switch / maintenance circuit pack for a mobile communication switch, characterized in that it is configured to perform a multiplexing / demultiplexing circuit pack function and a time slot interchange function.

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