KR950002869Y1 - Bit rate conversion system in high way lines - Google Patents

Abstract

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Description

Highway Bit Rate Inverter

1 is a local sub-system block diagram of the redundancy of the present invention.

2 is an internal block diagram of a highway bit rate converter of the present invention.

The present invention relates to a communication exchange system of an exchange, and in particular, performs a matching function between a global service device having a tertiary or conference call function and a recording guide function for conveying fault information or living information, etc. The present invention relates to a highway bit rate converter.

Specifically, when the user wants to use the recording guidance information and the conference call function accommodated in each telephone station, the user selects the button of the telephone connected to the subscriber channel to store the information desired by the global service device as a voice pattern. It was made to be sent to the inquirer for listening.

Conventionally, a time slot switch for performing a connection function with a global service device is used in a space division switch, which is an exchange method in which a connection path is used between input and output terminals according to a specific call and the connection path is continuously dedicated during the holding time of the call. The local sub system was constructed by connecting the optical cable between the time slot switch and the space division switch to transmit at 131M b / s.

In the electronic switch, the time slot switch is accommodated in a local sub system, and thus has a problem such as standardization when a global service device is accommodated in a specific local sub system.

Therefore, by developing a device that has a time slot switch function and transmits it at 8M b / s transmission speed with the space division switch, it avoids the use of expensive equipment such as optical cables. It has the advantages of convenience and standardization.

Accordingly, a main object of the present invention is to provide a highway bit rate converter that is matched with a space division switch and a global service device to accommodate a global service device in a common sub system.

This will be described in detail with reference to the accompanying drawings.

FIG. 1 is a redundant highway bit rate converter showing the main components of the present invention. The data is duplicated at a data rate of 8192K b / s from the space split switch (A) and (B) via an interface terminal. The high-speed bit rate converter is matched to the global service device, and the voice data is selected by the internal service logic and outputted by the global service device, and the transmission speed is 2048K b / s. At the speed, the highway bit rate converter transfers the service data stored in the voice memory to the interrogator side by the synchronization of the dual processor and the control of the voice data address.

2 is a redundant high-speed bit rate converter showing the main components of the present invention. The data transmitted from the interrogator side is divided into 8192K b / s through the redundancy devices (A) and (B) of the space division switch. A voice memory 22 for accessing and sequentially storing data by a latch receiving end 21 for storing at a speed, the latch means being connected, and accessing data sequentially by selection of a fault collection and redundancy path test step under the control of a processor; A control memory 25 is configured to address the voice memory to transmit data stored in the data to the time slot at a rate of 2048K b / s, and is physically connected to the control memory for global service and subscriber calls. A processor 31 for controlling selection and address is connected and the demultiplexer 23 retrieves parity of data and demultiplexes in the form of serial data. The multiple station through a flower bed 23 Save a short latches the output data to TTL driver 24 is transmitted to the global service.

The global service device selects and outputs subscriber channel data based on internal specific logic for the request from the inquirer. The transmission rate is 2048K b / s.

The subscriber channel data is connected to a sub highway composed of 32 channels of the highway bit rate converter. The TTL receiver 27 inputs in the form of serial data and the input data can be transmitted at a rate of 8192K b / s parallel data, and 8192K 2048K b / s serial 8 bits input from 32 subhighways. A multiplexing stage 28 for converting b / s into parallel data, a voice memory 29 for sequentially storing subscriber channel data, and subscriber channel data temporarily stored in the voice memory 29 are stored in 16 bits of control memory. The control memory 33, which is selected by the control data, is randomly used by the processor and is sequentially read or performed by the clock divided by the counter 26, and converts the input subscriber channel data into parallel data. It consists of a latch means 30 which serves to transmit to the space division switch.

As described above, the highway bit rate converter is provided in a common sub system and configured to be matched with a global service device and a space division switch, thereby providing an efficient service at a lower cost.

Claims (1)

In a local sub system of an electronic exchange, a latch receiving end (21) which sequentially stores data transmitted from an inquirer's side via a duplication device (A) and (B) of a space splitting switch, and a latch receiving end, is stored in a processor. A voice memory 22 for accessing and sequentially storing data by failure collection and control of a redundant path test stage by control, and an address of the voice memory to transfer data stored in the voice memory 22 to a time slot The control memory 25 retrieves the parity of the data and demultiplexes the serial data into a demultiplexer 23 and a TTL driver, which is temporarily latched and transmitted as a global service. TTL receiver 27 inputs in the form of serial data and serial 8 bits input from 32 transmission paths into 8 bits of parallel data. The switching includes the multiplexing section 28, the voice memory 29 which sequentially stores the subscriber channel data, and the sequential reading of the control data by a clock which is randomly used by the processor and divided by the counter. The subscriber channel data temporarily stored in the voice memory includes the control memory 30 which is a means selected by the control data consisting of 16 bits of the control memory, and the subscriber channel data to be output to the inquirer side. And a latch drive stage (30) which sequentially stores data output from the voice memory (29) for outputting to a space division switch.