KR100289621B1 - Transform and inverse transform encoding apparatus of video encoder and method thereof - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a video encoding apparatus using transform and inverse transform encoding.

2. The technical problem to be solved by the invention

The present invention is configured to be used four times repeated one-dimensional DCT / IDCT four times with only one one-dimensional DCT / IDCT to increase the utilization of hardware, thereby reducing the power consumption of the video encoder conversion and An inverse transform encoding apparatus and a method thereof are provided.

3. Summary of Solution to Invention

The present invention provides one discrete cosine transform / inverse discrete cosine transform means for converting a video input from outside into frequency components by means of discrete cosine transforms; Quantization / inverse quantization means connected to one discrete cosine transform / inverse discrete cosine transform means and dividing the discrete cosine transformed values into different quantization steps according to the importance of their frequency components; And scanning conversion means for transferring the quantized data to the variable length encoding means by changing the scanning order, and using the discrete cosine transform / inverse discrete cosine transform means repeatedly for a predetermined number of times.

4. Important uses of the invention

The present invention is used for transform and inverse transform encoding of a video encoding apparatus.

Description

Transform and inverse transform encoding apparatus of video encoder and method thereof

The present invention relates to a video encoding apparatus using transform and inverse transform encoding. In particular, a single one-dimensional Discrete Cosine Transform / Inverse Discrete Cosine Transform (DCT / IDCT) is used. The present invention relates to an apparatus and a method for improving the utilization of hardware by configuring the module to be repeatedly used only four times with the dimension DCT / IDCT.

The MPEG-2 video encoding apparatus is largely composed of an input module that receives an image as an input, a ME / MC module for motion compensation and estimation, a frame memory module that manages the entire memory, a converter module related to data conversion such as DCT, and a variable length. It may be divided into a variable length coding (VLC) module for encoding. In particular, the converter module, which consists of DCT / IDCT and quantizer / dequantizer (Q / IQ), is the part where the image is compressed the most due to the configuration of the entire encoder circuit. Compared to time-consuming modules.

In this regard, a video encoding apparatus, in particular, a transform and inverse transform encoding apparatus, has been conventionally implemented using two two-dimensional DCT / IDCT, a quantizer / inverse quantizer, and a scan converter. Here, the two-dimensional DCT / IDCT can be separated into two 1-dimensional DCT / IDCT and one matrix transpose due to the orthogonal transformation characteristics and separation of the orthogonal transformation of the DCT transform. In the related art, two two-dimensional DCT / IDCTs implemented as described above are used for the DCT and the other for the IDCT, so that hardware that performs the same function is repeatedly used. This not only increases the hardware cost for the overall transform and inverse transform encoding, but also increases the power consumption.

To solve this problem, Uramoto et al. Described in the article "; IEJJ of the Solid-State Circuit"; "A 100MHz 2-D DCT Core Processor (pp. 492-499)"; Under the title, the technique of using two-dimensional DCT / IDCT and one pre-circuit circuit for implementing two-dimensional DCT / IDCT has been published, but the conventional problems have not been improved much.

Accordingly, an object of the present invention is to provide a video encoder transform and inverse transform encoding apparatus and method for reducing hardware cost and power consumption.

In addition, another object of the present invention, a video encoder transform and inverse transform encoding apparatus and method for improving the utilization of the hardware by configuring the repeated DCT / IDCT can be used repeatedly multiple times with only one 1-D DCT / IDCT only To provide.

1 is a block diagram of a video encoder using a transform and inverse transform device according to the present invention.

2 is a block diagram of a transform and inverse transform device according to the present invention.

3 is a timing diagram of a transform and inverse transform device according to the present invention.

4 is a timing diagram for input data DATA_IN of FIG. 2;

5 is a diagram illustrating the configuration of an interface device for input data DATA_IN of FIG. 2.

6 is a diagram illustrating the configuration of an interface device for the output data TO_DPCM of FIG. 2.

7 is a data output flow chart for the output data TO_VLC of FIG.

8 is a zigzag scan flow chart.

9 is an alternate injection flowchart.

10 is a diagram illustrating data order mapping relations different from zigzag and alternate scans in generating an output address in a scan address generator (SAG).

FIG. 11 is a diagram showing an implementation scheme of a two-dimensional DCT / IDCT (Discrete Cosine Transform / Inverse Discrete Cosine Transform) used in the present invention. FIG.

12 is a structural diagram of a one-dimensional DCT / IDCT using a 3-bit serial distributed operation for the transform and inverse transformer proposed in the present invention.

13 is an input data timing schedule of DCT / IDCT for a transform and an inverse transformer according to the present invention.

14 is a circuit diagram for the PISO of FIG.

FIG. 15 is a circuit diagram for the PISO of FIG. 2. FIG.

* Explanation of symbols for the main parts of the drawings

100: 1-D DCT / IDCT 200A: Quantizer

200B: Inverse Quantizer

An apparatus of the present invention for achieving the above objects, in the transform and inverse transform encoding apparatus of the video encoder, a discrete cosine transform / inverse for converting the video input from the outside into a frequency component by the discrete cosine transform (DCT) Discrete cosine transform (DCT / IDCT) means; Quantization / inverse quantization means connected to said discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means and dividing the discrete cosine transform (DCT) values into different quantization steps according to the importance of their frequency components; And scanning conversion means for transferring the quantized data to the variable length coding means by changing the scanning order, wherein the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means is repeatedly used a predetermined number of times.

The transform and inverse transform encoding apparatus of the video encoder according to the present invention inputs the output of the quantization / inverse quantization means and external data to be transmitted to the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means. Buffering means; And output buffering means for transferring the output of the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means to the quantization / dequantization means.

A method of the present invention for achieving the above objects, in the transform and inverse transform encoding method of a video encoder, the video input from the outside to a frequency component by one discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means A first step of converting; Dividing the discrete cosine transform (DCT) values through one discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means into different quantization steps according to the importance of the frequency component; And a third step of transferring the quantized data to the variable length encoding means by changing the scanning order, wherein the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means is repeatedly used a predetermined number of times.

The transform and inverse transform encoding method of the video encoder according to the present invention transmits the output of quantization / dequantization means and external data to the single discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means through an input buffering means. A fourth step of doing; And a fifth step of delivering the output of the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means to the quantization / dequantization means through an output buffering means.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do. In the drawings, the same reference numerals are used for the same components as in the prior art.

The transform and inverse transform encoding apparatus of the video encoder using only one one-dimensional DCT / IDCT proposed in the present invention is used as part of the entire encoding apparatus as shown in FIG. In FIG. 1, a right dotted block represents the concept of a video encoder's transform and inverse transform encoding apparatus using only one 1D DCT / IDCT according to the present invention. The configuration is largely one DCT / IDCT unit 100 for converting the video input from the outside into a frequency component by the DCT, and the DCT-converted values connected to the one DCT / IDCT unit According to the importance of the quantizer / dequantizer unit 200 divided into different quantization step, and the scanning converter unit for transferring the quantized data to the variable length coder in the scanning order is the main configuration.

In FIG. 1, the DCT unit 100 converts an external video input into a frequency component by DCT (Discrete Cosine Transform), and Q (Quantization) 200A converts DCT transformed values of the frequency component. By dividing into different quantization steps according to importance, it reduces the number of bits to be encoded and increases the compression rate. The SCAN converts the quantized data into a variable length coding (VLC) by changing the scanning order. In addition, the quantized data is passed back for use in differential pulse coded modulation (DPCM) through an inverse discrete cosine transform (IDCT) 100 and an inverse quantization (IQ) 200B.

The transform and inverse transform encoding apparatus proposed by the present invention uses a 54 MHz sck4 as a clock and must process one macro block whenever a mbck (macro block clock) for DCT appears. Since macroblock clocks occur every 660 clocks with a 27MHz sck2, the device must be configured to handle one macroblock every 1320 clocks with sck4. The encoding apparatus according to the present invention requires the following signals in addition to the sck4 and macroblock clock signals. Table 1 below describes the input and output signals and functions of the encoding apparatus according to the present invention.

altscan Scanning Method Selection Signal sck4 54 MHz clock signal DATA_IN (9) Data input to DCT from DPCM part FROM_VLC (12) DCT data from VLC SRAM MB_CK Macroblock Clock QSCALE_CODE (5) Quantization scale code value input to quantizer from bit rate controller QSCALE_TYPE Quantization scale type designation signal input to quantizer from bit rate controller RESET System reset signal TO_DPCM (9) IDCT output data output to DPCM VLC_MEM_ADDR (6) Address input to SRAM in VLC

For real-time processing of the transform and inverse converter, five operations of 2D DCT, Q, IQ, 2D IDCT, and SCAN within 1320 clock allocated to processing one macroblock when using 54 MHz sck4 clock should be performed. do. Comparing the amount of computation and the complexity of the hardware, the computational time of the two-dimensional DCT and the IDCT is the total of two parts of the clock scheduling of the transform and inverse transform device, which consists of the entire two-dimensional DCT, Q, IQ, two-dimensional IDCT, and scan Occupies. Therefore, consideration of the operation of DCT / IDCT is an important key to whether the entire apparatus is processed in real time. In the case of two-dimensional DCT / IDCT, since the mathematical operation is an orthogonal transformation, the same operation of one-dimensional DCT / KDCT is performed twice, and two one-dimensional DCT / IDCT operations are performed with only one one-dimensional DCT / IDCT. DCT / IDCT can be implemented. Based on these properties, we use a single one-dimensional DCT / IDCT to construct a two-dimensional DCT / IDCT that performs the operation of the first one-dimensional DCT, the second one-dimensional DCT, the first one-dimensional IDCT, and the second one-dimensional IDCT. Configure. Since one 1-D DCT / IDCT needs to perform 4 1-D DCT / IDCTs, in order to process 6 blocks in real time, the transform and inverse transform apparatus must perform 12 blocks within 1320 clocks.

Scheduling of the entire clock that satisfies the above constraints is described below. The overall structure of the transform and inverse transform device is shown in FIG. 2, and the input / output timing is shown in FIG. 3.

In this structure, as shown in FIG. 2, only six blocks are performed at the same time for the operation and quantization of the DCT in the DCT unit. In this case, six blocks that do not go through this IQ and IDCT are stored. RAM is needed. In this case, the SRAM used in the adjacent VLC is used instead of the SRAM, and data is quantized in the SRAM, so that the alternate or zig-zag scan is performed. In order to use it again in IQ and IDCT, ISCAN (Inverse SCAN) work is needed. This operation may be performed in the same manner as in the case of storing the address generated by the scan address generator SAG. In the transform and inverse transform apparatus, as shown in FIG. 2, six blocks are performed at the same time by DCT and Q, stored in VLC_DCT_MEM (SRAM), and read back to perform IQ and IDCT. In addition, the ID DCT / IDCT core receives one column (8 pixel) of data at the same time, and simultaneously outputs one column as an output. In the case of ID, five clocks are used to process one column. Since it takes 8 data every 5 clocks, it should be input. In the case of the second one-dimensional output, it takes 7 clocks and needs to process 8 data every 7 clocks. Therefore, in order to apply to an existing structure in which one pixel value is input every clock, an input buffer for solving the underflow of data at the input unit and 7 from DCT / IDCT Output buffer for synchronizing the data of one column output per clock with the data rate of an adjacent device that receives one pixel of data every clock. Will be needed.

In the form of input to DCT / IDCT from DPCM, which is an adjacent device of DCT / IDCT, one pixel value is output every clock. The value of DCT / IDCT can give 64 data for 64 clocks on the input side, and because IDCT requires 64 data for 35 clocks, the difference of 64-35 = 29 pixels is stored in the buffer. Should be. In addition, since 8 pixels must be processed in parallel in order of pixel-by-pixel data, a normal input to parallel output (SIPO) buffer is required, which is a general flip-flop to store 3 columns (24 pixels) of data. A single column SIPO buffer is required on the input side with (F / F: Flip Flop) buffer. On the output side, 8 pixels per 7 clocks must be processed, so one data is accumulated to process one column, and eight data are accumulated to process eight columns, that is, one block. PISO buffer which can handle 2 columns because PISO (Parallel Input to Serial Output) buffer is needed to send out buffer to store 8 columns (8 pixels) and 8 data output in parallel one by one Is needed. As shown in FIG. 3, the input of the converting and inverse converting device receives data of 6 blocks by repeating an operation of receiving data for 64 clocks after the macroblock clock, stopping 32 clocks, and then receiving data for 64 clocks again, and outputting the same. The data output for 64 clocks and the rest of 32 clocks are repeated six times to output all the results.

The interface with the peripheral device will be described below.

For the interface of DPCM, first, when different clocks are used, 1) data is transmitted to 54MHz by conversion and inverse conversion device, and 2) interface with data transmitted by 54MHz after IDCT. This is done through a buffer in the DPCM. 1), basically, the output is 54MHz, the enable (enable) signal should be shown in the form as shown in Figure 4, Figure 4 shows the DCT_ENABLE signal of the conversion and inverse conversion device. In order to make the signal as shown in Fig. 4, the clock of the device is set to sck2 and counts 32 clocks (sck4 64 clocks) and 16 clocks (sck4 32 clocks), respectively, and counts six blocks, and then enables the enable signal again. Perform the wait operation.

5 is a diagram illustrating a process of reading and subtracting a stored value from an SRAM and subtracting it, and then sending the converted and inverse transform apparatus to all of the RAM control signals and addresses at 54 MHz according to dct_enable. do. The value input from the transformed and inverted device is combined with the motion compensated data and stored back in RAM. Therefore, there is a need for a device that reads motion compensation data to be combined with an IDCT value input from a transform and inverse transform device in the order in which the IDCT values are received from the RAM, and stores the added values back into the RAM. The data flow for this is shown in FIG.

The interface with VLC is as follows. Data after the DCT and Q are shown in the order shown in FIG. However, the result of DCT is DC (Korean name or English full name:

Values close to DC and AC (Korean name or English full name:) values become important, and the remaining high frequency components are close to zero, which is likely to become zero by quantization. Therefore, if the current order is used as it is, it is not helpful for compression since all zero values of the unnecessary structure wave must be coded.

For this reason, the quantized data is changed in a zigzag manner as shown in FIG. 8 or as an alternate method as shown in FIG. 9, so that only useful data is coded. To this end, the SAG unit looks at the altscan signal of the DCT data in the order of FIG. 10, and if the altscan is 1, the address corresponding to the alternate scan order is 0, and the address corresponding to the zigzag scan sequence is 0. And then pass this value to the VLC with the SRAM to store the result of the quantization. Likewise, the same ROM table can be used when the quantized result is read and scanned in reverse order (SCAN). When data is read or written to the SRAM of the VLC, addresses generated in the SAG unit are output in the order shown in FIG. 10.

The design of the one-dimensional DCT / IDCT unit is described as follows. Various implementations of DCT have been proposed to date, and this study is based on direct computation using matrix decomposition. The algorithm used in this study has a small number of multiplications for processing one pixel value as a matrix decomposition method, and thus an error size due to multiplication is small. There is this. In the low error algorithm, the internal minimum number of processing bits of the circuit to be implemented is small, and the overall circuit size is reduced. In addition, since the number of clocks allocated to the DCT unit is small for the implementation of the conversion and inverse transformation, a direct calculation method using matrix decomposition is suitable.

The hardware implementation scheme of the DCT is illustrated in FIG. 11. Since the implementation of 2-D DCT / IDCT is a DCT (Discrete Cosine Transform) is an orthogonal transform, the one-dimensional and two-dimensional operations are the same. The hardware implementation of 1-D DCT / IDCT reduces the dimension of the matrix through matrix decomposition and then implements it directly in hardware. The matrix operation method is based on 3-bit serial processing through a ROM multiplier. 12 shows a block diagram of the implemented 1-D DCT / IDCT. In order to implement 2-D DCT / IDCT, 1-D DCT / IDCT is repeatedly used. In the present invention, 2-D DCT / IDCT is implemented using only one 1-D DCT / IDCT that is repeatedly used. In addition, this process was applied to two-dimensional IDCT, and consequently, one two-dimensional DCT / IDCT was calculated to calculate two two-dimensional DCT / IDCT.

Clock speeds of the one-dimensional DCT / IDCT used in the present invention are shown in FIG. 13 for DCT and IDCT. DCT data is inputted through a first-in first-out circuit (FIFO), and eight pixel data are input in parallel with 9-bit two's complement. In IDCT data, data in which dequantized coefficients are stored in an SRAM buffer is input in parallel in a 12-bit two's complement format. The input data is output in 9 bit 2's complement format after IDCT.

The range of input data and output data is as follows (Table 2).

IDCT input data 12 bit 2's complement -2048-2047 IDCT output data 9 bit 2's complement -256 to 255 DCT input data 9 bit 2's complement -256 to 255 ICT output data 12 bit 2's complement -2048-2047

The internal data format is designed with 21 bits. 16 bits of data are processed four times in the first one-dimensional DCT and six times in the second one-dimensional DCT, and the lower two bits and the upper five bits are rounded and clipped. Will output a value.

The circuit that constitutes the transpose matrix for the calculated values after one-dimensional DCT / IDCT is composed of a multiplexer (MUX) and a flip-flop, not RAM. One precell of a precircuit circuit may consist of 16-bit registers and a multiplexer. In addition, in the case of the last column in which the value of the transpose row is output, the data output is composed of 3 bits, which are DCT / IDCT processing units, not 16 bits. When the output is set to 16 bits, a bus of 18 x 8 = 144 bits is required, which is inefficient because the wiring area occupies a large portion of the wire during layout. To solve this problem, PISO at the input of DCT / IDCT was added to the output of the pre-circuit. At this time, only the multiplexer (MUX) is needed. As a result, the size of the multiplexer for the selection of the 1D / 2D DCT / IDCT required for the input of the DCT / IDCT is reduced to a 3x8 = 24bit multiplexer rather than a 16x8 = 128bit multiplexer (mux). Could.

The input buffer is used to solve the underflow of data generated by the result of DPCM and IQ inputting one pixel value in one clock and the processing speed of DCT / IDCT do not match. In the case of DCT / IDCT, one column is processed every 5 clocks, and an input pixel is input every clock. Therefore, in the case of 1-D DCT / IDCT, one block is processed, and 5 × 7 = 35 clocks are required, which requires a buffer to store data of 64-35 = 29 pixels. Therefore, the size of the input buffer is 12 bits x 29 to store inputs for the two modes of DCT / IDCT.

14 shows the structure of an input buffer. In FIG. 14, each input of an 8: 1 multiplexer (mux) is connected at three flip-flop (F / F) intervals, and the interval between each window is 5 clocks. Therefore, if the address of the multiplexer (MUX) is increased every 5 clocks of reading data in DCT / IDCT, 8 columns of data can be read in order.

15 shows an output buffer in which DCT results and IDCT results are Q and DPCM, respectively, and one pixel data is input in one clock. The result from DCT / IDCT is one column (COLUMN) data every 7 clocks, so all the results are output only at 7x7 = 49 clocks, and 1 block of data must be output for 64 clocks. A buffer of is required.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.

As described above, if it is configured to perform four iterations using only one 1D DCT / IDCT proposed in the present invention, an area reduction effect of about 3/4 can be obtained when the video encoding apparatus is implemented in hardware. To this end, in the present invention, a buffer is added to the input / output part to facilitate the interface with adjacent devices, and 3-bit serial distributed operation that is performed by shifting 3 bits at a time to improve the internal processing speed of 1-dimensional DCT / IDCT. The structure is adopted. This can be utilized to reduce the cost of hardware area and power consumption when implementing a system for video encoding in the field of video signal processing.

Claims (9)

In the transform and inverse transform encoding apparatus of a video encoder, One discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means for converting a video input from an external source into a frequency component by a discrete cosine transform (DCT); Quantization / inverse quantization means connected to said discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means and dividing the discrete cosine transform (DCT) values into different quantization steps according to the importance of their frequency components; And Scanning conversion means for transferring the quantized data to a variable length encoding means by changing the scanning order; And the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means is repeatedly used a predetermined number of times. The method of claim 1, Input buffering means for inputting the output of the quantization / inverse quantization means and external data to the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means The transform and inverse transform encoding apparatus of the video encoder further comprising. The method of claim 2, And the input buffering means is composed of SRAMs. The method according to claim 1 or 2, Output buffering means for delivering the output of said discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means to said quantization / dequantization means The transform and inverse transform encoding apparatus of the video encoder further comprising. The method of claim 4, wherein And the output buffering means is composed of SRAMs. In the transform and inverse transform encoding apparatus of a video encoder, One discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means for converting a video input from an external source into a frequency component by a discrete cosine transform (DCT); Quantization / inverse quantization means connected to said discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means and dividing the discrete cosine transform (DCT) values into different quantization steps according to the importance of their frequency components; Input buffering means for inputting the output of said quantization / dequantization means and external data to said discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means; Output buffering means for transferring the output of said discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means to said quantization / dequantization means; And Scanning conversion means for transferring the quantized data to a variable length encoding means by changing the scanning order; And the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means is repeatedly used a predetermined number of times. In the transform and inverse transform encoding method of a video encoder, A first step of converting video input from the outside into frequency components by means of one discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means; Dividing the discrete cosine transform (DCT) values through one discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means into different quantization steps according to the importance of the frequency component; A third step of transferring the quantized data to the variable length encoding means by changing the scanning order, And using the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means repeatedly a predetermined number of times. The method of claim 7, wherein A fourth step of delivering the output of the quantization / dequantization means and the external data to the single discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means through input buffering means; Transform and inverse transform encoding method of a video encoder further comprising. The method according to claim 7 or 8, A fifth step of delivering the output of the discrete cosine transform / inverse discrete cosine transform (DCT / IDCT) means to the quantization / dequantization means through an output buffering means; Transform and inverse transform encoding method of a video encoder further comprising.