KR100284687B1 - Memory device that can access memory cells without RAS / CAS precharge - Google Patents

Abstract

A memory device capable of accessing memory cells without RAS / CAS precharge is disclosed. The memory device may include a memory cell array including a plurality of memory cells, a first low address buffer / decoder for latching a first low address and decoding a latched first low address in response to a first low address strobe signal; And a first sense amplifier configured to sense and amplify data of a memory cell designated by an output signal of the first low address buffer / decoder among the memory cells. In response to a first column address strobe signal, a first column address buffer / decoder and a second low address strobe signal latching the first column address and decoding the latched first column address to access the first sense amplifier. A second low address buffer / decoder for latching a second low address and decoding the latched second low address, and data of a memory cell designated by an output signal of the second low address buffer / decoder among the memory cells. In response to the sensed second sense amplifier and the two column address strobe signals, a second column address buffer / decoder latches the second column address and decodes the latched second column address to access the second sense amplifier. It is characterized by including.

Description

Memory device capable of accessing memory cells without RAS / CAS precharge

1 is a schematic block diagram of a typical DRAM / VRAM.

2 is a block diagram of a memory device according to the present invention.

FIG. 3 is a detailed block diagram of the sense amplifier controller shown in FIG. 2. FIG.

4 is a timing diagram showing a read cycle of a typical DRAM / SRAM shown in FIG. 1 in the normal mode.

5 is a timing diagram showing a read cycle of the memory device according to the present invention shown in FIG. 2 in the normal mode.

6 is a timing diagram showing a read cycle of a typical DRAM / SRAM shown in FIG. 1 in page mode.

FIG. 7 is a timing diagram showing a read cycle of the memory device according to the present invention shown in FIG. 2 in the page mode.

The present invention relates to a memory device, and more particularly, to a memory device capable of improving memory access bandwidth with access to memory cells without RAS / CAS precharge.

Rapid advances in the design and processing of semiconductor memories have increased the capacity of memory chips at an enormous rate, while the access speed of memory chips has been greatly improved. The memory cells of the DRAM and the VRAM have a two-dimensional array type, so that row and column addresses may be separated and addressed twice to access bits of a desired memory cell. However, in the burst mode, that is, the page mode, it is possible to address several consecutive column memory cells located in the same row with one row address, thereby improving access speed. . However, in the normal mode, when the row address is changed, the next address becomes valid after each RAS precharge time has elapsed. In such a case, a considerable overhead must be paid for the memory access. This will be described in more detail as follows.

In normal mode, a DRAM / VRAM with a memory access time of 60 ns, for example, has a low address strobe (RAS) precharge time of 40 ns and a single read cycle or write cycle of 100 ns. On the other hand, in the page mode, a column address strobe (CAS) precharge time of 10 ns is required every time the column address is changed for successive column addresses. Therefore, in high-speed image processing that requires row vector or column vector access or high-speed graphics processing with the characteristics of locality of reference (LOR), RAS precharge time and CAS precharge time are a significant overhead for the overall system performance. There is a problem that degrades performance.

Accordingly, an object of the present invention is to provide a memory device capable of improving the memory access bandwidth, that is, the memory access speed by accessing memory cells without RAS / CAS precharge to solve the above problems.

In order to achieve the above object, a memory device according to the present invention includes a memory cell array including a plurality of memory cells; A first low address buffer / decoder, in response to the first low address strobe signal, latching the first low address and decoding the latched first low address; A first sense amplifier configured to sense and amplify data of a memory cell designated by an output signal of the first low address buffer / decoder among the memory cells; A first column address buffer / decoder for latching a first column address and decoding the latched first column address to access the first sense amplifier in response to a first column address strobe signal; A second low address buffer / decoder, in response to the second low address strobe signal, latching the second low address and decoding the latched second low address; A second sense amplifier configured to sense and amplify data of a memory cell designated by an output signal of the second low address buffer / decoder among the memory cells; And a second column address buffer / decoder for latching the second column address and decoding the latched second column address to access the second sense amplifier in response to a two column address strobe signal.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a general DRAM / VRAM. Referring to this, the general DRAM / VRAM includes a memory cell block, an input / output buffer, a refresh address counter, and a control and clock signal generator. The memory cell block includes a memory cell array, an address buffer, a row decoder, a column decoder, and a sense amplifier. The DRAM further includes a serial data register / selector and a serial input / output buffer.

2 is a block diagram of a memory cell block of a memory device, that is, a DRAM / VRAM according to the present invention. The memory cell block shown in FIG. 2 is a portion corresponding to the memory cell block among the components of the general DRAM / VRAM shown in FIG.

Referring to FIG. 2, the memory cell block of the memory device according to the present invention has a dual address buffer form and includes a memory cell array 28 and a first low address buffer / decoder 21 including a plurality of memory cells. , The second low address buffer / decoder 22, the first column address buffer / decoder 23, the second column address buffer / decoder 24, the first sense amplifier 25, the second sense amplifier 26 And a sense amplifier section 27.

The first low address buffer / decoder 21 latches the first low address of the address ADDR applied from the outside and decodes the latched first low address in response to the first low address strobe signal RAS /. . The first sense amplifier 25 senses and amplifies data of a memory cell designated by an output signal of the first low address buffer / decoder 21 among the memory cells of the memory cell array 28. The first column address buffer / decoder 23 latches the first column address of the address ADDR applied from the outside in response to the first column address strobe signal CAS / to decode the latched first column address. The first sense amplifier 25 is accessed. The output of the accessed first sense amplifier 25 is output to the outside via a path not shown.

The second low address buffer / decoder 22 latches the second low address of the address ADDR externally applied and decodes the latched second low address in response to the second low address strobe signal RAS '/. do. The second sense amplifier 26 senses and amplifies data of a memory cell designated by an output signal of the second low address buffer / decoder 22 among the memory cells of the memory cell array 28. The second column address buffer / decoder 24 latches the second column address of the externally applied address ADDR in response to the second column address strobe signal CAS ′ / and decodes the latched second column address. The second sense amplifier 26 is accessed. The output of the accessed second sense amplifier 26 is output to the outside via a path not shown.

FIG. 3 is a detailed block diagram of the sense amplifier controller 27 shown in FIG. 2. Referring to this, the sense amplifier controller 27 may include one T flip-flop 31 and four oragates. 32 to 35). In the normal mode, RAS / and RAS '/ are alternately used to enable the sense amplifiers 25 and 26.

Referring to FIG. 3, the sense amplifier control unit 27 controls the data of the memory cell selected by the row address to be appropriately loaded into the first and second sense amplifiers 25 and 26 according to the operation mode. do. That is, data of different row addresses are loaded into the first and second sense amplifiers 25 and 26 in the normal mode, and data of the same row address is loaded in the page mode. A detailed description thereof will be described in detail in the operation description section below.

4 is a timing diagram showing a read cycle of the general URAM / SRAM shown in FIG. 1 in the normal mode, and FIG. 5 is a timing diagram showing a read cycle of the memory device according to the present invention shown in FIG. 2 in the normal mode. to be.

Hereinafter, an operation in the normal mode of the memory device according to the present invention shown in FIG. 2 will be described with reference to the timing diagram shown in FIG. 5. In the read / write operation of the shin mode, the control signal PG becomes a logic low so that the first row address Rl of the address ADDR applied from the outside is the first low address strobe signal RAS / in response to the first row address strobe signal RAS /. Latched and decoded by the low address buffer / decoder 21. Next, the memory cell data of the row selected by the output signal of the first low address buffer / decoder 21 among the memory cells of the memory cell array 28 is electrically sensed and amplified by the first sense amplifier 25. do.

Next, the first column address C1 of the externally applied address ADDR is latched and decoded by the first column address buffer / decoder 23 in response to the first column address strobe signal CAS /. The first sense amplifier 25 is accessed. The output of the accessed first sense amplifier 25 is output to the outside as output data DATA via a path not shown.

In addition, while the output of the first sense amplifier 25 is output to the outside, the second row address R2 of the address ADDR applied from the outside is in response to the second low address strobe signal RAS '/. Latched and decoded by the low address buffer / decoder 22. Next, the memory cell data of the row selected by the output signal of the second low address buffer / decoder 22 among the memory cells of the memory cell array 28 is electrically sensed and amplified by the second sense amplifier 26. do.

Next, the second column address C2 of the externally applied address ADDR is latched and decoded by the second column address buffer / decoder 24 in response to the second column address strobe signal CAS '/. Accordingly, the second sense amplifier 26 is accessed. The output of the accessed second sense amplifier 26 is output to the outside as output data DATA via a path not shown.

Next, the data of the memory cells selected by the row and column addresses R3, C3, R4, C4,... Sequentially applied from outside are sequentially outputted to the outside. Is output as.

Therefore, as described above, the memory device according to the present invention includes two row address buffers / decoders, two column address buffers / decoders, and two sense amplifiers, thereby receiving the first received row and column in response to RAS / and CAS /. The second row and column address in response to RAS '/ and CAS' / even though the memory cell data at addresses R1 and C1 are not completely valid, i.e. while the memory cell data at the first received address is output. (R2, C2) is received and the second memory cell data is output. Accordingly, in the normal mode of the memory device according to the present invention, since the memory cells can be accessed without the RAS precharge time, the memory access band withs, that is, the memory access speed can be improved.

FIG. 6 is a timing diagram showing a read cycle of the general DRAM / SRAM shown in FIG. 1 in page mode, and FIG. 7 is a timing diagram showing a read cycle of the memory device according to the present invention shown in FIG. 2 in page mode. to be.

Hereinafter, an operation in the page mode of the memory device according to the present invention shown in FIG. 2 will be described with reference to the timing diagram shown in FIG. 7. In the read / write operation of the page mode, the control signal PG becomes logic high, so that the second low address buffer / decoder 22 is disabled, and the row address R1 of the address ADDR applied from the outside is reset. It is latched and decoded by the first low address buffer / decoder 21 in response to the one low address strobe signal RAS /. Next, the data of the memory cells of the row selected by the output signal of the first low address buffer / decoder 21 among the memory cells of the memory cell array 28 are first sensed amplifier 25 and second sensed amplifier. It is electrically sensed and amplified by the section 26. That is, data of the same row address is loaded in both the first sense amplifier 25 and the second sense amplifier 26.

Next, the column addresses C1, c2, ... that are sequentially applied externally are first and second column address buffers / decoders in response to the first and second column address strobe signals CAS / and CAS ′ /. Latched and decoded by (23, 24), thereby alternately accessing the first and second sense amplifiers (25, 26). That is, each time the column address changes, the first and second sense amplifiers 25 and 26 are alternately accessed. The output of the accessed first sense amplifier 25 and the output of the second sense amplifier 26 are alternately output to the outside via an unillustrated path as output data DATA.

Therefore, in the page mode of the memory device according to the present invention, since the memory cells can be accessed without the CAS precharge time, the memory access bands, that is, the memory access speed can be improved.

In the memory device according to the present invention as described above, a memory having an access time of 60 ns is taken as an example. In the normal mode, a 40 ns RAS precharge time can be saved, and in the page mode, 10 ns CAS-free. The charge timing can be saved.

In addition, in applications such as image processing, memory cells are often accessed by row or column address units.In this case, when accessing a row vector, the normal mode is enabled to save the RAS precharge time, thereby accessing the memory cells and column. In the case of a vector, a memory cell can be accessed by saving a CAS precharge time.

In graphic applications, RAS precharge time is used for VLD (Vertual Line Drawing), and LOR is characteristic of two-dimensional array due to the characteristics of graphics processing in general. Therefore, multiple column addresses are accessed for the same row address. Memory can be accessed by saving CAS precharge time.

Claims (3)

A memory cell array including a plurality of memory cells; A first low address buffer / decoder, in response to the first low address strobe signal, latching the first low address and decoding the latched first low address; A first sense amplifier configured to sense and amplify data of a memory cell designated by an output signal of the first low address buffer / decoder among the memory cells; A first column address buffer / decoder for latching a first column address and decoding the latched first column address to access the first sense amplifier in response to a first column address strobe signal; A second low address buffer / decoder, in response to the second low address strobe signal, latching the second low address and decoding the latched second low address; A second sense amplifier configured to sense and amplify data of a memory cell designated by an output signal of the second low address buffer / decoder among the memory cells; And a second column address buffer / decoder for latching the second column address and decoding the latched second column address to access the second sense amplifier in response to a second column address strobe signal. . The memory device of claim 1, wherein in the normal mode of the memory device, the first and second low address strobe signals alternately enable the first and second sense amplifiers. The memory device of claim 1, wherein in the page mode of the memory device, one of the first and second low address buffers / decoders is disabled and the first and second sense amplifiers are enabled. And sequentially detecting and amplifying data of memory cells sequentially designated by an output signal of a buffer / decoder.