KR100284290B1 - Standby Current Reduction Circuit Using Substrate Voltage - Google Patents

Abstract

The present invention relates to a standby current reduction circuit using a substrate voltage. In the related art, since a clamp transistor is always turned on in a standby state, a leakage current is generated through the clamp transistor. There is a problem that the consumption is increased. Therefore, the present invention connects the switch transistor Qs and the NMOS transistor NM operated in series between the power supply voltage terminal VCC and the ground terminal VSS by the standby signals / AC and ACT. The clamp transistor Qc and the PMOS transistor PM are connected in series between the voltage terminal VCC and the ground terminal VSS, and the first switch SW1 is connected to the clamp transistor Qc to select the voltage VBB or VSS. The second switch SW2 is connected to the back gate of the PMOS transistor PM so as to select the VCC or VPP voltage, and the source and the clamp transistor Qc of the switch transistor Qs. Connect the local power line VCC_L to the drain of the power supply, connect the local power line VSS_L to the source of the NMOS transistor NM and the drain of the PMOS transistor PM, The local power line VCC_L and Inverter chain 10 is connected between a plurality of inverters in which PMOS transistors P1, P2, P3 .. and NMOS transistors N1, N2, N3, ... are connected in parallel between phosphorus (VSS_L). When the semiconductor integrated circuit is in a short standby state, VCC and VSS are selected as the substrate terminals of the clamp transistor so that the voltage level of the local power line is lowered by the threshold voltage than the main power line to have a fast transition time. In the long standby state, VPP and VBB are selected on the PMOS transistor substrate terminal, so that the voltage level of the local power line is lowered by the increased threshold voltage than the main power line, reducing the leakage current and the fast transition time. It is to ensure that.

Description

Standby Current Reduction Circuit Using Substrate Voltage

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a standby current reduction circuit using a substrate voltage for reducing the sub-threshold current flowing when the semiconductor integrated circuit is in a standby state. In particular, the present invention relates to an active state in the standby state. The present invention relates to a standby current reduction circuit using a substrate voltage that is suitable for low power and low voltage circuits by maintaining a fast transition time when a transition occurs.

FIG. 1 is a circuit diagram of a standby current reduction circuit using a conventional substrate voltage. As shown therein, a switch transistor Qs and an NMOS transistor NM are connected in series between a power supply voltage terminal VCC and a ground terminal VSS. The clamp transistor Qc and the PMOS transistor PM are connected in series between another power supply voltage terminal VCC and the ground terminal VSS, and the source of the switch transistor Qs and the clamp transistor Qc The local power line VCC_L is connected to the drain, and the local power line VSS_L is connected to the source of the NMOS transistor NM and the drain of the PMOS transistor PM. An inverter chain in which a plurality of inverters in which PMOS transistors P1, P2, P3 .. and NMOS transistors N1, N2, N3, ... are connected in series between the power lines VCC_L and VSS_L. 10) is connected and configured.

Looking at the prior art configured in this way in detail as follows.

First, when the semiconductor integrated circuit is in the ACTIVE state, ACT = 1 and / ACT = 0, so that the switch transistor Qs and the NMOS transistor NM are turned on.

As the switch transistor Qs is turned on, a voltage obtained by subtracting the threshold voltage Vt from the power supply voltage VCC is supplied to the powered local power line VCC_L, and the NMOS transistor NM is turned on. Accordingly, the ground voltage is supplied to the ground voltage supplying local power line VSS_L.

When the signal is supplied to the input terminal IN while the voltage is supplied to the local power line VCC_L VSS_L, the PMOS transistors P1, P2, P3, .. and the NMOS transistors N1, N2, N3. Data determined through the inverter chain 10 consisting of.

In this manner, when the semiconductor integrated circuit enters the standby state (Stand-by), ACT = 0 and / ACT = 1, so that the switch transistor Qs and the NMOS transistor NM are turned off.

At this time, the clamp transistor Qc and the PMOS transistor PM continue to be turned on.

Therefore, the voltage dropped to the local power line VCC_L by the threshold of the clamp transistor Qc is supplied and maintained, and the ground voltage is supplied and maintained to the other local power line VSS_L.

If this state is maintained and then the transition from the standby state (Stand-by) to the active state (Active), the transition is quick.

As a result, when the transition from the standby state (Stand-by) to the active state (Active) has a fast transition time.

However, in the prior art as described above, when the voltage transition of the local power line in the standby state by using the clamp transistor to maintain the reduced state by the threshold voltage at the voltage level of the main power line to transition to the operating state Although there is an advantage of having a fast transition time, since the clamp transistor is always turned on, leakage current is generated through the clamp transistor, and when the standby state is long, there is a problem in that power consumption due to leakage current is increased.

Accordingly, an object of the present invention for solving the conventional problems as described above is to connect a switch to a substrate terminal (substrate terminal) of the clamp transistor connecting the main power line and the local power line (Short Stand-By: The present invention provides a standby current reduction circuit using a substrate voltage so that different substrate voltages can be selected according to SSB) and long stand-by (LSB).

Another object of the present invention is to select VCC and VSS as the substrate terminal of the clamp transistor when the semiconductor integrated circuit is in a short standby state, and to make the voltage transition of the local power line drop by the threshold voltage from the main power line to make the fast transition. The present invention provides a standby current reduction circuit using a substrate voltage having a time.

It is still another object of the present invention to select VPP (> VCC) and VBB (< VSS) for the substrate terminals of the clamp transistor when the semiconductor integrated circuit is in a long standby state, thereby maintaining the voltage reduced by the increased threshold voltage. It is to provide a standby current reduction circuit using a substrate voltage to reduce the leakage current compared to the short standby state, and to have a fast transition time.

1 is a standby current reduction circuit diagram using a conventional substrate voltage.

2 is a standby current reduction circuit using the substrate voltage of the present invention.

3A is another embodiment of the first switch in FIG. 2;

Figure 3b is another embodiment of the second switch in Figure 2;

Figure 4 is a voltage characteristic diagram operating in the short standby state and the long standby state in FIG.

*** Explanation of symbols for main parts of drawing ***

10: inverter chain Qc: clamp transistor

Qs: switch transistor NM: NMOS transistor

PM: PMOS transistor

In order to achieve the above object, the present invention provides a series connection between a switch transistor Qs and an NMOS transistor NM operated by a standby signal / AC, ACT between a power supply voltage terminal VCC and a ground terminal VSS. The clamp transistor Qc and the PMOS transistor PM are connected in series between another power supply voltage terminal VCC and the ground terminal VSS, and the first switch SW1 is selected to select the VBB or VSS voltage. The second switch SW2 is connected to the back gate of the PMOS transistor PM so as to be connected to the back gate of the clamp transistor Qc, and to select a VCC or VPP voltage, and the source of the switch transistor Qs. And a local power line VCC_L for supplying power to the drain of the clamp transistor Qc, and a local power line VSS_L for supplying a ground voltage to the drain of the source and PMOS transistors PM of the NMOS transistor NM. ) And the local An inverter in which a plurality of inverters in which PMOS transistors P1, P2, P3 .. and NMOS transistors N1, N2, N3, ... are connected in series between the power line VCC_L and the line VSS_L are connected in parallel. It is characterized in that the chain 10 is configured to connect.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a circuit diagram illustrating a standby current reduction circuit using a substrate voltage according to an embodiment of the present invention. As shown therein, a switch transistor operated by a standby signal (/ AC, ACT) between a power supply voltage terminal VCC and a ground terminal VSS. (Qs) and NMOS transistor (NM) are connected in series, and clamp transistor (Qc) and PMOS transistor (PM) are connected in series between another power supply voltage terminal (VCC) and ground terminal (VSS), and VBB or The first switch SW1 is connected to the back gate of the clamp transistor Qc to select the VSS voltage, and the second switch SW2 is connected to the back gate of the PMOS transistor PM to select the VCC or VPP voltage. A local power line VCC_L for supplying power to a source of the switch transistor Qs and a drain of the clamp transistor Qc, and a source and a PMOS transistor PM of the NMOS transistor NM. Ground voltage at the drain Connect the power supply local power line (VSS_L), PMOS transistor (P1, P2, P3 ..) and NMOS transistor (N1, N2, N3, ..) between the local power line (VCC_L) and the line (VSS_L). Inverter chain (10) is configured by connecting a plurality of inverters connected in series in parallel.

Referring to the operation and effect of the present invention configured as described in detail as follows.

First, when the semiconductor integrated circuit is in the ACTIVE state, ACT = 1 and / ACT = 0, so that the switch transistor Qs and the NMOS transistor NM are turned on.

As the switch transistor Qs is turned on, a voltage obtained by subtracting the threshold voltage Vt from the power supply voltage VCC is supplied to the powered local power line VCC_L, and the NMOS transistor NM is turned on. Accordingly, the ground voltage is supplied to the ground voltage supplying local power line VSS_L.

When the signal is supplied to the input terminal IN while the voltage is supplied to the local power line VCC_L VSS_L, the PMOS transistors P1, P2, P3, .. and the NMOS transistors N1, N2, N3. Data determined through the inverter chain 10 consisting of.

In this manner, when the semiconductor integrated circuit enters the standby state (Stand-by), ACT = 0 and / ACT = 1, so that the switch transistor Qs and the NMOS transistor NM are turned off.

At this time, the voltage level of the power source local power line VCC_L is determined by the threshold voltage Vt of the clamp transistor Qc.

When the semiconductor integrated circuit enters a short standby state (Short Stand-By) among the standby states, the movable terminal of the first switch SW1 connected to the substrate terminal (or the back gate) of the clamp transistor Qc is VSS. It is connected to the power supply terminal, and the movable terminal of the second switch SW2 connected to the substrate terminal (or the back gate) of the PMOS transistor PM is connected to the VCC power supply terminal, respectively.

Then, the clamp transistor Qc is turned on so that the voltage dropped by the threshold voltage Vt of the clamp transistor is supplied to the power supply local power line VCC_L through the clamp transistor Qc, and the PMOS transistor is provided. PM is also turned on to supply the ground voltage source local power line VSS_L.

As a result, in the short standby state, as shown in FIG. 4A, a voltage is supplied between the VCC power supply and the VSS power supply.

In addition, when the semiconductor integrated circuit enters a long standby state (Long Stand-By) of the standby state, the movable terminal of the first switch SW1 connected to the substrate terminal (or the back gate) of the clamp transistor Qc. It is connected to the VBB power supply terminal, and the movable terminal of the second switch SW2 connected to the substrate terminal (or the back gate) of the PMOS transistor PM is connected to the VPP power supply terminal, respectively.

Here, VPP> VCC and VBB <VSS.

Then, the clamp transistor Qc is turned on so that the threshold voltage Vt of the clamp transistor is increased more than the threshold voltage of the short standby state.

The voltage dropped by the increased threshold is supplied to the power supply local power line VCC_L through the clamp transistor Qc, and the PMOS transistor PM is also turned on to supply the ground voltage source local power line VSS_L. )

Accordingly, in the long standby state, the leakage current is reduced in the long standby state, and the voltage level of the local power line can be maintained at a constant level, thereby ensuring a fast transition time from the standby state to the operating state.

As a result, in the long standby state, as shown in FIG. 4B, a voltage between the VPP power supply and the VBB power supply is supplied.

Alternatively, a circuit as shown in FIG. 3A may be used instead of the first switch SW1 and a circuit as shown in FIG. 3B may be applied instead of the second switch SW2.

That is, in the short standby state = 1, long waits 0 is provided to allow VSS, VCC or VBB and VPP voltages respectively to be connected to the substrate terminals of the clamp transistor Qc.

For example, in short standby When = 1 is provided, the NMOS transistor NM1 shown in FIG. 3A is turned on, and 0 inverted through the inverter I1 turns off the other NMOS transistor NM2 to turn off the VSS power supply to the substrate terminal of the clamp transistor. Supply.

And When = 1 is provided, the PMOS transistor PM1 shown in FIG. 3B is turned off, and 1 reversed through the inverter I2 turns on another PMOS transistor PM2 to turn on the VCC power supply to the substrate terminal of the PMOS transistor. To supply.

And long standby When 0 is provided, the NMOS transistor NM1 shown in FIG. 3A is turned off, and 1 inverted through the inverter I1 turns on another NMOS transistor NM2 to turn on the VBB power supply to the substrate terminal of the clamp transistor. Supply.

And, If 0 is provided, PMOS transistor PM1 shown in FIG. 3B is turned on, and 0 inverted through inverter I2 turns off another PMOS transistor PM2 to turn off the PPP power supply to the substrate terminal of the PMOS transistor. To supply.

Therefore, when the semiconductor integrated circuit is in a short standby state, VCC and VSS are selected as the substrate terminals of the clamp transistor so that the voltage level of the local power line is lowered by the threshold voltage than the main power line, so that the transition time is fast. In the long standby state, VPP and VBB are selected in the PMOS transistor substrate terminal, so that the voltage level of the local power line is lowered by the increased threshold voltage than the main power line, thereby reducing the leakage current and fast transitioning. It has the effect of freeing up time.

Claims (5)

Between the power supply voltage terminal VCC and the ground terminal VSS, a switch transistor Qs and an NMOS transistor NM operated by a standby signal / AC, ACT are connected in series, and another power supply voltage terminal VCC is connected. ) And the first switch SW1 is connected to the back gate of the clamp transistor Qc so that the clamp transistor Qc and the PMOS transistor PM are connected in series between the terminal and the ground terminal VSS. The second switch SW2 to the back gate of the PMOS transistor PM so as to select the VCC or VPP voltage, and to the source of the switch transistor Qs and the drain of the clamp transistor Qc. Connect a local power line VCC_L for power supply, connect a local power line VSS_L for ground voltage supply to a source of the NMOS transistor NM, and a drain of the PMOS transistor PM, and connect the local power line. Between (VCC_L) and line (VSS_L) Board characterized in that the inverter chain 10 is connected to the inverter connected in parallel with the MOS transistor (P1, P2, P3 ..) and the NMOS transistor (N1, N2, N3, ...) connected in series Standby current reduction circuit using voltage. The standby current using the substrate voltage of claim 1, wherein the first switch SW1 is configured to switch to the VSS power supply in the short standby state (SSB) and to the VBB power supply in the long standby state (LSB). Reduction circuit. The standby current using the substrate voltage according to claim 1, wherein the second switch SW2 is configured to switch to the VCC power supply in the short standby state (SSB) and to the VPP power supply in the long standby state (LSB). Reduction circuit. According to claim 1, Instead of the first switch (SW1) receives the VSS power source and VBB power source respectively, and the standby signal (the gate terminal) ) And the drain of the NMOS transistors NM1 and NM2 that receive the inverted standby signals through the inverter I1 are connected in parallel to the substrate terminal of the clamp transistor Qc. Current reduction circuit. The VPP power source and the VCC power source are respectively input to the drain instead of the second switch SW2, and the standby signal ( ) And a source of the PMOS transistors PM1 and PM2 respectively receiving the inverted standby signals through the inverter I2 are connected in parallel to the substrate terminals of the PMOS transistor PM. Standby current reduction circuit.