KR100284141B1 - Contact hole formation method of semiconductor device - Google Patents
Contact hole formation method of semiconductor device Download PDFInfo
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- KR100284141B1 KR100284141B1 KR1019980025661A KR19980025661A KR100284141B1 KR 100284141 B1 KR100284141 B1 KR 100284141B1 KR 1019980025661 A KR1019980025661 A KR 1019980025661A KR 19980025661 A KR19980025661 A KR 19980025661A KR 100284141 B1 KR100284141 B1 KR 100284141B1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by physical means, e.g. sputtering, evaporation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76825—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/485—Bit line contacts
Abstract
1. 청구 범위에 기재된 발명이 속하는 기술 분야1. TECHNICAL FIELD OF THE INVENTION
본 발명은 반도체 소자의 콘택 형성 방법에 관한 것임.The present invention relates to a method for forming a contact of a semiconductor device.
2. 발명이 해결하고자 하는 기술적 과제2. Technical problem to be solved by the invention
종래의 콘택 홀(Contact Hole) 오픈(open) 공정시에는 패드 폴리실리콘층 상부의 반사 방지막이 완전히 제거되지 않아, 콘택 저항이 증가하고 콘택이 완전히 오픈되지 않음은 물론 소자의 리프레쉬(refresh) 특성이 저하되는 문제점이 있음.In the conventional contact hole open process, the anti-reflection film on the top of the pad polysilicon layer is not completely removed, so that the contact resistance is increased, the contact is not completely opened, and the refresh characteristics of the device are not improved. There is a problem that is degraded.
3. 발명의 해결 방법의 요지3. Summary of the Solution of the Invention
콘택 홀 오픈 공정 후, 콘택 홀 오픈 공정시 사용한 포토레지스트를 제거하지 않은 상태에서 이온 주입 공정을 실시하고, 포토레지스트 제거 및 세정 공정을 실시한 다음, 티타늄(Ti)을 증착하고 열처리를 실시한 후 비트라인 또는 저장 노드(Storage Node) 형성 공정을 진행함.After the contact hole opening process, the ion implantation process is performed without removing the photoresist used in the contact hole opening process, the photoresist removal and cleaning process is performed, and then the titanium (Ti) is deposited and the heat treatment is performed. Alternatively, the storage node formation process is performed.
4. 발명의 주요한 용도4. Main uses of the invention
고집적 반도체 소자Highly Integrated Semiconductor Devices
Description
본 발명은 반도체 소자의 콘택 홀(Contact Hole) 형성 방법에 관한 것으로, 특히 고집적 반도체 소자의 콘택 홀 형성시 콘택 저항 및 소자의 리프레쉬(Refresh) 특성을 향상시킬 수 있는 반도체 소자의 콘택 홀 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and more particularly, to a method for forming a contact hole in a semiconductor device capable of improving contact resistance and refresh characteristics of a device when forming a contact hole in a highly integrated semiconductor device. It is about.
종래에는 비트라인 또는 저장 노드(Storage Node) 형성을 위한 콘택 홀 오픈(open) 공정시 패드 폴리실리콘층 상부의 반사 방지막이 완전히 제거되지 않아 콘택 저항이 증가하는 문제점이 있었다.In the related art, the contact resistance is increased because the anti-reflection film on the pad polysilicon layer is not completely removed during the contact hole opening process for forming the bit line or the storage node.
도 1은 종래 콘택 홀 형성 방법을 설명하기 위해 도시한 소자의 단면도이다.1 is a cross-sectional view of a device illustrated to explain a conventional method for forming a contact hole.
하부 구조가 형성된 반도체 기판(11) 상부에 제 1 폴리실리콘을 증착한 후 선택된 영역을 패터닝하여 게이트 전극(12)을 형성한다. 이후, 게이트 전극(12) 양측부에 스페이서(13)를 형성한다. 다음에 전체 구조 상부에 패드 폴리실리콘층(14) 및 제 1 반사 방지막(15)을 순차적으로 형성한다. 이후, 전체 구조 상부에 유전체막(16)을 형성한 다음, 콘택 마스크를 이용한 식각 공정으로 유전체막(16)의 선택된 부분을 제거하여 패드 폴리실리콘층(14) 상부의 일부를 노출시킨다.After the first polysilicon is deposited on the semiconductor substrate 11 on which the lower structure is formed, the selected region is patterned to form the gate electrode 12. Thereafter, spacers 13 are formed at both sides of the gate electrode 12. Next, the pad polysilicon layer 14 and the first antireflection film 15 are sequentially formed on the entire structure. Thereafter, the dielectric layer 16 is formed over the entire structure, and then a selected portion of the dielectric layer 16 is removed by an etching process using a contact mask to expose a portion of the upper portion of the pad polysilicon layer 14.
그런데, 이 경우 패드 폴리실리콘층(14) 상부에 형성된 반사 방지막(15)이 완전히 제거되지 않아 콘택 저항이 증가하고 콘택 홀이 완전히 오픈되지 않으며 소자의 리프레쉬 특성이 저하되는 문제점이 있다.However, in this case, since the anti-reflection film 15 formed on the pad polysilicon layer 14 is not completely removed, the contact resistance is increased, the contact holes are not completely opened, and the refresh characteristics of the device are deteriorated.
따라서, 본 발명은 콘택 홀 오픈 공정 후, 콘택 홀 오픈 공정시 사용한 포토레지스트를 제거하지 않은 상태에서 이온 주입 공정을 실시하고, 포토레지스트 제거 및 세정 공정을 실시한 다음, 티타늄(Ti)을 증착하고 열처리를 실시한 후 비트라인 또는 저장 노드 형성 공정을 진행하므로써, 콘택 저항을 감소시키고 소자의 리프레쉬 특성을 향상시킬 수 있는 반도체 소자의 콘택 홀 형성 방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, after the contact hole opening process, the ion implantation process is performed without removing the photoresist used in the contact hole opening process, the photoresist removal and cleaning process is performed, and then titanium (Ti) is deposited and heat treated. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device capable of reducing contact resistance and improving refresh characteristics of a device by performing a bit line or a storage node forming process after performing the process.
상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 콘택 홀 형성 방법은 반도체 소자의 콘택 홀 형성 방법에 있어서, 하부 구조가 형성된 반도체 기판 상에 유전체막을 형성하고 콘택 홀 형성용 포토레지스트를 도포한 후 식각 공정을 실시하여 콘택 홀을 형성하는 단계와, 전체 구조에 대하여 이온 주입을 실시하는 단계와, 상기 포토레지스트를 제거한 후 세정 공정을 실시하는 단계와, 상기 콘택 홀을 포함한 전체 구조 상부에 티타늄을 증착한 후 급속 열 어닐링 공정을 실시하는 단계를 포함하여 이루어지는 것을 특징으로 한다.In the method for forming a contact hole of a semiconductor device according to the present invention for achieving the above object, in the method for forming a contact hole of a semiconductor device, a dielectric film is formed on a semiconductor substrate on which a lower structure is formed and a photoresist for forming contact holes is coated. Forming a contact hole by performing an etching process, performing ion implantation on the entire structure, performing a cleaning process after removing the photoresist, and titanium on the entire structure including the contact hole. After the deposition is characterized in that it comprises a step of performing a rapid thermal annealing process.
도 1은 종래 콘택 홀 형성 방법을 설명하기 위해 도시한 소자의 단면도.1 is a cross-sectional view of a device shown for explaining a conventional method for forming a contact hole.
도 2(a) 내지 2(c)는 본 발명의 제 1 실시예에 따른 반도체 소자의 콘택 홀 형성 방법을 설명하기 위해 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to a first embodiment of the present invention.
도 3(a) 및 3(b)는 본 발명의 제 2 실시예에 따른 반도체 소자의 콘택 홀 형성 방법을 설명하기 위해 도시한 소자의 단면도.3 (a) and 3 (b) are cross-sectional views of a device for explaining a method for forming a contact hole in a semiconductor device according to a second embodiment of the present invention.
〈도면의 주요 부분에 대한 부호 설명〉<Description of Signs of Major Parts of Drawings>
21, 31 : 반도체 기판21, 31: semiconductor substrate
22, 32 : 제 1 폴리실리콘층(게이트 전극)22, 32: first polysilicon layer (gate electrode)
23 : 스페이서 24, 33 : 패드 폴리실리콘층23: spacer 24, 33: pad polysilicon layer
25 : 제 1 반사 방지막 26, 36 : 유전체막25: first antireflection film 26, 36: dielectric film
27 : 포토레지스트 28, 37 : 티타늄막27: photoresist 28, 37: titanium film
29, 35 : 제 2 폴리실리콘층(비트라인) 30 : 제 2 반사 방지막29 and 35: second polysilicon layer (bit line) 30: second antireflection film
34 : 반사 방지막 38 : 폴리실리콘층34: antireflection film 38: polysilicon layer
A, B : 티타늄 실리사이드층A, B: titanium silicide layer
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
도 2(a) 내지 2(c)는 본 발명의 제 1 실시예에 따른 반도체 소자의 콘택 홀 형성 방법에 관한 것으로, 비트라인용 콘택 홀을 형성하는 경우의 예이다.2 (a) to 2 (c) relate to a method of forming a contact hole in a semiconductor device according to a first embodiment of the present invention, which is an example of forming a contact hole for a bit line.
도 2(a)에 도시된 바와 같이, 하부 구조가 형성된 반도체 기판(21) 상부에 제 1 폴리실리콘층을 증착한 후 게이트 전극 형성용 마스크를 이용한 식각 공정으로 게이트 전극(22)을 형성한다. 이후, 각 게이트 전극(12) 양측부에 스페이서(23)를 형성한다. 다음에, 전체 구조 상부에 패드 폴리실리콘층(24) 및 제 1 반사 방지막(25)을 순차적으로 형성한다. 이후, 두 게이트 전극(22) 간의 노출된 반도체 기판(21) 및 두 게이트 전극(22) 상의 일부에만 패드 폴리실리콘층(24)이 남아 있도록 하는 마스크를 이용한 식각 공정으로 제 1 반사 방지막(25) 및 패드 폴리실리콘층(24)을 제거한다. 다음에, 전체 구조 상부에 유전체막(26)을 형성한다.As shown in FIG. 2A, the first polysilicon layer is deposited on the semiconductor substrate 21 on which the lower structure is formed, and then the gate electrode 22 is formed by an etching process using a mask for forming a gate electrode. Thereafter, spacers 23 are formed at both sides of each gate electrode 12. Next, the pad polysilicon layer 24 and the first antireflection film 25 are sequentially formed on the entire structure. Subsequently, the first anti-reflection film 25 may be formed by an etching process using a mask in which the pad polysilicon layer 24 remains only on the exposed semiconductor substrate 21 between the two gate electrodes 22 and the two gate electrodes 22. And pad polysilicon layer 24 is removed. Next, a dielectric film 26 is formed over the entire structure.
도 2(b)에 도시된 바와 같이, 콘택 홀 형성용 포토레지스트(27)를 전체 구조 상부에 도포한 후 식각 공정을 실시하여 콘택 홀을 오픈한다. 이때, 패드 폴리실리콘층(24) 상부의 제 1 반사 방지막(25)을 완전히 제거하기 위하여 콘택 홀 오픈용 포토레지스트(27)를 제거하지 않은 상태에서 이온 주입 공정을 실시한다.As shown in FIG. 2 (b), the contact hole forming photoresist 27 is coated on the entire structure, followed by an etching process to open the contact hole. In this case, in order to completely remove the first anti-reflection film 25 on the pad polysilicon layer 24, an ion implantation process is performed without removing the contact hole open photoresist 27.
이 이온 주입 공정은 100KeV 이하의 에너지로 31P, As, BF2,B 및 Ar 이온 중 어느 하나를 이용하여 실시하며, 주입 농도는 5.0×1015Ion/㎠가 되도록 한다.This ion implantation process is performed using any one of 31P, As, BF 2, B and Ar ions with an energy of 100KeV or less , and the implantation concentration is 5.0 × 10 15 Ion / cm 2.
도 2(c)에 도시된 바와 같이, 포토레지스트(27)를 제거한 후 세정 공정을 실시한다. 여기에서, 세정 공정은 B(H2SO4: H2Os), N(NH4F : H2O2) 및 N(NH4OH : H2O2: H2O) 용액 중 어느 하나를 이용하여 실시한다. 세정 공정이 완료되면, 전체 구조 상부에 티타늄(Ti)막(28)을 형성하고 급속 열 어닐링(Rapid Thermal Annealing; RTA) 공정을 실시한다. 이에 의해 콘택 홀 저부의 제 1 반사 방지막(25)이 잔류하는 부분에 티타늄 실리사이드층(TiSi2; A)이 형성된다. 여기에서, 티타늄막(28)은 물리적 기상 증착(Physical Vapor Deposition; PVD) 방법 또는 화학적 기상 증착(Chemical Vapor Deposition; CVD) QDKQJQDMF 이용하여 1000Å 이하의 두께로 형성하며, RTA 공정은 650℃에서 10초 이상 실시한다.As shown in FIG. 2 (c), the cleaning process is performed after removing the photoresist 27. Here, the washing step is any one of B (H 2 SO 4 : H 2 Os), N (NH 4 F: H 2 O 2 ) and N (NH 4 OH: H 2 O 2 : H 2 O) solution Use it. After the cleaning process is completed, a titanium (Ti) film 28 is formed on the entire structure, and a rapid thermal annealing (RTA) process is performed. As a result, a titanium silicide layer (TiSi 2 ; A) is formed in a portion where the first anti-reflection film 25 at the bottom of the contact hole remains. Here, the titanium film 28 is formed to a thickness of 1000 Å or less by using a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) QDKQJQDMF, and the RTA process is performed at 650 ° C for 10 seconds. Do the above.
이와 같이 진행한 후, 전체 구조 상부에 제 2 폴리실리콘층(29) 및 제 2 반사 방지막(30)을 형성하고, 비트라인 형성용 마스크를 이용한 식각 공정으로 제 2 반사 방지막(30), 제 2 폴리실리콘층(29) 및 유전체막(26) 상부의 티타늄막(28)을 순차적으로 제거하여 비트라인을 형성한다.After proceeding in this manner, the second polysilicon layer 29 and the second anti-reflection film 30 are formed on the entire structure, and the second anti-reflection film 30 and the second are etched by an etching process using a mask for forming a bit line. The bit line is formed by sequentially removing the polysilicon layer 29 and the titanium film 28 over the dielectric film 26.
도 3은 본 발명의 제 2 실시예에 따른 반도체 소자의 콘택 홀 형성 방법에 관한 것으로, 저장 노드용 콘택 홀을 형성하는 경우의 예이다.3 illustrates a method of forming a contact hole in a semiconductor device according to a second exemplary embodiment of the present invention, and is an example of forming a contact hole for a storage node.
게이트 전극(32), 패드 폴리실리콘층(33), 반사 방지막(34) 및 비트라인(35) 등이 형성된 반도체 기판(31) 상에 유전체막(36)을 형성한다. 이후, 콘택 홀 형성용 포토레지스트를 이용한 식각 공정으로 패드 폴리실리콘층(33) 상부를 일부 노출시켜 저장 노드 형성용 콘택 홀을 형성한다. 이때, 패드 폴리실리콘층(33) 상부의 반사 방지막(34)을 완전히 제거하기 위하여, 콘택 홀 오픈용 포토레지스트를 제거하지 않은 상태에서 이온 주입 공정을 실시한다.The dielectric film 36 is formed on the semiconductor substrate 31 on which the gate electrode 32, the pad polysilicon layer 33, the antireflection film 34, the bit line 35, and the like are formed. Thereafter, the upper portion of the pad polysilicon layer 33 is partially exposed by an etching process using a photoresist for forming contact holes to form a storage node forming contact hole. At this time, in order to completely remove the anti-reflection film 34 on the pad polysilicon layer 33, an ion implantation process is performed without removing the contact hole open photoresist.
이 이온 주입 공정은 100KeV 이하의 에너지로 31P, As, BF2및 Ar 이온 중 어느 하나를 이용하여 실시하며, 주입 농도는 5.0×1015Ion/㎠가 되도록 한다.This ion implantation process is performed using any one of 31P, As, BF 2 and Ar ions with energy of 100KeV or less, and the implantation concentration is 5.0 × 10 15 Ion / cm 2.
다음에, 포토레지스트를 제거한 후 세정 공정을 실시한다. 여기에서, 세정 공정은 B(H2SO4: H2Os), O(NH4F : H2O2) 및 N(NH4OH : H2O2: H2O) 용액 중 어느 하나를 이용하여 실시한다. 세정 공정이 완료되면, 전체 구조 상부에 티타늄(Ti)막(37)을 형성하고 급속 열 어닐링(Rapid Thermal Annealing; RTA) 공정을 실시한다. 이에 의해 콘택 홀 저부의 반사 방지막(34)이 잔류하는 부분에 티타늄 실리사이드층(TiSi2; B)이 형성된다. 여기에서, 티타늄막(34)은 물리적 기상 증착(Physical Vapor Deposition; PVD) 방법 또는 화학적 기상 증착(Chemical Vapor Deposition; CVD) 방법을 이용하여 1000Å 이하의 두께로 형성하며, RTA 공정은 650℃에서 10초 이상 실시한다.Next, after the photoresist is removed, a washing step is performed. Here, the cleaning process is performed by using any one of B (H 2 SO 4 : H 2 Os), O (NH 4 F: H 2 O 2 ), and N (NH 4 OH: H 2 O 2 : H 2 O) solution. Use it. When the cleaning process is completed, a titanium (Ti) film 37 is formed on the entire structure, and a rapid thermal annealing (RTA) process is performed. As a result, a titanium silicide layer (TiSi 2 ; B) is formed in the portion where the anti-reflection film 34 at the bottom of the contact hole remains. Here, the titanium film 34 is formed to a thickness of 1000 Å or less by using a physical vapor deposition (PVD) method or a chemical vapor deposition (CVD) method, and the RTA process is performed at 10 ° C at 650 ° C. Do this for more than a second.
이와 같이 진행한 후, 전체 구조 상부에 폴리실리콘층(38)을 형성하고 패터닝하여 저장 노드를 형성한다.After proceeding as described above, the polysilicon layer 38 is formed and patterned on the entire structure to form a storage node.
이와 같이, 콘택 홀 오픈 공정시 패드 폴리실리콘층(24, 33) 상부에 잔류하는 반사 방지막(25, 34)을 티타늄 실리사이드화하므로써, 콘택 홀을 완전히 오픈시킬 수 있음은 물론, 콘택 저항을 감소시킬 수 있다.In this way, the titanium anti-reflective layers 25 and 34 remaining on the pad polysilicon layers 24 and 33 during the contact hole opening process may be used to completely open the contact holes and to reduce contact resistance. Can be.
상술한 바와 같이, 본 발명에 따르면 비트라인 및 저장 노드용 콘택 홀 형성시 콘택 홀을 완전히 오픈시킬 수 있고 콘택 저항을 감소시킬 수 있다. 또한, 콘택 홀 오픈 후의 이온 주입 공정에 의해 소오스 및 드레인 콘택 지역의 저항 또한 감소시킬 수 있으며, 이에 따라 소자의 리프레쉬 특성이 개선되어 소자의 신뢰성 및 수율을 향상시킬 수 있는 탁월한 효과가 있다.As described above, according to the present invention, the contact hole can be completely opened and the contact resistance can be reduced when forming the contact hole for the bit line and the storage node. In addition, the resistance of the source and drain contact regions may also be reduced by the ion implantation process after the contact hole is opened, thereby improving the refresh characteristics of the device, thereby improving the reliability and yield of the device.
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