KR100280480B1 - Multilevel Cell Lead Circuit of Flash Epirom - Google Patents

Abstract

The present invention relates to a multi-level cell read circuit of a flash Y pyrom, and in the related art, one cell has a reference cell in each cell sensing unit, so that the area of the sensing circuit to be implemented within a limited area becomes too large. Accordingly, the present invention provides a flash cell unit including a plurality of flash cells in which data is read or written; A column decoder which receives the wire dress signal and decodes the wire dress signal and outputs the bit line selection signal accordingly; A current generator for generating a starting current when a power supply voltage is applied to a gate of a predetermined flash cell of the flash cell unit; The detection signal is rapidly compared with the predetermined reference data selected by the clock signal which is enabled by the starting current of the current generating unit and is programmed at various levels of levels to the predetermined flash cell of the flash cell unit. A plurality of cell detection units for outputting the data; An output control unit which receives a clock signal and is electrically connected thereto and controls an output of comparison data of the corresponding cell detection unit; The sensing unit receives the data output by the output control unit and latches it, thereby enabling level sensing by multiple cell sensing units at the same time. Since a plurality of reference cells are connected to one cell sensing unit, the area occupied by the sensing circuit is reduced. It is reduced by dividing by the number of reference cells connected to one cell detector.

Description

Multilevel Cell Lead Circuit of Flash Epirom

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read circuit of a multilevel cell of a flash epirom, and is particularly accurate since a single flash memory cell has two or more states in a multilevel cell employed in a flash memory for storing a large amount of data. The present invention relates to a read circuit of a multilevel cell of a flash Y pyrom which can quickly and quickly determine each state.

FIG. 1 is a circuit diagram showing a configuration of a read circuit for a multilevel cell of a conventional flash Y pyrom. As shown therein, a flash cell unit 10 including a plurality of flash cells FC to which data is read or written; A column decoder 11 for receiving a wire dress signal and decoding the wire dress signal to select a predetermined flash cell FC of the flash cell unit 10 connected to the bit line; A current generator 12 generating a starting current when a power supply voltage is applied to a gate of a predetermined flash cell FC of the flash cell unit 10; First and second enable by the starting current of the current generating unit 12 compares the data programmed in the predetermined flash cell (FC) of the flash cell unit 10 with the predetermined reference data and outputs a detection signal accordingly; 2 cell detecting units 13-1 and 13-2; First and second cell detectors 13-1 and 13-2 receiving the starting current of the current generator 12 and sensing data of different reference cells 16 and 17 accordingly. Wow; First and second output controllers which receive the clock signals CLK1 and CLK2 and are electrically connected accordingly to output the data of the first and second cell detectors 13-1 and 13-2. (18), (19); The first and second latches 14 and 15 receive data from the output controllers 18 and 19 and latch the data and output the latched signals to sense amplifiers (not shown). .

The current generator 12 is connected to the gate and the drain of the PMOS transistor MP1 to which the power supply voltage Vcc is applied on the source side and the decoding signal of the column decoder 11 is applied on the drain side. The signal is configured to be generated.

The first cell sensing unit 13-1 has an MOS transistor MN3 at the drain of the PMOS transistor MP2 to which the power supply voltage Vcc is applied to the source and the signal of the current generator 12 is applied to the gate. A drain of the NMOS transistor MN3 is connected to a source of the NMOS transistor MN2 to which a power supply voltage Vcc is applied to a drain, and a gate of the NMOS transistor MN3 is connected to a source of the NMOS transistor MN3. The gate of the MOS transistor MN2 is connected in common, and the inverter INV1 is connected in a reverse direction between the common connection point and the source common connection point of the MOS transistor MN2 and the NMOS transistor MN3, and the MOS transistor The clock signal CLK2 is applied to the gate at the source common connection point of the MN2 and the NMOS transistor MN3, and the drain of the NMOS transistor MN4 having the reference cell 16 connected to the source is connected.

The first output control unit 18 is composed of an NMOS transistor MN8 which is electrically connected to the gate by receiving the clock signal CLK1 and outputs the data applied to the drain side to the source side. do.

First, data is programmed by applying a power supply voltage Vcc to a gate of a predetermined flash cell FC of the flash cell unit 10. At this time, the column decoder 11 randomly selects the flash cell unit 10 by a predetermined address signal. The flash cell FC is decoded and selected, whereby the PMOS transistor MP1 of the current generating unit 12 is turned on to generate a predetermined starting current.

Thereafter, the first and second cell detection units 13-1 and 13-2 are enabled by the starting current of the current generation unit 12, so that the data of the reference cells 16 and 17 can be obtained. Detect and output

Here, the operation of the first cell detection unit 13-1 will be described as an example.

The sensing data of the first cell detector 13-1 is applied to the first latch unit 14 through the NMOS transistor MN7 turned on by the corresponding clock signal CLK1, thereby providing a first latch. The unit 14 latches the sensed data coming through the NMOS transistor MN7 and applies the latched data to the first sense amplifier (not shown) for sensing.

At this time, when the operation of the first cell detection unit 13-1 is described in a circuit, the current of the first PMOS transistor MP1 is limited by the flash cell FC selected by the column decoder 11. That is, a bias voltage corresponding to a current flowing through the first PMOS transistor MP1 is generated.

Here, the voltage Va flowing through the first node NodeA is applied to the gate of the second PMOS transistor MP2 of the first cell sensing unit 13-1 by current mirroring, and the first cell sensing unit is applied. In 13-1, the current is determined by the reference cell 16 so that the current of the reference cell 16 also flows in the second PMOS transistor MP2.

Accordingly, since the voltages flowing through the source and the gate of the second PMOS transistor MP2 are already determined, the voltage Vb flowing through the second node NodeB in order for the reference current to flow through the second PMOS transistor MP2. ) Should be adjusted.

If the current flowing through the first node NodeA is greater than the reference current, the second PMOS transistor MP2 must flow a current smaller than the current flowing through the first node NodeA, so that the voltage of the second node NodeB Vb) must be high to make the drain-source of the second PMOS transistor MP2 small.

Here, when only a slight rise condition occurs due to an operating region condition on the parameter of the second PMOS transistor MP2, the voltage Vb of the second node NodeB is raised to a power supply voltage level, so that high-potential data is sensed. Will be.

On the contrary, when the current flowing through the first node NodeA is smaller than the reference current, the drain-source of the second PMOS transistor MP2 must be increased, so that the voltage of the second node NodeB is lowered. The voltage Vc of the NodeC is also lowered so that the current of the NMOS transistor MN2 flows into the reference cell 16 at the same time.

Therefore, low potential data is sensed.

That is, when data sensing starts, the current of the flash cell FC mirrored through the first PMOS transistor MP1 is reflected to the cell sensing units 13-1 and 13-2 so that the sensing operation occurs. The sensing result is reflected on a corresponding sense amplifier (not shown) and finally decoded so that the program state of the flash cell FC is read.

However, the conventional apparatus operating as described above has a problem that the area of the sensing circuit that is to be implemented within a limited area is too large by having one reference cell in each cell sensing unit.

Accordingly, the present invention devised in view of the above-described problems provides a multilevel cell read circuit of a flash Y pyrom which allows a plurality of reference cells to be connected to one cell detection unit so that level sensing can be simultaneously performed by several cell detection units. Has its purpose.

1 is a circuit diagram showing a configuration of a read circuit of a multilevel cell of a conventional flash EPIROM.

Fig. 2 is a block diagram showing the configuration of the read circuit of the multilevel cell of the flash easy pyrom of the present invention.

* Description of the symbols for the main parts of the drawings *

10: flash cell part 11: column decoder

12: current generator 20-1, 20-2: cell detection unit

21, 22: Latch part 16, 17, 23, 24: Reference cell

25, 26: output control unit

The above object includes a flash cell unit including a plurality of flash cells in which data is read or written; A column decoder which receives the wire dress signal and decodes the wire dress signal and outputs the bit line selection signal accordingly; A current generator for generating a starting current when a power supply voltage is applied to a gate of a predetermined flash cell of the flash cell unit; The detection signal is rapidly compared with the predetermined reference data selected by the clock signal which is enabled by the starting current of the current generating unit and is programmed at various levels of levels to the predetermined flash cell of the flash cell unit. A plurality of cell detection units for outputting the data; An output control unit which receives a clock signal and is electrically connected thereto and controls an output of comparison data of the corresponding cell detection unit; And a latch unit configured to receive the data output by the output control unit and latch it.

Hereinafter, the operation and effect of the multi-level cell read circuit of the memory according to the present invention will be described with reference to the accompanying drawings.

Fig. 2 is a circuit diagram showing the configuration of a multilevel cell read circuit of the memory of the present invention, which includes a flash cell unit 10 including a plurality of flash cells to which data is read or written; A column decoder 11 for receiving the wire dress signal and decoding the wire dress signal and outputting the bit line selection signal accordingly; A current generator 12 generating a starting current when a power supply voltage Vcc is applied to a gate of a predetermined flash cell of the flash cell unit 10; By clock signals CLK1 and CLK2 which are enabled by the starting current of the current generating unit 12 and sequentially input to data programmed at various levels into predetermined flash cells of the flash cell unit 10. First and second cell detection units 20-1 and 20-2 for comparing the selected predetermined reference data with each other and quickly outputting a detection signal according thereto; First and second output controllers 25 for receiving the clock signals CLK1 and CLK2 and conducting them accordingly to control output of the comparison data of the corresponding cell sensing units 20-1 and 20-2. , 26; The first and second latch units 21 and 22 receive the data output by the output control units 25 and 26 and latch the same.

The first cell sensing unit 20-1 has an MOS transistor MN3 at a drain of the PMOS transistor MP2, to which a power supply voltage Vcc is applied to a source and a signal of the current generator 12 is applied to a gate. A drain of the NMOS transistor MN3 is connected to a source of the NMOS transistor MN2 to which a power supply voltage Vcc is applied to a drain, and a gate of the NMOS transistor MN3 is connected to a source of the NMOS transistor MN3. The gate of the MOS transistor MN2 is connected in common, and the inverter INV1 is connected in a reverse direction between the common connection point and the source common connection point of the MOS transistor MN2 and the NMOS transistor MN3, and the MOS transistor EnMOS transistors MN10 and (CN1), in which clock signals CLK1 and CLK2 are applied to the gate and the reference cells 23 and 16 are connected to the source at the source common connection point of MN2) and NMOS transistor MN3. The common connection point of the drain of MN4) is connected and comprised.

The first output control unit 25 receives a sensing signal of the first cell detecting unit 20-1 on the drain side and is connected to the source side by the first clock signal CLK1 to apply the first enMOS transistor ( MN8); The sensing signal of the first cell detecting unit 20-1 is input to the drain side, and is configured as a second NMOS transistor MN12 that is connected by the second clock signal CLK2 and applied to the source side.

The latch unit 21 constitutes a latch formed of inverters INV3 and INV4 connected in parallel in the opposite directions, as many as the number of reference cells 23 and 16 of the cell sensing unit 20-1. The operation of the present invention thus constructed will be described.

First, the general operation is the same as in the prior art.

That is, data is programmed by applying a power supply voltage Vcc to a gate of a predetermined flash cell FC of the flash cell unit 10, and the column decoder 11 performs arbitrary flash cell FC of the flash cell unit 10. ) Is decoded and selected, whereby the PMOS transistor MP1 of the current generating unit 12 is turned on to generate a predetermined starting current.

Thereafter, the first and second cell detection units 20-1 and 20-2 are enabled by the starting current of the current generator 12, and the reference cells 16 corresponding to the clock signals are corresponding thereto. ), (17), (23), (24) detects and outputs the data.

Here, the operation of the first cell detection unit 20-1 will be described as an example. The detection data of the first cell detection unit 20-1 is sequentially performed by the corresponding clock signals CLK1 and CLK2. The first latch unit 21 is applied to the first latch unit 21 through the NMOS transistors MN4 and MN10 that are turned on, and thus the first latch unit 21 senses the inputs through the NMOS transistors MN4 and MN10. The data is latched and the latched data is applied to a first sense amplifier (not shown) for sensing.

In this case, when the operation of the first cell detecting unit 20-1 is described in a circuit, the current of the first PMOS transistor MP1 is limited by the flash cell FC selected by the column decoder 11. That is, a bias voltage corresponding to a current flowing through the first PMOS transistor MP1 is generated.

Here, voltage Va flowing through the first node NodeA is applied to the gate of the second PMOS transistor MP2 of the first cell sensing unit 20-1 by current mirroring, and the first cell sensing is performed. In the unit 20-1, current is determined by the reference cells 23 and 16 so that the current of the reference cells 23 and 16 also flows in the second PMOS transistor MP2.

Accordingly, since the voltages flowing through the source and the gate of the second PMOS transistor MP2 are already determined, the voltage Vb flowing through the second node NodeB in order for the reference current to flow through the second PMOS transistor MP2. ) Should be adjusted.

If the current flowing through the first node NodeA is greater than the reference current, the second PMOS transistor MP2 must flow a current smaller than the current flowing through the first node NodeA, so that the voltage of the second node NodeB Vb) must be high to make the drain-source of the second PMOS transistor MP2 small.

Here, when only a slight rise condition occurs due to an operating region condition on the parameter of the second PMOS transistor MP2, the voltage Vb of the second node NodeB is raised to a power supply voltage level, so that high-potential data is sensed. Will be.

On the contrary, when the current flowing through the first node NodeA is smaller than the reference current, the drain-source of the second PMOS transistor MP2 must be increased, so that the voltage of the second node NodeB is lowered. The voltage Vc of the NodeC is also lowered so that the current of the NMOS transistor MN2 flows into the reference cells 23 and 16 at the same time.

Therefore, low potential data is sensed.

That is, when data sensing starts, the current of the flash cell FC mirrored through the first PMOS transistor MP1 is reflected to the cell sensing units 20-1 and 20-2 so that the sensing operation occurs. The sensing result is reflected on a corresponding sense amplifier (not shown) and finally decoded so that the program state of the flash cell FC is read.

As described in detail above, the present invention enables level sensing with multiple cell sensing units at the same time, and since multiple reference cells are connected to one cell sensing unit, the area occupied by the sensing circuit is connected to one cell sensing unit. Divided by the number is effective.

Claims (4)

A flash cell unit comprising a plurality of flash cells to which data is read or written; A column decoder which receives the wire dress signal and decodes the wire dress signal and outputs the bit line selection signal accordingly; A current generator for generating a starting current when a power supply voltage is applied to a gate of a predetermined flash cell of the flash cell unit; The detection signal is rapidly compared with the predetermined reference data selected by the clock signal which is enabled by the starting current of the current generating unit and is programmed at various levels of levels to the predetermined flash cell of the flash cell unit. A plurality of cell detection units for outputting the data; An output control unit which receives a clock signal and is electrically connected thereto and controls an output of comparison data of the corresponding cell detection unit; And a latch unit for receiving the data output by the output control unit and latching the data outputted by the output control unit. The method of claim 1, wherein the cell sensing unit is connected to the drain of the first NMOS transistor to the drain of the first PMOS transistor to which the power supply voltage is applied to the source and the signal of the current generator is applied to the gate, the first NMOS transistor A source of a second NMOS transistor, to which a power supply voltage is applied to a drain, is connected to a source of N, and gates of the first and second NMOS transistors are commonly connected to each other so that the common connection point and the first and second NMOS transistors Inverters are connected in a reverse direction between the source common connection points, and clock signals are sequentially applied to the gates of the source common connection points of the first and second NMOS transistors, respectively. A multilevel cell read circuit of a flash Y pyrom, which is configured by being connected to a drain of the flash. 2. The flash level controller of claim 1, wherein the output controller comprises a predetermined NMOS transistor which receives the sensing signal of the cell sensing unit to the drain side and is connected to the source side by a predetermined clock signal. Lead circuit. The flash level controller read circuit of claim 1, wherein the latch unit comprises a latch including first and second inverters connected in parallel in opposite directions to correspond to the reference cells of the cell sensing unit.