KR100273345B1 - Digital demodulation circuit of orthogonal amplitude modulation signals - Google Patents

Abstract

PURPOSE: A digital demodulation circuit of an orthogonal amplitude demodulation signal is provided to simplify a structure by sampling an intermediate frequency by means of a clock synchronized with a phase of a carrier wave. CONSTITUTION: A same phase sampler(10) and an orthogonal phase sampler(20) sample an intermediate frequency by means of a clock synchronized with a phase of a carrier wave through a demodulator. A re-sampler(30) samples a base band signal of a carrier wave rate by means of a fixed speed by receiving a clock signal synchronized with a phase of a symbol and a clock signal synchronized with a phase of a carrier wave. At this time, the fixed speed is a multiple of the symbol rate. An RC filter(40) decreases an interference between symbols by receiving an output of the re-sampler(30). A timing recovering part(50) generates the clock signal synchronized with the phase of the carrier wave by presuming the phase of the carrier wave, and supplies the clock signal with the re-sampler(30). A channel equalizer(60) equalizes a channel of an output signal of the timing recovering part(50). A decider(70) decides a symbol level. A carrier phase recovering part(80) generates a clock signal synchronized with the phase of the carrier wave by receiving outputs of the channel equalizer(60) and the decider(70). At this time, the clock signal synchronized with the phase of the carrier wave has a fixed phase difference.

Description

Digital Demodulation Circuit for Quadrature Amplitude Modulation Signal

1 is a demodulation block diagram according to a conventional analog method.

2 is a digital demodulation block diagram of an orthogonal amplitude modulated signal by the even invention sampling method.

3A to 3C are clock timing diagrams synchronized with a carrier and a carrier phase.

(A) of FIG. 4 is a symbol waveform diagram.

(B) Output waveform diagram of the timing recovery unit in FIG.

5 is a block diagram of one embodiment of a resampler in FIG.

6A to 6J are operational timing diagrams of respective parts of FIG.

* Explanation of symbols for main parts of the drawings

10: statue sampler 20: orthogonal sampler

30: resampler 40: RC filter

50: timing recovery unit 60: channel equalizer

70: determiner 80: carrier phase recovery unit

The present invention relates to a digital demodulation technique, and in particular, overcomes the problems of the conventional analog method of extracting baseband signals using mixers, that is, harmonic components of demodulated carriers, phase errors of ideal phases, and difficulties in hardware implementation. The present invention relates to a digital demodulation circuit of an orthogonal amplitude modulated signal suitable for easily implementing an ASIC as a simple digital system.

1 is a demodulation block diagram according to a conventional analog method, as shown therein, an in-phase mixer 1A that multiplies an output signal of an intermediate frequency input signal S _mt and Vsio 3 with the intermediate frequency input. The quadrature mixer 1B multiplies the signal S _mt and the output signal of the V.O.3 delayed by 90 ° through the phase shifter 2 and the output signals of the mixers 1A and 1B, respectively. First and second low pass filters 4A and 4B which remove the double frequency components of the carrier and output baseband signals I and Q in phase and quadrature and are output from the clock signal generator 7. First and second A / D converters 5A and 5B for converting the analog output signals of the first and second low pass filters 4A and 4B into digital signals, respectively, First and second RC filters 6A and 6B for receiving the output signals of the 1,2A / D converters 5A and 5B, respectively, to reduce intersymbol interference, and the first and second RC filters 6A, Supply the output signal of 6B A channel equalizer 8 for removing distortion on the sub-channel, and a carrier power recovery unit for receiving the output signal of the channel equalizer 8 and restoring the phase of the carrier and outputting the phase to the VIO 3; 8A) and a determiner 9 which receives the output signal of the channel equalizer 8 and recovers the original information data DATA that the transmitter intends to send. The operation thereof is as follows.

The intermediate frequency input, i.e., S _m (t), is input to the in-phase mixer 1A and the quadrature mixer 1B, respectively. On the other hand, the output waveform of VSO 3, the voltage controlled local oscillator, is the in-phase mixer ( It is supplied as it is to 1A), and it is supplied to the quadrature mixer 1B in the state which the phase was delayed by -90 degrees through the ideal phase 2. Accordingly, the mixers 1A and 1B each perform an arithmetic function of multiplying two inputs, and the results are as follows.

I = Sm (t) * COS (ω _c t)

= Im _c * Ucos ² (ω _c t) -I _ms * U (t) * sin (ω _c t) * cos (ω _c t)

= 1/2 * I _mc * U (t) + 1/2 * I _mc * U (t) * cos (2ω _c t)

1/2 * I _ms * U (t) * sin (2ω _c t)

Q = -Sm (t) * sin (ω _c t)

=-I _mc * U (t) * (ω _c t) * sin (ω _c t) + I _ma * U (t) * sin ² (ω _c t)

= 1/2 * I _ms * U (t)-1/2 * I _mc * U (t) * cos (2ω _c t)

1/2 * I _ms * U (t) * sin (2ω _c t)

As these two results pass through the first and second low pass filters 4A and 4B, respectively, the double frequency component of the carrier is removed and only the baseband signals I and Q in phase and orthogonality remain. . The baseband signal in phase and orthogonal to each other is converted into a digital signal by the output clock signal of the clock signal generator 7 in the first, second and second A / D converters 5A and 5B. The digital baseband signal in phase and orthogonality passes through the first and second RC filters 6A and 6B for reducing the intersymbol interference and the channel equalizer 8 for removing distortion on the channel sequentially, and then the determinant 9 ) Is restored to the data (DATA) that the sender wanted to send.

The output of the channel equalizer 8 is also input to the carrier phase recovery unit 8A which controls the VIO 3 to output a sine wave whose phase is synchronized with the carrier. The outputs of the first and second RC filters 6A and 6B are used to generate a clock signal generator so that the clock signal input to the first and second A / D converters 5A and 5B is synchronized with the symbol phase of the baseband signal. It is also entered in 7).

However, in the conventional demodulation system, the harmonic component of the duplicated carrier, the phase error of the phase shifter, and the difficulty of hardware implementation are accompanied. Simple analogization of the analog method requires a means of compensating the phase by sampling an intermediate frequency signal with a clock independent of the phase of the carrier.The down converter includes a sampler, a complex multiplier, a phase compensation function, and a low pass filter. There was a problem of getting complicated.

In order to solve the above problems, the present invention has been devised to overcome the problems of the analog method using a conventional mixer by sampling and demodulating an intermediate frequency signal with a clock synchronized with a carrier phase. It demonstrates in detail by one figure.

2 is a block diagram of a digital demodulation circuit of an orthogonal amplitude modulated signal according to the present invention. As shown in FIG. 2, an intermediate frequency signal S _{m is obtained} by using a demodulator for demodulating a signal simultaneously modulated with amplitude and phase. The in phase sampler 10 and the quadrature sampler 20 each sampling (t) to a clock synchronized with the phase of the carrier, the clock signal synchronized with the phase of the symbol, and the clock signal synchronized with the carrier phase are input. A resampler 30 for resampling the baseband signal of the carrier rate at a rate that is a multiple of the symbol rate, and an RC filter 40 for receiving an output signal of the resampler 30 and filtering to reduce interference between symbols And a timing recovery unit 50 for estimating the phase of the carrier with respect to the output signal of the RC filter 40, generating a clock signal synchronized with the phase of the carrier, and supplying the clock signal to the resampler 30. tie A channel equalizer 60 for equalizing a channel with respect to the output signal of the recovery unit 50, and a determiner for determining a symbol level estimated to be transmitted by the transmitting end by receiving the output signal of the channel equalizer 60. (70) and the outputs of the channel equalizer (60) and the determiner (70) are synchronized with the phase of the carrier and generate a clock signal having a predetermined phase difference, respectively, the samplers (10) and (20). It is composed of a carrier phase recovery unit 50 to supply to (30), and will be described in detail with reference to FIGS. 3 to 6 attached to the operation and effect of the present invention configured as described above.

Quadrature amplitude modulation is a method of simultaneously modulating the amplitude and phase of a carrier wave and can be viewed as a combination of pulse amplitude modulation (PAM) and pulse phase modulation (PSX). The M-level quadrature amplitude modulation signal S _m (t) is expressed as follows.

Sm (t) = I _mc * U (t) * cos (ω _c t)-I _ms * sin (ω _c t) m = 1,2, ... M

Where I _mc * U (t) and I _ms * U (t) are baseband signals in phase and quadrature respectively, and I _mc and I _mc are symbol levels having a constant value for one symbol period, and U (t) is Pulse for transmitting a signal with a limited bandwidth, ω _c (= 2πf _c ) is the angular frequency of the carrier wave. The quadrature amplitude modulated signal can be configured using two independent pulse amplitude modulated signals, and demodulation can be implemented in the same way.

In the digital demodulation process of the quadrature amplitude modulated signal by the sampling method, as shown in FIG. 3, the received quadrature amplitude modulated signal S _m (t) is simultaneously supplied to the in-phase sampler 10 and the quadrature sampler 20. The outputs of the in-phase sampler 10 and the quadrature sampler 20 are all supplied to the resampler 30, and the resampler 30 supplies a clock signal synchronized with the phase of a symbol and a clock signal synchronized with a carrier phase. As an input, the baseband signal of the carrier rate is resampled at a rate that is a multiple of the symbol rate.

The output of the resampler 30 is input to the determiner 70 through the channel equalizer 60 after the filtering operation for reducing the interference between symbols in the RC filter 40 is performed.

In addition, the output of the RC filter 40 is also input to the timing recovery unit 50 to output the clock φ ₃ synchronized with the symbol phase, and FIG. 4 shows the timing of the clock synchronized with the symbol and the symbol phase. .

The carrier phase recovery unit 80 uses the output of the channel equalizer 60 and the output of the determiner 70 as inputs to synchronize two clocks φ ₁ and φ ₂ synchronized with the phase of the carrier and having a phase difference of 1 / 2π. The timing diagram of the clocks synchronized with the carrier and the carrier phase is shown in FIG.

When the received quadrature amplitude modulated signal S _m (t) is input to the in-phase sampler 10 and sampled at ω _c t = 0,2π, 4π, ... by φ ₁ , only the baseband signal of the verb remains. When input to the quadrature sampler 20 and sampled at ω _c t = 3π / 2, 7π / 2, 11π / 2, ... by φ ₂ , only the orthogonal baseband signal remains.

S _m (2nπ) = I _m c * U (2nπ) where n = 1,2,3 .....

If sampling is performed according to the phase of the carrier as described above, baseband signals in phase and quadrature can be obtained at the carrier frequency ratio. The resampler 30 inputs a clock φ ₁ synchronized with the phase of the symbol, resamples the baseband signal of the carrier rate at a rate that is a multiple of the symbol rate, and resamples the baseband signal at an n-fold symbol rate. As the signal is supplied to the determiner 70 through the RC filter 40 to reduce the intersymbol interference or the channel equalizer 60 for channel equalization, the determinator 70 may be transmitted from the input signal from the input signal. The estimated symbol level is determined.

A timing recovery unit 50 such as an early rate gate for generating a clock synchronized with the phase of the symbol may operate by using the output of the RC filter 40 as an input, and generate a clock synchronized with the phase of the carrier wave. In the carrier phase recovery unit 80, such as the decision feedback loop, the determined symbol level is used.

The operation of the resampler 30 will be described in more detail with reference to FIGS. 5 and 6 below.

Baseband signals I ₁ and Q ₁ in phase and orthogonal to the carrier frequency rate are supplied to the data inputs of the latches 33 and 34. The clock signal φ ₁ synchronized with the carrier phase is supplied to the input terminal of the inverter 31 and the clock input terminal of the latch 32, and the clock signal φ ₃ synchronized with the symbol phase is supplied to the data of the latch 32. The input terminal and the clock input terminal of the latches 37 and 38 are respectively supplied.

The clock signal φ ₁ ′ of the inverter 31 is supplied to the clock input terminals of the latches 33 and 34, respectively, and the output signals φ ₃ ′ of the latch 32 are latched 35, 36. Are supplied to the clock input terminal of The output signal I ₂ of the latch 33 is supplied to the data input terminal of the latch 35, and the output signal Q ₂ of the latch 34 is supplied to the data input terminal of the latch 36, respectively. The output signal I ₃ of the latch 35 is supplied to the data input terminal of the latch 37, and the output signal Q ₃ of the latch 36 is supplied to the data input terminal of the latch 38, respectively.

The output signal I ₄ of the latch 37 and the output signal Q ₄ of the latch 38 become the final output of the resampler 30, and the timing of operation of each part of the resampler 30 is shown in FIG. Shown in

As described in detail above, the present invention has the effect of solving existing problems and ASIC with a simple configuration by sampling and demodulating an intermediate frequency signal with a clock synchronized with a phase of a carrier wave.

Claims (2)

An in-phase sampler 10 and a quadrature sampler 20 for sampling the intermediate frequency signal S _m (t) into a clock synchronized with the phase of the carrier using a demodulator for demodulating a signal simultaneously modulated in amplitude and phase; A resampler 30 for resampling a baseband signal of a carrier rate at a rate that is a multiple of a symbol rate by inputting a clock signal synchronized with a phase of a symbol and a clock signal synchronized with a carrier phase; and the resampler ( RC filter 40 for receiving an output signal of 30) and filtering to reduce interference between symbols, and a clock signal synchronized with the carrier phase by estimating the phase of the carrier with respect to the output signal of the RC filter 40. A timing recovery unit 50 for generating and supplying the same to the resampler 30, a channel equalizer 60 for equalizing a channel for an output signal of the timing recovery unit 50, and the channel equalizer Receive 60 output signals A clock signal having a predetermined phase difference, which is supplied with outputs of the channel equalizer 60 and the determiner 70, and is determined to determine a symbol level estimated to have been transmitted by the transmitting end, and synchronized with the phase of the carrier wave. And a carrier phase recovery unit (50) for generating and supplying the sampler to the respective samplers (10), (20), and (30). 4. The digital demodulation circuit of the quadrature amplitude modulated signal according to claim 1, wherein the resampler 30 comprises a latch driven by a clock synchronized with the phase of the carrier and a latch driven by a clock synchronized with the phase of the symbol. in.