KR950013059A

KR950013059A - Digital Demodulation Circuit for Quadrature Amplitude Modulation Signal

Info

Publication number: KR950013059A
Application number: KR1019930022805A
Authority: KR
Inventors: 김기현
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1993-10-29
Filing date: 1993-10-29
Publication date: 1995-05-17
Also published as: KR100273345B1

Abstract

본 발멸은 디지탈 복조기술에 관한 것으로, 종래의 복조시스템에 있어서는 복제된 반송파의 하모닉 성분, 이상기의 위상오차, 하드웨어 구현상의 어려움등이 수반되었다. 아날로그 방식의 단순한 디지탈화는 반송파의 위상과 무관한 클럭으로 중간주파수의 신호를 샘플링하는 까닭에 위상을 보상해주는 수단을 필요로 하고, 다운 컨버터에 샘플러, 콤플렉스 멀티플라이어, 위상 보정기능, 저역통과필터등의 복잡한 갖게 되는 문제점이 있었다. 따라서 본 발명은 중간주파수의 신호를 반송파의 위상과 동기된 클럭으로 샐플링하여 복조함으로써 기존의 제반 문제점을 해결하고 간단한 구성으로 ASIC화 할 수 있게 된다.This emanation relates to digital demodulation techniques, and in the conventional demodulation system, the harmonic component of the duplicated carrier, the phase error of the phase shifter, and the difficulty of hardware implementation were accompanied. Simple analogization of the analog method requires a means of compensating the phase by sampling an intermediate frequency signal with a clock independent of the phase of the carrier.The down converter includes a sampler, a complex multiplier, a phase compensation function, and a low pass filter. There was a problem of getting complicated. Therefore, the present invention solves all the conventional problems by demodulating the signal of the intermediate frequency by the clock synchronized with the phase of the carrier and can be ASIC with a simple configuration.

Description

Digital Demodulation Circuit for Quadrature Amplitude Modulation Signal

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 종래의 아날로그 방식에 의한 복조 블록도.1 is a demodulation block diagram according to a conventional analog method.

제2도는 본 발명 생플링 방식에 의한 직교 진폭변조신호의 디지탈 복조 블록도,2 is a digital demodulation block diagram of an orthogonal amplitude modulated signal according to the present plunging scheme;

제3도의 (가)내지 (다)는 반송파와 반송파 위상에 동기된 클럭 타이밍도,(A) to (c) of FIG. 3 show a clock timing diagram synchronized with a carrier and a carrier phase,

제4도의 (가)는 심볼 파형도, (나)는 제2도에서 타이밍 복구부의 출력파형도.4 is a symbol waveform diagram and (b) is an output waveform diagram of a timing recovery unit in FIG.

Claims

An in-phase sampler (10) and an orthogonal sampler (20) for sampling the intermediate frequency signal (Sm (t)) into a clock synchronized with the phase of the carrier wave by using a demodulator for demodulating a signal whose amplitude and phase are modulated simultaneously; A resampler 30 for resampling a baseband signal of a carrier rate at a rate that is a multiple of a symbol rate by inputting a clock signal synchronized with a phase of a symbol and a clock signal synchronized with a carrier phase; and the resampler 30 RC filter 40 for filtering to reduce the interference between symbols by receiving the output signal of the) and the clock signal synchronized with the phase of the carrier is generated by estimating the phase of the carrier with respect to the output signal of the RC filter 40 A timing recovery unit 50 for supplying the same to the resampler 30, a channel equalizer 60 for equalizing a channel for the output signal of the timing recovery unit 50, and the channel equalizer ( Supply 60 output signal A clock signal having a predetermined phase difference, which is supplied with outputs of the channel equalizer 60 and the determiner 70, and is determined to determine a symbol level estimated to have been transmitted by the transmitting end, and synchronized with the phase of the carrier wave. And a carrier phase recovery unit (50) for generating and supplying the sampler to the respective samplers (10), (20), and (30).

4. The digital demodulation circuit of the quadrature amplitude modulated signal according to claim 1, wherein the resampler 30 comprises a latch driven by a clock synchronized with the phase of the carrier and a latch driven by a clock synchronized with the phase of the symbol. in.

※ Note: The disclosure is based on the initial application.