KR100273305B1 - Method for fabricating isolation region of lateral double deffused mos transistor - Google Patents

Method for fabricating isolation region of lateral double deffused mos transistor Download PDF

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KR100273305B1
KR100273305B1 KR1019980019017A KR19980019017A KR100273305B1 KR 100273305 B1 KR100273305 B1 KR 100273305B1 KR 1019980019017 A KR1019980019017 A KR 1019980019017A KR 19980019017 A KR19980019017 A KR 19980019017A KR 100273305 B1 KR100273305 B1 KR 100273305B1
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oxide film
trench
region
high voltage
oxide layer
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KR1019980019017A
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Korean (ko)
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KR19990086157A (en
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이창재
이익희
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

PURPOSE: A method for forming a separative region of an LDMOS(Lateral Double diffused MOS) transistor is provided to improve reliability and productivity by simplifying a fabricating process of an isolation region. CONSTITUTION: A p-type epitaxial layer(23) is formed on an upper portion of an insulating oxide layer(22) of a semiconductor substrate(21). A high voltage transistor region is defined by forming a p-type well(24) and an n-type drift(25) on an upper portion of the p-type epitaxial layer(23). A trench structure is formed on an edge of high voltage transistor region. An oxide layer(26) is grown on a wall side of the trench structure. An oxide layer(27) and a polysilicon(28) are deposited on an upper portion of the semiconductor substrate(21). An oxide layer(29) is deposited on a surface of the whole structure. A photo-resist is coated thereon. The photo-resist is formed partially on the oxide layer(29) by performing an exposure process and a development process. The remaining oxide layer(29) is etched by performing a wet etch process.

Description

수평 확산형 모스트랜지스터의 분리영역 제조방법{METHOD FOR FABRICATING ISOLATION REGION OF LATERAL DOUBLE DEFFUSED MOS TRANSISTOR}METHODS FOR FABRICATING ISOLATION REGION OF LATERAL DOUBLE DEFFUSED MOS TRANSISTOR}

본 발명은 수평 확산형 모스트랜지스터(lateral double diffused MOS : LDMOS)의 분리영역 제조방법에 관한 것으로, 특히 분리영역의 제조공정을 단순화하여 신뢰성과 양산성을 향상시킬 수 있는 수평 확산형 모스트랜지스터의 분리영역 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a separation region of a lateral double diffused MOS transistor (LDMOS), and in particular, a separation of a horizontal diffusion type morph transistor which can improve reliability and mass productivity by simplifying the manufacturing process of the separation region. It relates to a method for producing a region.

최근들어 반도체소자의 집적도 향상과 그에 따른 설계기술이 점차로 발달하여 하나의 반도체 칩에 시스템을 구성하려는 시도가 진행되고 있다. 이와같은 시스템의 원칩(one-chip)화는 주로 시스템의 주요기능인 제어기, 메모리 및 기타 저전압에서 동작하는 회로를 하나의 칩으로 통합하는 기술로 발전되고 있다.In recent years, attempts have been made to construct a system on a single semiconductor chip due to the development of semiconductor devices and the development of design techniques. The one-chip development of such systems is being developed with the integration of the main functions of the system, controllers, memory and other low voltage circuits into one chip.

그러나, 시스템이 더욱 경량화 및 소형화되기 위해서는 시스템의 전원을 조절하는 입력단 및 출력단과 주요기능을 하는 회로가 하나의 칩에 통합되어야 하는데, 이와같은 입력단 및 출력단은 고전압이 인가되는 회로이므로, 일반적인 저전압 씨모스(CMOS)트랜지스터로는 구성이 불가능하여 고전압 전력 트랜지스터로 구성하였다. 즉, 고전압 브레이크다운(breakdown) 전압을 구현하기 위하여 두꺼운 에피택셜층을 갖는 반도체웨이퍼에 매몰된 접합층을 형성하였다.However, in order to make the system lighter and smaller, the input and output stages for controlling the power supply of the system and the circuits having the main functions must be integrated in a single chip. It is impossible to configure with CMOS transistor, so it is composed of high voltage power transistor. That is, in order to realize a high voltage breakdown voltage, a junction layer embedded in a semiconductor wafer having a thick epitaxial layer was formed.

상기한 바와같은 방식은 매몰된 접합층의 제조시 수천분의 확산시간이 요구되므로, 수율이 낮은 단점과, 고전압 트랜지스터와 저전압 씨모스트랜지스터간의 소자 분리영역을 접합분리(junction isolation) 또는 자기분리(self isolation)를 통해 형성하므로, 칩의 크기가 커지는 단점과, 일반 씨모스 트랜지스터의 제조공정과 통합하기 어려운 단점이 있었다.As described above, since the diffusion time of thousands of minutes is required in manufacturing the buried junction layer, the yield is low, and the junction isolation or magnetic separation between the high voltage transistor and the low voltage seam transistor is performed. Because of the self-isolation, the chip has a large size and it is difficult to integrate with a general CMOS transistor manufacturing process.

이를 개선하기 위하여 에스오아이(silicon-on-insulator : 이하, SOI) 기판을 사용하여 고전압 트랜지스터와 저전압 씨모스 트랜지스터를 하나의 칩으로 통합하는 파워 아이씨(power IC) 기술이 개발되었다.To improve this, a power IC technology has been developed that integrates a high voltage transistor and a low voltage CMOS transistor into one chip using a silicon-on-insulator (SOI) substrate.

상기한 바와같은 파워 아이씨 기술은 고전압 트랜지스터영역을 트렌치 분리(trench isolation) 방법을 통해 분리하고, 저전압 씨모스 트랜지스터영역을 로코스(LOCOS)분리 방법을 통해 분리하면서, 동시에 고전압 트랜지스터영역의 트렌치 분리영역의 상부에 열산화막을 형성하는데, 이 고전압 트랜지스터영역과 저전압 씨모스 트랜지스터영역을 연속적으로 연결하는 소자분리방법 및 필드(field)를 형성하는 기술이 핵심기술이다. 따라서, 매몰된 접합층이 요구되지 않으며, 소자 분리영역을 트렌치분리를 통해 형성하므로, 칩의 크기를 작게함과 아울러 수율을 향상시킬 수 있고, 또한 일반 씨모스 트랜지스터의 제조공정과 통합하기가 용이한 장점이 있다. 이와같은 종래 수평 확산형 모스트랜지스터의 분리영역 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.As described above, the power IC technology separates the high voltage transistor region through the trench isolation method, separates the low voltage CMOS transistor region through the LOCOS separation method, and simultaneously divides the high voltage transistor region into the trench isolation region of the high voltage transistor region. A thermal oxide film is formed on the upper side of the core, and a method of forming a device and a field for connecting the high voltage transistor region and the low voltage CMOS transistor region continuously are key technologies. Therefore, the buried junction layer is not required, and since the device isolation region is formed through the trench isolation, the chip size can be reduced and the yield can be improved, and it is easy to integrate with the general CMOS transistor manufacturing process. There is one advantage. Referring to the accompanying drawings, a method for manufacturing a separation region of a conventional horizontal diffusion type morph transistor is described in detail as follows.

도1a 내지 도1f는 종래 수평 확산형 모스트랜지스터의 분리영역 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 SOI구조의 반도체기판(1) 상부 절연산화막(2)의 상부에 피형 에피택셜층(3)을 형성한 후, 그 피형 에피택셜층(3) 상에 피형 웰(4)과 엔형 드리프트(5)를 형성하여 고전압 트랜지스터 영역을 정의하는 단계(도1a)와; 그 고전압 트랜지스터 영역의 가장자리에 내부의 절연산화막(2)이 노출되도록 트렌치구조를 형성하고, 그 트렌치구조의 벽면에 산화막(6)을 성장시키는 단계(도1b)와; 그 산화막(6)이 형성된 반도체기판(1)의 상부전면에 산화막(7) 및 폴리실리콘(8)을 증착한 후, 식각하여 트렌치구조를 완전히 채우는 단계(도1c)와; 상기 반도체기판(1)의 표면을 열산화시켜 산화막(9)을 형성한 후, 그 산화막(9)의 상부에 질화막(10)을 형성하고, 사진식각공정을 통해 패터닝하여 상기 트렌치구조를 노출시키는 단계(도1d)와; 고온산화 분위기에서 노출된 폴리실리콘(8)을 산화시켜 산화막(11)을 형성하고, 상기 질화막(10)과 산화막(9)을 제거하는 단계(도1e)와; 그 산화막(11)이 형성된 반도체기판(1)의 상부전면에 산화막(12)을 형성하고, 그 산화막(12)의 상부에 포토레지스트(PR1)를 도포한 후, 노광 및 현상하여 상기 피형 웰(4)과 인접하는 엔형 드리프트(5) 상의 산화막(12) 상부일부에 포토레지스트(PR1)를 형성하고, 포토레지스트(PR1)가 도포되지 않은 영역의 산화막(12)을 습식식각하는 단계(도1f)로 이루어지며, 이후에 게이트산화막, 게이트전극 및 소스/드레인을 형성하고, 배선을 형성하여 트렌치구조를 통해 절연되는 수평 확산형 모스트랜지스터의 제조가 완료된다. 이하, 상기한 바와같은 종래 수평 확산형 모스트랜지스터의 분리영역 제조방법을 좀더 상세히 설명한다.1A through 1F are cross-sectional views illustrating a method of manufacturing a separation region of a conventional horizontal diffusion type MOS transistor. As shown in FIG. 1A through 1F, an epitaxial epitaxial layer may be formed on top of an insulating oxide film 2 on an SOI structure semiconductor substrate 1. 3) and then forming a well of a well 4 and an drift 5 on the epitaxial layer 3 to define a high voltage transistor region (FIG. 1A); Forming a trench structure at the edge of the high voltage transistor region to expose the insulating oxide film 2 therein, and growing an oxide film 6 on the wall surface of the trench structure (FIG. 1B); Depositing an oxide film 7 and a polysilicon 8 on the upper surface of the semiconductor substrate 1 on which the oxide film 6 is formed, followed by etching to completely fill the trench structure (FIG. 1C); After the surface of the semiconductor substrate 1 is thermally oxidized to form an oxide film 9, a nitride film 10 is formed on the oxide film 9, and patterned through a photolithography process to expose the trench structure. Step (FIG. 1D); Oxidizing the polysilicon (8) exposed in a high temperature oxidation atmosphere to form an oxide film (11), and removing the nitride film (10) and the oxide film (9) (FIG. 1E); The oxide film 12 is formed on the upper surface of the semiconductor substrate 1 on which the oxide film 11 is formed, and the photoresist PR1 is coated on the oxide film 12, and then exposed and developed to expose the wells. Forming a photoresist PR1 on an upper portion of the oxide film 12 on the n-type drift 5 adjacent to 4) and wet etching the oxide film 12 in a region where the photoresist PR1 is not applied (FIG. 1F). Next, a gate oxide film, a gate electrode and a source / drain are formed, and wiring is formed to manufacture a horizontal diffusion morph transistor which is insulated through the trench structure. Hereinafter, a method of manufacturing a separation region of a conventional horizontal diffusion type morph transistor as described above will be described in more detail.

먼저, 도1a에 도시한 바와같이 SOI구조의 반도체기판(1) 상부 절연산화막(2)의 상부에 피형 에피택셜층(3)을 형성한 후, 그 피형 에피택셜층(3) 상에 피형 웰(4)과 엔형 드리프트(5)를 형성하여 고전압 트랜지스터 영역을 정의한다.First, as shown in FIG. 1A, the epitaxial epitaxial layer 3 is formed on the upper portion of the insulating oxide film 2 of the semiconductor substrate 1 having the SOI structure, and thereafter, the well is formed on the epitaxial layer 3 of the SOI structure. (4) and the n-type drift 5 are formed to define the high voltage transistor region.

그리고, 도1b에 도시한 바와같이 고전압 트랜지스터 영역의 가장자리에 내부의 절연산화막(2)이 노출되도록 트렌치구조를 형성하고, 그 트렌치구조의 벽면에 산화막(6)을 성장시킨다. 이때, 트렌치구조는 반도체기판(1)의 상부전면에 산화막(미도시)을 화학기상증착법으로 증착한 후, 사진식각공정을 통해 패터닝하여 식각마스크를 형성하고, 이를 적용하여 반도체기판(1)을 식각하여 형성하며, 산화막(6)은 H2,O2의 분위기에서 900℃의 온도로 얇게 형성한다.As shown in Fig. 1B, a trench structure is formed at the edge of the high voltage transistor region to expose the insulating oxide film 2 therein, and the oxide film 6 is grown on the wall surface of the trench structure. In this case, the trench structure deposits an oxide film (not shown) on the upper surface of the semiconductor substrate 1 by chemical vapor deposition, and then forms an etching mask by patterning through a photolithography process, and applies the semiconductor substrate 1 to the trench substrate. It is formed by etching, and the oxide film 6 is thinly formed at a temperature of 900 ° C. in an atmosphere of H 2 , O 2 .

그리고, 도1c에 도시한 바와같이 산화막(6)이 형성된 반도체기판(1)의 상부전면에 산화막(7) 및 폴리실리콘(8)을 증착한 후, 식각하여 트렌치구조를 완전히 채운다. 이때, 폴리실리콘(8)은 에치백하고, 산화막(7)은 HF용액에 세정하여 트렌치구조가 형성되지 않은 반도체기판(1)을 노출시킨다.1C, an oxide film 7 and a polysilicon 8 are deposited on the upper surface of the semiconductor substrate 1 on which the oxide film 6 is formed, and then etched to completely fill the trench structure. At this time, the polysilicon 8 is etched back, and the oxide film 7 is washed with HF solution to expose the semiconductor substrate 1 in which the trench structure is not formed.

그리고, 도1d에 도시한 바와같이 반도체기판(1)의 표면을 열산화시켜 산화막(9)을 형성한 후, 그 산화막(9)의 상부에 질화막(10)을 형성하고, 사진식각공정을 통해 패터닝하여 상기 트렌치구조를 노출시킨다. 이때, 질화막(10)은 저압화학기상증착법을 통해 형성하며, 트렌치구조 상부에 형성된 질화막(10)은 건식식각을 통해 제거한다.Then, as shown in FIG. 1D, the surface of the semiconductor substrate 1 is thermally oxidized to form an oxide film 9, and then a nitride film 10 is formed on the oxide film 9, and a photolithography process is performed. Patterning to expose the trench structure. In this case, the nitride film 10 is formed through a low pressure chemical vapor deposition method, the nitride film 10 formed on the trench structure is removed by dry etching.

그리고, 도1e에 도시한 바와같이 고온산화 분위기에서 노출된 폴리실리콘(8)을 산화시켜 산화막(11)을 형성하고, 상기 질화막(10)과 산화막(9)을 제거한다. 이때, 질화막(10)은 뜨거운 H3PO4용액에 세정하여 제거한다.1E, the polysilicon 8 exposed in the high temperature oxidation atmosphere is oxidized to form an oxide film 11, and the nitride film 10 and the oxide film 9 are removed. At this time, the nitride film 10 is removed by washing in a hot H 3 PO 4 solution.

그리고, 도1f에 도시한 바와같이 산화막(11)이 형성된 반도체기판(1)의 상부전면에 산화막(12)을 형성하고, 그 산화막(12)의 상부에 포토레지스트(PR1)를 도포한 후, 노광 및 현상하여 상기 피형 웰(4)과 인접하는 엔형 드리프트(5) 상의 산화막(12) 상부일부에 포토레지스트(PR1)를 형성하고, 포토레지스트(PR1)가 도포되지 않은 영역의 산화막(12)을 습식식각한다. 이때, 산화막(12)은 화학기상증착법을 통해 7000Å의 두께로 증착하고, 식각되지 않은 산화막(12)은 고전압 트랜지스터 영역의 엔형 드리프트(5)에 리서프(reduced surface : resurf) 필드(field)로 작용하며, 상기 트렌치구조의 상부에 형성된 산화막(11)도 습식식각에 의해 식각되어 두께가 얇아진다.Then, as shown in Fig. 1F, an oxide film 12 is formed on the upper surface of the semiconductor substrate 1 on which the oxide film 11 is formed, and after the photoresist PR1 is applied on the oxide film 12, The photoresist PR1 is formed on an upper portion of the oxide film 12 on the n-type drift 5 adjacent to the target well 4 by exposure and development, and the oxide film 12 in the region where the photoresist PR1 is not applied. Wet etch. At this time, the oxide film 12 is deposited to a thickness of 7000 kV through chemical vapor deposition, and the non-etched oxide film 12 is reduced to the reduced surface (resurf) field in the n-type drift 5 of the high voltage transistor region. The oxide film 11 formed on the trench structure is also etched by wet etching, so that the thickness becomes thin.

한편, 도2는 제조가 완료된 종래 수평 확산형 모스트랜지스터를 보인 사시도이다.On the other hand, Figure 2 is a perspective view showing a conventional horizontal diffusion type morph transistor is completed.

그러나, 상기한 바와같은 종래 수평 확산형 모스트랜지스터의 분리영역 제조방법은 트렌치구조의 상부에 산화막을 형성하는 별도의 공정이 추가되므로, 공정의 안정성이 저하되고, 제조단가가 상승하는 문제점이 있었다.However, in the method of manufacturing a separation region of the conventional horizontal diffusion type MOS transistor as described above, since a separate process of forming an oxide film is added to the upper portion of the trench structure, there is a problem that the process stability is lowered and the manufacturing cost is increased.

본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 분리영역의 제조공정을 단순화하여 신뢰성과 양산성을 향상시킬 수 있는 수평 확산형 모스트랜지스터의 분리영역 제조방법을 제공하는데 있다.The present invention was devised to solve the above problems, and an object of the present invention is to provide a method for manufacturing a separation region of a horizontal diffusion type morph transistor, which can improve the reliability and mass production by simplifying the manufacturing process of the separation region. It is.

도1은 종래 수평 확산형 모스트랜지스터의 분리영역 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a method for manufacturing a separation region of a conventional horizontal diffusion morph transistor.

도2는 제조가 완료된 종래 수평 확산형 모스트랜지스터를 보인 사시도.Figure 2 is a perspective view showing a conventional horizontal diffusion morph transistor is completed manufacturing.

도3은 본 발명의 일 실시예를 보인 수순단면도.Figure 3 is a cross-sectional view showing an embodiment of the present invention.

도4는 제조가 완료된 본 발명의 일 실시예를 보인 사시도.Figure 4 is a perspective view showing an embodiment of the present invention the manufacturing is completed.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

21:반도체기판 22:절연산화막21: semiconductor substrate 22: insulating oxide film

23:피형 에피택셜층 24:피형 웰23: skin epitaxial layer 24: skin well

25:엔형 드리프트 26,27,29:산화막25: N-type drift 26, 27, 29: Oxide film

28:폴리실리콘 PR21:포토레지스트28: polysilicon PR21: photoresist

상기한 바와같은 본 발명의 목적은 에스오아이(SOI) 구조를 갖도록 반도체기판 위에 적층된 절연산화막의 상부에 피형 에피택셜층을 형성한 후, 그 피형 에피택셜층 상에 피형 웰과 엔형 드리프트를 형성하여 고전압 트랜지스터 영역을 정의하는 공정과; 상기 고전압 트랜지스터 영역의 가장자리에 상기 절연산화막의 일부가 노출되도록 선택 식각하여 트렌치를 형성하고, 그 트렌치의 벽면에 제1산화막을 성장시키는 공정과; 상기 제1산화막이 형성된 결과물의 상부전면에 제2산화막과 폴리실리콘을 순차적으로 증착하고, 평탄화하여 트렌치를 완전히 채우는 공정과; 상기 트렌치가 채워진 결과물의 상부전면에 제3산화막을 증착하고, 상기 트렌치의 상부 및 상기 피형 웰과 인접하는 엔형 드리프트의 상부에 형성된 제3산화막이 선택적으로 잔류하도록 사진식각을 실시하는 공정을 구비하여 이루어짐으로써 달성되는 것으로, 본 발명에 의한 수평 확산형 모스트랜지스터의 분리영역 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above is to form the epitaxial epitaxial layer on top of the insulating oxide film laminated on the semiconductor substrate to have a SOI structure, and then to form the well and n-type drift on the epitaxial layer. Defining a high voltage transistor region; Selectively etching a portion of the insulating oxide film at an edge of the high voltage transistor region to form a trench, and growing a first oxide film on a wall of the trench; Depositing a second oxide film and polysilicon sequentially on the upper surface of the resultant product on which the first oxide film is formed, and planarizing to completely fill the trench; And depositing a third oxide film on the upper surface of the trench-filled resultant, and performing photolithography to selectively retain the third oxide film formed on the upper portion of the trench and on the upper portion of the n-type drift adjacent to the well of the trench. This is achieved by being made, and will be described in detail with reference to the accompanying drawings, a method for producing a separation region of the horizontal diffusion type morph transistor according to the present invention.

도3a 내지 도3d는 본 발명의 일 실시예를 보인 수순단면도로서, 이에 도시한 바와같이 SOI구조의 반도체기판(21) 상부 절연산화막(22)의 상부에 피형 에피택셜층(23)을 형성한 후, 그 피형 에피택셜층(23) 상에 피형 웰(24)과 엔형 드리프트(25)를 형성하여 고전압 트랜지스터 영역을 정의하는 단계(도3a)와; 그 고전압 트랜지스터 영역의 가장자리에 내부의 절연산화막(22)이 노출되도록 트렌치구조를 형성하고, 그 트렌치구조의 벽면에 산화막(26)을 성장시키는 단계(도3b)와; 그 산화막(26)이 형성된 반도체기판(21)의 상부전면에 산화막(27) 및 폴리실리콘(28)을 증착한 후, 식각하여 트렌치구조를 완전히 채우는 단계(도3c)와; 그 트렌치구조가 채워진 반도체기판(21)의 상부전면에 산화막(29)을 증착하고, 그 산화막(29)의 상부에 포토레지스트(PR21)를 도포한 후, 노광 및 현상하여 상기 트렌치구조 상의 산화막(29) 상부와 상기 피형 웰(24)과 인접하는 엔형 드리프트(25) 상의 산화막(29) 상부일부에 포토레지스트(PR21)를 형성하고, 포토레지스트(PR21)가 도포되지 않은 영역의 산화막(29)을 습식식각하는 단계(도3d)로 이루어진다.3A to 3D are cross-sectional views showing an embodiment of the present invention, in which the epitaxial epitaxial layer 23 is formed on the upper insulating oxide layer 22 on the semiconductor substrate 21 of the SOI structure. Thereafter, forming a well (24) and an en- drift (25) on the epitaxial epitaxial layer (23) to define a high voltage transistor region (FIG. 3A); Forming a trench structure at the edge of the high voltage transistor region to expose the insulating oxide film 22 therein, and growing an oxide film 26 on the wall surface of the trench structure (FIG. 3B); Depositing an oxide film 27 and a polysilicon 28 on the upper surface of the semiconductor substrate 21 on which the oxide film 26 is formed, followed by etching to completely fill the trench structure (FIG. 3C); The oxide film 29 is deposited on the upper surface of the semiconductor substrate 21 filled with the trench structure, the photoresist PR21 is coated on the oxide film 29, and then exposed and developed to expose the oxide film on the trench structure ( 29. A photoresist PR21 is formed on an upper portion and an upper portion of the oxide film 29 on the n-type drift 25 adjacent to the shaped well 24, and the oxide film 29 in a region where the photoresist PR21 is not applied. Wet etching is made (step 3d).

상기한 바와같은 본 발명의 일 실시예는 별도의 마스크를 이용하여 트렌치구조의 상부에 로코스(LOCOS) 공정방법으로 산화막(11)을 형성하는 종래의 제조방법과 다르게, 고전압 트랜지스터 영역의 엔형 드리프트(25) 상부에 사진식각공정을 통해 리서프 필드로 증착되는 산화막(29)의 형성시에 트렌치구조의 상부에 산화막(29)을 동시에 형성한다.One embodiment of the present invention as described above, unlike the conventional manufacturing method of forming the oxide film 11 by the LOCOS process method on the trench structure by using a separate mask, n-type drift of the high voltage transistor region (25) An oxide film 29 is simultaneously formed on the trench structure when the oxide film 29 is deposited on the resurf field through a photolithography process.

한편, 도4는 제조가 완료된 본 발명의 일 실시예를 보인 사시도이다.On the other hand, Figure 4 is a perspective view showing an embodiment of the present invention the manufacturing is completed.

상기한 바와같은 본 발명에 의한 수평 확산형 모스트랜지스터의 분리영역 제조방법은 고전압 트랜지스터와 저전압 씨모스 트랜지스터가 하나의 칩으로 통합되는 파워 아이씨 기술에서 고전압 트랜지스터의 트렌치 분리영역 형성을 단순화할 수 있게 되어 신뢰성과 양산성을 향상시킬 수 있는 효과가 있다.As described above, the method of manufacturing the isolation region of the horizontal diffusion MOS transistor according to the present invention can simplify the formation of the trench isolation region of the high voltage transistor in the power IC technology in which the high voltage transistor and the low voltage CMOS transistor are integrated into one chip. There is an effect that can improve the reliability and mass production.

Claims (1)

에스오아이(SOI) 구조를 갖도록 반도체기판 위에 적층된 절연산화막의 상부에 피형 에피택셜층을 형성한 후, 그 피형 에피택셜층 상에 피형 웰과 엔형 드리프트를 형성하여 고전압 트랜지스터 영역을 정의하는 공정과; 상기 고전압 트랜지스터 영역의 가장자리에 상기 절연산화막의 일부가 노출되도록 선택 식각하여 트렌치를 형성하고, 그 트렌치의 벽면에 제1산화막을 성장시키는 공정과; 상기 제1산화막이 형성된 결과물의 상부전면에 제2산화막과 폴리실리콘을 순차적으로 증착하고, 평탄화하여 트렌치를 완전히 채우는 공정과; 상기 트렌치가 채워진 결과물의 상부전면에 제3산화막을 증착하고, 상기 트렌치의 상부 및 상기 피형 웰과 인접하는 엔형 드리프트의 상부에 형성된 제3산화막이 선택적으로 잔류하도록 사진식각을 실시하는 공정을 구비하여 이루어지는 것을 특징으로 하는 수평 확산형 모스트랜지스터의 분리영역 제조방법.Forming a epitaxial epitaxial layer on top of the insulating oxide film stacked on the semiconductor substrate so as to have a SOI structure, and then forming a well and an drift on the epitaxial layer to define a high voltage transistor region; ; Selectively etching a portion of the insulating oxide film at an edge of the high voltage transistor region to form a trench, and growing a first oxide film on a wall of the trench; Depositing a second oxide film and polysilicon sequentially on the upper surface of the resultant product on which the first oxide film is formed, and planarizing to completely fill the trench; And depositing a third oxide film on the upper surface of the trench-filled resultant, and performing photolithography to selectively retain the third oxide film formed on the upper portion of the trench and on the upper portion of the n-type drift adjacent to the well of the trench. Separation region manufacturing method of a horizontal diffusion morph transistor, characterized in that made.
KR1019980019017A 1998-05-26 1998-05-26 Method for fabricating isolation region of lateral double deffused mos transistor KR100273305B1 (en)

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