KR100273286B1 - Method for fabricating gate of semiconductor device - Google Patents
Method for fabricating gate of semiconductor device Download PDFInfo
- Publication number
- KR100273286B1 KR100273286B1 KR1019980010291A KR19980010291A KR100273286B1 KR 100273286 B1 KR100273286 B1 KR 100273286B1 KR 1019980010291 A KR1019980010291 A KR 1019980010291A KR 19980010291 A KR19980010291 A KR 19980010291A KR 100273286 B1 KR100273286 B1 KR 100273286B1
- Authority
- KR
- South Korea
- Prior art keywords
- photoresist
- chamber
- gate
- lower electrode
- electrode
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 238000000034 method Methods 0.000 title claims abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 57
- 229920000642 polymer Polymers 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052710 silicon Inorganic materials 0.000 abstract description 8
- 239000010703 silicon Substances 0.000 abstract description 8
- 239000007789 gas Substances 0.000 abstract 2
- 239000006117 anti-reflective coating Substances 0.000 abstract 1
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- 239000001301 oxygen Substances 0.000 abstract 1
- 229910052760 oxygen Inorganic materials 0.000 abstract 1
- 230000003667 anti-reflective effect Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- -1 and at the same time Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005086 pumping Methods 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 게이트 제조방법에 관한 것으로, 특히 게이트를 식각할 때, 포토레지스트와 반사방지막의 식각 선택비를 확보하여 보다 정확한 임계치수(critical dimension : CD)를 구현하기에 적당하도록 한 반도체소자의 게이트 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate of a semiconductor device. In particular, when etching a gate, a semiconductor having a selectivity ratio between a photoresist and an anti-reflection film is secured so as to be more suitable for realizing a critical dimension (CD) It relates to a method for manufacturing a gate of the device.
종래 반도체소자의 게이트 제조방법을 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.A method of manufacturing a gate of a conventional semiconductor device will be described in detail with reference to the accompanying drawings.
도1a 내지 도1c는 일반적인 반도체소자의 게이트 제조방법을 보인 수순단면도로서, 이에 도시한 바와같이 반도체기판(1)의 상부에 순차적으로 게이트산화막(2), 게이트전극(3), 절연막(4) 및 반사방지막(5)을 형성하는 단계(도1a)와; 그 반사방지막(5)의 상부에 포토레지스트(PR1)를 도포한 후, 노광 및 현상하여 패터닝하고, 반사방지막(5)을 식각하는 단계(도1b)와; 순차적으로 절연막(4), 게이트전극(3) 및 게이트산화막(2)을 식각한 후, 포토레지스트(PR1)를 제거하여 게이트를 형성하는 단계(도1c)로 이루어진다. 이하, 상기한 바와같은 종래 반도체소자의 게이트 제조방법을 좀더 상세히 설명한다.1A through 1C are cross-sectional views showing a method of manufacturing a gate of a general semiconductor device. As shown in FIG. 1, the gate oxide film 2, the gate electrode 3, and the insulating film 4 are sequentially formed on the semiconductor substrate 1. And forming an antireflection film 5 (FIG. 1A); Applying photoresist PR1 on top of the antireflection film 5, then patterning by exposing and developing, and etching the antireflection film 5 (Fig. 1B); After sequentially etching the insulating film 4, the gate electrode 3, and the gate oxide film 2, the photoresist PR1 is removed to form a gate (FIG. 1C). Hereinafter, a method of manufacturing a gate of a conventional semiconductor device as described above will be described in more detail.
먼저, 도1a에 도시한 바와같이 반도체기판(1)의 상부에 순차적으로 게이트산화막(2), 게이트전극(3), 절연막(4) 및 반사방지막(5)을 형성한다. 이때, 게이트전극(3)으로는 도핑된 폴리실리콘과 텅스텐 실리사이드(silicide)의 적층구조를 사용하거나, 폴리실리콘만을 사용하고, 절연막(4)은 이후의 공정에서 엘디디구조의 형성 및 콘택홀의 형성시 자기정렬을 위해 질화막을 사용하며, 반사방지막(5)은 빛의 난반사로 인한 배선의 국부적인 끊김이나 얇아짐을 방지하기 위해 증착한다.First, as shown in FIG. 1A, a gate oxide film 2, a gate electrode 3, an insulating film 4, and an antireflection film 5 are sequentially formed on the semiconductor substrate 1. In this case, the doped polysilicon and tungsten silicide layered structure may be used as the gate electrode 3, or only polysilicon may be used, and the insulating film 4 may form an LED structure and a contact hole in a subsequent process. The nitride film is used for self-alignment at the time, and the anti-reflection film 5 is deposited to prevent local disconnection or thinning of the wiring due to diffuse reflection of light.
그리고, 도1b에 도시한 바와같이 반사방지막(5)의 상부에 포토레지스트(PR1)를 도포한 후, 패터닝하여 반사방지막(5)을 식각한다. 이때, 포토레지스트(PR1)는 포토레지스트(PR1)를 도포한 후, 노광 및 현상하여 게이트가 형성되지 않는 영역의 포토레지스트(PR1)를 제거하는 통상의 사진식각공정으로 반사방지막(5)을 노출시켜 식각한다.As shown in FIG. 1B, the photoresist PR1 is coated on the antireflection film 5, and then patterned to etch the antireflection film 5. At this time, the photoresist PR1 exposes the anti-reflection film 5 by a conventional photolithography process in which the photoresist PR1 is applied and then exposed and developed to remove the photoresist PR1 in the region where the gate is not formed. Etch it.
이와같은 반사방지막(5)은 포토레지스트(PR1)와 주성분이 유사하여 식각시 포토레지스트(PR1)에 대한 반사방지막(5)의 선택비를 확보하기에 상당한 노력을 요하게 되며, 반사방지막(5)의 식각공정은 도2의 챔버를 도시한 단면도를 참조하면, 하부전극(12)상에 포토레지스트(PR1) 패턴 및 반사방지막(5)이 형성된 웨이퍼(13)를 올려놓은 상태에서 N2/O2가스를 주입하고, 상부전극(11) 및 하부전극(12)에 고주파전원을 인가하여 N2/O2플라즈마(14)를 형성하여 식각을 진행한다.Since the antireflection film 5 has a main component similar to that of the photoresist PR1, it requires considerable effort to secure the selectivity of the antireflection film 5 to the photoresist PR1 during etching, and the antireflection film 5 the etching process is a reference to a cross-sectional view showing the chamber of the second, lower electrode the photoresist (PR1) on the 12 pattern and the anti-reflection film (5) N 2 / O in a state placed the wafer 13 is formed 2 gas is injected, and an N 2 / O 2 plasma 14 is formed by applying a high frequency power to the upper electrode 11 and the lower electrode 12 to perform etching.
이때, N2/O2플라즈마(14)내의 N*라디컬(radical)은 포토레지스트(PR1) 및 반사방지막(5)의 주성분인 C와 결합하여 포토레지스트(PR1)의 측벽 및 반사방지막(5)의 상부에 C-N결합 폴리머(polymer)를 형성하고, O*라디컬은 C와 결합하여 증기압이 낮은 CO 또는 CO2를 형성하는데, 포토레지스트(PR1)의 측벽에 형성된 C-N결합 폴리머는 포토레지스트(PR1)가 식각되는 것을 방지하고, 건식식각의 특징인 수직방향으로 이방성식각이 이루어져 반사방지막(5)의 상부에 형성된 C-N결합 폴리머는 반사방지막(5)과 함께 식각되어 CO 또는 CO2를 형성하고, 이 CO 또는 CO2는 펌핑을 통해 반응실에서 제거된다.At this time, N * radicals in the N 2 / O 2 plasma 14 are combined with C, which is a main component of the photoresist PR1 and the antireflection film 5, and the sidewall and the antireflection film 5 of the photoresist PR1. A CN-bonded polymer is formed on the upper side, and the O * radical combines with C to form CO or CO 2 having low vapor pressure. The CN-bonded polymer formed on the sidewall of the photoresist PR1 is formed of a photoresist ( PR1) is prevented from being etched, and anisotropic etching is performed in a vertical direction, which is a characteristic of dry etching, and the CN-bonded polymer formed on the antireflection film 5 is etched together with the antireflection film 5 to form CO or CO 2 . This CO or CO 2 is removed from the reaction chamber by pumping.
그리고, 도1c에 도시한 바와같이 순차적으로 절연막(4), 게이트전극(3) 및 게이트산화막(2)을 식각한 후, 포토레지스트(PR1)를 제거하여 게이트를 형성한다.1C, the insulating film 4, the gate electrode 3, and the gate oxide film 2 are sequentially etched, and then the photoresist PR1 is removed to form a gate.
그러나, 상기한 바와같은 종래 반도체소자의 게이트 제조방법은 포토레지스트 및 반사방지막의 주성분이 유사하여 포토레지스트에 대한 반사방지막의 식각 선택비를 확보하기 어려워 원하는 임계치수를 구현하기 어려운 문제점이 있었다.However, the gate manufacturing method of the conventional semiconductor device as described above has a problem that it is difficult to achieve the desired threshold dimension because it is difficult to secure the etch selectivity of the anti-reflection film to the photoresist because the main components of the photoresist and the anti-reflection film are similar.
본 발명은 상기한 바와같은 문제점을 해결하기 위하여 창안한 것으로, 본 발명의 목적은 포토레지스트에 대한 반사방지막의 식각 선택비를 확보하여 보다 정확하게 원하는 임계치수를 구현할 수 있는 반도체소자의 게이트 제조방법을 제공하는데 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method for manufacturing a gate of a semiconductor device which can more accurately implement a desired threshold dimension by securing an etching selectivity ratio of an antireflection film to a photoresist. To provide.
도1은 일반적인 반도체소자의 게이트 제조방법을 보인 수순단면도.1 is a cross-sectional view showing a gate manufacturing method of a general semiconductor device.
도2는 도1에 있어서, 반사방지막의 식각이 이루어지는 챔버를 도시한 단면도.FIG. 2 is a cross-sectional view of the chamber in which the anti-reflection film is etched in FIG.
도3은 본 발명의 일 실시예에 따른 반사방지막의 식각이 이루어지는 챔버를 도시한 단면도.3 is a cross-sectional view illustrating a chamber in which an anti-reflection film is etched according to an embodiment of the present invention.
도4는 도3에 있어서, 전처리방전을 실시한 결과의 그래프도.4 is a graph of the results of performing pretreatment discharge in FIG.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
20:CFx계열 폴리머 21:상부전극20: CFx series polymer 21: upper electrode
22:하부전극 23:웨이퍼22: lower electrode 23: wafer
24:N2/O2플라즈마24: N 2 / O 2 plasma
상기한 바와같은 본 발명의 목적은 반도체기판상에 순차적으로 게이트산화막, 게이트전극, 반사방지막 및 포토레지스트 패턴을 형성하여 타겟 웨이퍼를 준비함과 아울러 상기 반사방지막의 식각이 진행될 챔버의 하부전극상에 실리콘층과 포토레지스트가 적층된 전처리 웨이퍼를 올려놓고 CF계열의 가스를 주입한 다음 상부전극 및 하부전극에 고주파전원을 인가하여 챔버의 벽에 CFx계열 폴리머를 형성하는 단계와; 상기 전처리 웨이퍼를 제거하고, 챔버의 하부전극상에 타겟 웨이퍼를 올려놓은 상태에서 N2/O2가스를 주입하고, 상부전극 및 하부전극에 고주파전원을 인가하여 상기 포토레지스트 패턴에 따라 반사방지막을 식각하는 단계와; 상기 포토레지스트 패턴에 따라 게이트전극 및 게이트산화막을 식각하는 단계로 이루어짐으로써 달성되는 것으로, 본 발명에 의한 반도체소자의 게이트 제조방법을 도면을 참조하여 상세히 설명하면 다음과 같다.An object of the present invention as described above is to prepare a target wafer by sequentially forming a gate oxide film, a gate electrode, an antireflection film, and a photoresist pattern on a semiconductor substrate, and at the same time, silicon on the lower electrode of the chamber where the antireflection film is to be etched. Placing a pre-processed wafer on which layers and photoresists are stacked, injecting CF-based gas, and applying high-frequency power to the upper electrode and the lower electrode to form a CFx-based polymer on the wall of the chamber; The pretreatment wafer is removed, the N 2 / O 2 gas is injected while the target wafer is placed on the lower electrode of the chamber, and a high frequency power is applied to the upper electrode and the lower electrode to form an anti-reflection film according to the photoresist pattern. Etching; It is achieved by etching the gate electrode and the gate oxide film according to the photoresist pattern, the method of manufacturing a gate of a semiconductor device according to the present invention in detail with reference to the drawings as follows.
도3은 본 발명의 일 실시예에 따른 식각공정이 이루어지는 챔버의 단면도로서, 이에 도시한 바와같이 챔버의 벽에 실리콘웨이퍼의 방전을 통한 CFx계열 폴리머(20)가 형성되어 있고, 하부전극(22)상에 포토레지스트 패턴 및 반사방지막이 형성된 웨이퍼(23)를 올려놓은 상태에서 N2/O2가스를 주입하고, 상부전극(21) 및 하부전극(22)에 고주파전원을 인가하여 N2/O2플라즈마(24)를 형성하여 식각을 진행한다.3 is a cross-sectional view of a chamber in which an etching process is performed according to an embodiment of the present invention. As shown therein, a CFx-based polymer 20 is formed on the wall of the chamber through discharge of a silicon wafer, and the lower electrode 22 is formed. N 2 / O 2 gas is injected while the wafer 23 on which the photoresist pattern and the anti-reflective film is formed is placed thereon, and a high frequency power is applied to the upper electrode 21 and the lower electrode 22 to provide N 2 /. The O 2 plasma 24 is formed to perform etching.
이때, N2/O2플라즈마내의 N*라디컬은 종래와 마찬가지로 포토레지스트 및 반사방지막의 주성분인 C와 결합하여 포토레지스트의 측벽 및 반사방지막의 상부에 C-N결합 폴리머를 형성하고, O*라디컬은 C와 결합하여 증기압이 낮은 CO 또는 CO2를 형성하는데, 포토레지스트의 측벽에 형성된 C-N결합 폴리머는 포토레지스트가 식각되는 것을 방지하고, 건식식각의 특징인 수직방향으로 이방성식각이 이루어져 반사방지막의 상부에 형성된 C-N결합 폴리머는 반사방지막과 함께 식각되어 CO 또는 CO2를 형성하고, 이 CO 또는 CO2는 펌핑을 통해 반응실에서 제거된다.At this time, N * radicals in the N 2 / O 2 plasma are combined with C, which is a main component of the photoresist and the antireflection film, to form a CN-bonded polymer on the sidewall of the photoresist and the antireflection film as in the prior art, and the O * radical Is combined with C to form low vapor pressure CO or CO 2. The CN-bonded polymer formed on the sidewall of the photoresist prevents the photoresist from being etched and is anisotropically etched in the vertical direction, which is a characteristic of dry etching. CN-linked polymers formed thereon are etched with a bottom anti-reflective coat forming a CO or CO 2 and the CO or CO 2 is removed from the reaction chamber through a pump.
그런데, 이때 상기 실리콘웨이퍼의 전처리방전에 의해 챔버의 벽에 형성된 CFx계열 폴리머가 다량의 'C'를 포함하고 있으므로, N2/O2플라즈마내의 N*라디컬과 반응하여 C-N결합 폴리머를 형성하고, 주식각 요소인 O*라디컬과 반응하여 CO 또는 CO2를 형성한다. 따라서, N2/O2플라즈마내의 O*라디컬의 양을 감소시키고, 포토레지스트의 측벽은 보다 두터운 C-N결합 폴리머가 형성되어 반사방지막의 식각시 포토레지스트의 측벽을 안정되게 보호한다.However, since the CFx-based polymer formed on the wall of the chamber by the pretreatment discharge of the silicon wafer contains a large amount of 'C', it reacts with N * radicals in the N 2 / O 2 plasma to form a CN-bonded polymer. It reacts with the stock radical element O * radicals to form CO or CO 2 . Therefore, the amount of O * radicals in the N 2 / O 2 plasma is reduced, and the sidewalls of the photoresist have a thicker CN-bonded polymer formed to stably protect the sidewalls of the photoresist during etching of the antireflective film.
그리고, 상기 전처리방전에 사용하는 CF계열의 가스는 CxHyFz이고, 이때 x=1∼100, y=0∼100, z=1∼100이며, 실리콘층만을 성장시킨 경우 전처리 실리콘웨이퍼의 실시예는 도4a의 그래프도에 도시하였고, 실리콘층의 상부에 포토레지스트가 도포된 경우 전처리 실리콘웨이퍼의 실시예는 도4b의 그래프도에 도시하였다.In addition, the CF-based gas used for the pretreatment discharge is CxHyFz, wherein x = 1-100, y = 0-100, z = 1-100, and only the silicon layer is grown. 4a, an embodiment of a pretreatment silicon wafer when a photoresist is applied on top of the silicon layer is shown in the graph of FIG. 4b.
이에 도시한 바와같이 실리콘층의 상부에 포토레지스트가 도포된 경우가 뛰어난 특성을 보이는 것을 알수 있다.As shown in FIG. 2, it can be seen that the photoresist is applied to the upper portion of the silicon layer.
상기한 바와같은 본 발명에 의한 반도체소자의 게이트 제조방법은 주식각 요소인 O*라디컬의 양을 감소시키고, 포토레지스트의 측벽을 보다 두터운 C-N결합 폴리머로 보호하여 포토레지스트에 대한 반사방지막의 식각 선택비를 확보함에 따라 보다 정확하게 원하는 임계치수를 구현함으로써, 마스크검증 및 공정조건의 재설정 등에 따른 시간의 손실과 추가 장비의 구매에 따른 비용의 손실을 없앨수 있어 생산성을 향상시킬 수 있는 효과가 있다.The method for manufacturing a gate of a semiconductor device according to the present invention as described above reduces the amount of O * radicals, which are staple elements, and protects the sidewalls of the photoresist with thicker CN-bonded polymer to etch the anti-reflection film on the photoresist. By securing the selection ratio more accurately by implementing the desired threshold dimension, it is possible to eliminate the loss of time due to mask verification and resetting of the process conditions and the cost of purchasing additional equipment, thereby improving productivity.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980010291A KR100273286B1 (en) | 1998-03-25 | 1998-03-25 | Method for fabricating gate of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980010291A KR100273286B1 (en) | 1998-03-25 | 1998-03-25 | Method for fabricating gate of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990075840A KR19990075840A (en) | 1999-10-15 |
| KR100273286B1 true KR100273286B1 (en) | 2001-02-01 |
Family
ID=40749336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019980010291A KR100273286B1 (en) | 1998-03-25 | 1998-03-25 | Method for fabricating gate of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100273286B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9490140B2 (en) | 2014-08-26 | 2016-11-08 | Samsung Electronics Co., Ltd. | Method for manufacturing semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0621016A (en) * | 1992-07-01 | 1994-01-28 | Seiko Epson Corp | Manufacture of semiconductor device |
-
1998
- 1998-03-25 KR KR1019980010291A patent/KR100273286B1/en not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0621016A (en) * | 1992-07-01 | 1994-01-28 | Seiko Epson Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9490140B2 (en) | 2014-08-26 | 2016-11-08 | Samsung Electronics Co., Ltd. | Method for manufacturing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990075840A (en) | 1999-10-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7541270B2 (en) | Methods for forming openings in doped silicon dioxide | |
| US5843846A (en) | Etch process to produce rounded top corners for sub-micron silicon trench applications | |
| KR100743873B1 (en) | Techniques for improving etching in a plasma processing chamber | |
| KR100400173B1 (en) | Method of fabricating a semiconductor device | |
| US6475922B1 (en) | Hard mask process to control etch profiles in a gate stack | |
| KR20030081052A (en) | Method for manufacturing semiconductor device | |
| KR100273286B1 (en) | Method for fabricating gate of semiconductor device | |
| US20030096504A1 (en) | Method of dry etching for fabricating semiconductor device | |
| US6743726B2 (en) | Method for etching a trench through an anti-reflective coating | |
| JP3080055B2 (en) | Dry etching method | |
| KR100480233B1 (en) | Method for forming the contact hole of semiconductor device | |
| KR20040077272A (en) | Method of etching silicon nitride film | |
| KR100249012B1 (en) | Method for forming contact hole | |
| KR100283482B1 (en) | How to Form Plate Electrodes for Trench Capacitors | |
| KR20000061225A (en) | Method for fabricating trench of semiconductor device | |
| KR100668726B1 (en) | Method for forming the bit line contact in semiconductor device | |
| KR20020048616A (en) | Method for forming gate pattern of flash memory device | |
| KR100402940B1 (en) | Method for forming multi metal layer of semiconductor device | |
| KR100434312B1 (en) | Method for making contact hole in semiconductor device | |
| KR100342874B1 (en) | Method For Forming The Contact Double Photo Resist | |
| KR100434710B1 (en) | Method for forming via hole of semiconductor device | |
| JP2985841B2 (en) | Method for manufacturing semiconductor device | |
| KR100443351B1 (en) | Method of forming contact hole for semiconductor device | |
| KR20040039776A (en) | Method for forming the gate electrode in semiconductor device | |
| JP2003109943A (en) | Pattern formation method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20080820 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |