KR100273258B1 - Phase locked loop circuit - Google Patents

Phase locked loop circuit Download PDF

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KR100273258B1
KR100273258B1 KR1019970073460A KR19970073460A KR100273258B1 KR 100273258 B1 KR100273258 B1 KR 100273258B1 KR 1019970073460 A KR1019970073460 A KR 1019970073460A KR 19970073460 A KR19970073460 A KR 19970073460A KR 100273258 B1 KR100273258 B1 KR 100273258B1
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signal
amplifier
output
clock
input signal
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KR1019970073460A
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Korean (ko)
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KR19990053766A (en
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최준혁
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L1/00—Stabilisation of generator output against variations of physical values, e.g. power supply
    • H03L1/02—Stabilisation of generator output against variations of physical values, e.g. power supply against variations of temperature only
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0994—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising an accumulator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/14—Preventing false-lock or pseudo-lock of the PLL

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE: A phase synchronous loop circuit is provided to compensate for unlocking phenomenon in locking critical frequency by adding compensation circuit which is able to increase gain of amplifier in case input signal deviates a little from capture range in which input signal can be synchronized. CONSTITUTION: A compensation circuit(60) is added to a closed loop which consists of phase comparator(10), low filter(20), voltage control oscillator(40) and amplifier(50). Synchronization detector(61) detects deviation of input signal from synchronous range. A clock oscillator(62) generates clock according to output signal of the synchronization detector(61). A counter(63) increases number according to clock output in the clock oscillator(62) and outputs it. An adder(64) adds output of the counter(63) to set reference value and outputs the result. A D/A(digital/analog) convertor(65) converts digital signal which is output of the adder(64) into analog signal and outputs the converted signal, and controls gain of the amplifier(50).

Description

위상동기루프 회로{PHASE LOCKED LOOP CIRCUIT}Phase locked loop circuit {PHASE LOCKED LOOP CIRCUIT}

본 발명은 위상동기루프 회로에 관한 것으로, 특히 온도의 변화나 소자의 변동 등에 의하여 입력 신호를 동기(Lock)시킬 수 있는 범위인 캡쳐 범위(Capture Range)에서 입력 신호가 약간 벗어날 경우 시스템의 캡쳐 범위를 확장시켜 입력 신호를 동기시킬 수 있도록 하는 위상동기루프 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase-locked loop circuit, and in particular, a capture range of a system when the input signal deviates slightly from a capture range, which is a range in which an input signal can be locked due to temperature change or device change. The present invention relates to a phase-locked loop circuit that expands to synchronize an input signal.

위상동기루프(PLL : Phase Locked Loop) 회로는 외부로부터 들어오는 신호에 의해 임의의 주파수와 위상의 동기를 취하는 회로로 도 1은 종래 위상동기루프 회로의 구성을 보인 블록도로서, 이에 도시된 바와 같이 위상비교기(10), 저역필터(20), 증폭기(30) 및 전압제어 발진기(VCO, 40)로 이루어지는 폐루프로 구성되어 있는데, 입력신호(ΦS(t))와 전압제어 발진기(40)로 부터의 위상을 위상비교기(10)로 비교하여 오차신호를 얻으며, 그 오차신호를 저역필터(20)로 필터링하여 직류전압으로 변화시키고, 이 직류전압으로 증폭기(30)를 통해 전압제어 발진기(40)의 발진주파수를 제어하면 발진주파수는 입력신호의 주파수 즉, 위상과 완전히 일치하도록 한다.A phase locked loop (PLL) circuit is a circuit for synchronizing an arbitrary frequency and phase by a signal from an external source. FIG. 1 is a block diagram showing the configuration of a conventional phase locked loop circuit. As shown in FIG. It consists of a closed loop consisting of a phase comparator 10, a low pass filter 20, an amplifier 30, and a voltage controlled oscillator (VCO, 40), which consists of an input signal ΦS (t) and a voltage controlled oscillator 40. Compare the phase from the phase comparator 10 to obtain an error signal, filter the error signal with the low pass filter 20 to convert it to a DC voltage, and use the DC voltage through the voltage controlled oscillator 40 through the amplifier 30. When the oscillation frequency is controlled, the oscillation frequency should be completely coincident with the frequency of the input signal.

이를 첨부한 도 2를 참조하여 상세히 설명하면 다음과 같다.This will be described in detail with reference to FIG. 2.

도 2는 종래 위상동기루프 회로에서의 주파수와 전압의 상관 그래프로서, 이에 도시된 바와 같이 입력되는 신호의 주파수를 증가시킬 경우 주파수 f1에서 동기되어 주파수 f2까지 이동하면 동기가 풀어지며, 상기 주파수 f2에서부터 서서히 주파수를 낮추면 주파수 f3의 위치에서 동기되어 주파수 f4까지 이동하면 동기가 풀어진다. 또한 상기 입력 신호는 동기 범위안에 존재해야 만이 동기가 가능한데, 이 동기 범위를 식으로 나타내면 다음과 같다.FIG. 2 is a correlation graph between frequency and voltage in a conventional phase-locked loop circuit. As shown in FIG. 2, when the frequency of the input signal is increased, the synchronization is released when the frequency f1 is synchronized to the frequency f2 and the frequency f2 is released. From then on, the frequency is gradually lowered to synchronize the position at the frequency f3 and move up to the frequency f4. In addition, the input signal can be synchronized only if it exists in the synchronization range, which is expressed as follows.

Figure pat00001
Figure pat00001

여기서 KOSC는 전압제어 발진기의 주파수에서 전압으로의 변화이득 이고, KD는 전압에서 위상으로의 변화이득 이며, A는 증폭이득이다.Here, KOSC is the gain of change in frequency of voltage controlled oscillator from voltage, KD is the gain of change from voltage to phase, and A is amplification gain.

상기와 같이 종래의 기술에 있어서는 입력 신호의 주파수가 동기 범위의 임계 부분에 위치할 때 시스템의 온도변화 혹은 소자의 변화에 의해 동기 범위가 축소되거나 시프트되어 로킹(locking) 임계 주파수에서 언로킹(unlocking) 현상이 발생하는 문제점이 있었다.As described above, in the related art, when the frequency of the input signal is located at the critical portion of the synchronization range, the synchronization range is reduced or shifted by the temperature change of the system or the element change, thereby unlocking at the locking threshold frequency. ) There was a problem that occurs.

따라서, 본 발명은 상기와 같은 종래의 문제점을 해결하기 위하여 창안한 것으로, 입력 신호를 동기시킬 수 있는 범위인 캡쳐 범위(Capture Range)에서 입력 신호가 약간 벗어날 경우 증폭기의 이득을 키울 수 있도록 하는 보상회로를 추가함으로써 시스템의 캡쳐 범위를 확장시켜 입력 신호를 동기시킬 수 있도록 하는 위상동기루프회로를 제공함에 그 목적이 있다.Accordingly, the present invention was devised to solve the above-mentioned conventional problems, and compensates for increasing the gain of the amplifier when the input signal deviates slightly from the capture range, which is a range in which the input signal can be synchronized. It is an object of the present invention to provide a phase locked loop circuit that allows the input signal to be synchronized by expanding the capture range of the system.

도 1은 종래 위상동기루프 회로의 구성을 보인 블록도.1 is a block diagram showing the configuration of a conventional phase locked loop circuit.

도 2는 종래 위상동기루프 회로에서의 주파수와 전압의 상관 그래프.2 is a graph of correlation between frequency and voltage in a conventional phase-locked loop circuit.

도 3은 본 발명 위상동기루프 회로의 구성을 보인 블록도.Figure 3 is a block diagram showing the configuration of the phase-locked loop circuit of the present invention.

***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***

10 : 위상비교기 20 : 저역필터10: phase comparator 20: low pass filter

30 : 증폭기 40 : 전압제어발진기(VCO)30 amplifier 40 voltage controlled oscillator (VCO)

50 : 가변 증폭기 60 : 보상회로50: variable amplifier 60: compensation circuit

61 : 동기검출기 62 : 클럭발진기61: synchronous detector 62: clock oscillator

63 : 카운터 64 : 누산기63: counter 64: accumulator

65 : 디지탈/아날로그 변환기(DAC)65: digital to analog converter (DAC)

이와 같은 목적을 달성하기 위한 본 발명의 구성은, 위상비교기, 저역필터, 증폭기 및 전압제어 발진기로 이루어지는 폐루프로 구성되어 있는 위상동기루프 회로에 있어서, 입력 신호를 동기시킬 수 있는 범위인 캡쳐 범위(Capture Range)에서 입력 신호가 약간 벗어날 경우 증폭기의 이득을 키울 수 있도록 하는 보상회로를 구비함을 특징으로 한다.The configuration of the present invention for achieving the above object is a capture range which is a range capable of synchronizing an input signal in a phase locked loop circuit composed of a closed loop composed of a phase comparator, a low pass filter, an amplifier, and a voltage controlled oscillator. It features a compensation circuit to increase the gain of the amplifier when the input signal is slightly out of the (Capture Range).

상기 보상회로는 입력신호가 동기범위 영역에서 벗어나는 것을 검출하는 동기검출기와; 상기 동기검출기의 출력신호에 의해 클럭을 발생하는 클럭발진기와; 상기 클럭발진기에서 출력된 클럭에 따라 숫자를 증가시켜 출력하는 카운터와; 상기 카운터의 출력과 설정되어 있는 기준값을 더하여 출력하는 누산기와; 상기 누산기의 출력인 디지탈신호를 아날로그 신호로 변환한 제어신호를 출력하여 증폭기의 이득을 제어하는 디지탈/아날로그 변환기로 구성함을 특징으로 한다.The compensation circuit includes a synchronization detector for detecting that the input signal is out of the synchronization range region; A clock oscillator for generating a clock by the output signal of the synchronous detector; A counter for incrementing and outputting a number according to a clock output from the clock oscillator; An accumulator for adding and outputting the counter and a set reference value; And a digital / analog converter for controlling the gain of the amplifier by outputting a control signal obtained by converting the digital signal, which is the output of the accumulator, into an analog signal.

이하, 본 발명에 따른 일실시예를 첨부한 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

도 3은 본 발명 위상동기루프 회로의 구성을 보인 블록도로서, 이에 도시한 바와 같이 위상비교기(10), 저역필터(20), 전압제어 발진기(40) 및 증폭기(50)로 이루어지는 폐루프에 보상회로(60)를 구비하여 구성하고 즉, 입력신호가 동기범위 영역에서 벗어나는 것을 검출하는 동기검출기(61)와; 상기 동기검출기(61)의 출력신호에 의해 클럭을 발생하는 클럭발진기(62)와; 상기 클럭발진기(62)에서 출력된 클럭에 따라 숫자를 증가시켜 출력하는 카운터(63)와; 상기 카운터(63)의 출력과 설정되어 있는 기준값을 더하여 출력하는 누산기(64)와; 상기 누산기(64)의 출력인 디지탈신호를 아날로그 신호로 변환한 제어신호를 출력하여 상기 증폭기(50)의 이득을 제어하는 디지탈/아날로그 변환기(65)로 구성한다.3 is a block diagram showing the configuration of a phase-locked loop circuit according to the present invention. As shown in FIG. 3, a closed loop including a phase comparator 10, a low pass filter 20, a voltage controlled oscillator 40, and an amplifier 50 is shown. A synchronizing detector 61 configured to include a compensating circuit 60, that is, detecting that the input signal is out of the synchronizing range region; A clock oscillator 62 for generating a clock by the output signal of the synchronous detector 61; A counter 63 for increasing the number according to the clock output from the clock oscillator 62; An accumulator (64) for adding and outputting the output of the counter (63) and a set reference value; And a digital / analog converter 65 for controlling the gain of the amplifier 50 by outputting a control signal obtained by converting the digital signal, which is the output of the accumulator 64, into an analog signal.

동기 범위는 증폭기의 이득에 비례하는데, 입력신호(ΦS(t))가 동기 범위에서 벗어나게 되면 증폭기(50)의 출력은 상수 직류신호가 되지않고 계속 발진하게 되며, 이 신호는 동기검출기(61)에 의해 클럭발진기(62)에서 클럭을 발생하고, 이때부터 카운터(63)가 동작을 시작하며, 상기 클럭발진기(62)에서 출력된 클럭에 따라 숫자를 증가시켜 출력하면 이 카운터(63)의 출력과 설정되어 있는 기준전압의 데이터(기준값)를 누산기(64)에서 더하여 출력하고, 디지탈/아날로그 변환기(65)는 상기 누산기(64)의 출력인 디지탈신호를 아날로그 신호로 변환한 신호를 출력하여 상기 증폭기(50)의 이득을 제어한다.The synchronization range is proportional to the gain of the amplifier. When the input signal ΦS (t) is out of the synchronization range, the output of the amplifier 50 continues to oscillate instead of becoming a constant DC signal. The clock oscillator 62 generates a clock, and from this time, the counter 63 starts to operate, and if the number is increased in accordance with the clock output from the clock oscillator 62, the output of the counter 63 is outputted. And the data of the set reference voltage (reference value) is added to the accumulator 64, and the digital / analog converter 65 outputs a signal obtained by converting the digital signal, which is the output of the accumulator 64, into an analog signal. The gain of the amplifier 50 is controlled.

상기 증폭기(50)의 이득이 증가하여 그에 비례한 동기범위 또한 증가하면 동기검출기(61)는 입력신호가 동기 범위에 들어오는지를 검출하여 범위내이면 클럭발진기(62)에서 더 이상 클럭을 발생하지 않도록 신호를 보낸다.If the gain of the amplifier 50 increases and the synchronous range proportional to it also increases, the synchronous detector 61 detects whether the input signal enters the synchronous range and prevents the clock oscillator 62 from generating a clock any more when it is within the range. Send a signal

이상에서 설명한 바와 같이 본 발명 위상동기루프 회로는 온도변화나 시스템 자체 특성의 변화에 의한 동기 범위의 축소 또는 이동에 의한 로킹(locking) 임계 주파수에서의 언로킹(uniocking) 현상을 보상하여 주는 효과가 있다.As described above, the phase-locked loop circuit of the present invention has an effect of compensating for the unlocking phenomenon at the locking threshold frequency due to the reduction or movement of the synchronization range due to temperature change or changes in system characteristics. have.

Claims (1)

위상비교기, 저역필터, 증폭기 및 전압제어 발진기로 이루어지는 폐루프로 구성되어 있는 위상동기루프 시스템에 있어서, 상기 증폭기의 출력신호로 부터 입력신호가 동기범위 영역에서 벗어나는 것을 검출하는 동기검출기와; 상기 동기검출기의 출력신호에 의해 클럭을 발생하는 클럭발진기와; 상기 클럭발진기에서 출력된 클럭에 따라 숫자를 증가시켜 출력하는 카운터와; 상기 카운터의 출력과 설정되어 있는 기준값을 더하여 출력하는 누산기와; 상기 누산기의 출력인 디지탈신호를 아날로그 신호로 변환하여 상기 증폭기에 이득제어신호로 인가하는 디지탈/아날로그 변환기를 포함하여 구성된 것을 특징으로 하는 위상동기루프 회로.CLAIMS 1. A phase locked loop system consisting of a closed loop comprising a phase comparator, a low pass filter, an amplifier, and a voltage controlled oscillator, the phase locked loop system comprising: a synchronous detector for detecting a deviation of an input signal from an output signal of the amplifier; A clock oscillator for generating a clock by the output signal of the synchronous detector; A counter for incrementing and outputting a number according to a clock output from the clock oscillator; An accumulator for adding and outputting the counter and a set reference value; And a digital to analog converter for converting the digital signal, which is the output of the accumulator, into an analog signal and applying the gain control signal to the amplifier.
KR1019970073460A 1997-12-24 1997-12-24 Phase locked loop circuit KR100273258B1 (en)

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JP2001094418A (en) * 1999-09-21 2001-04-06 Toshiba Corp Voltage controlled oscillator
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