KR100271306B1 - A demultiplexer for atm cells - Google Patents

Abstract

The present invention relates to an AT cell separation apparatus for separating sequentially received AT cells to the corresponding subscriber port according to the header of the cell.

The apparatus of the present invention includes a control register 121, a port register 122-125 and a broadcast register 126, which are set according to control data transmitted from a host controller; Utopia interface unit 150 for receiving the cells received from the network side; A delay unit 160 delaying a predetermined clock cell according to the control signal; A comparator (130) for comparing the header of the received AT cell with the setting value of the port register or the setting value of the broadcast register according to a control signal and outputting the result; N FIFOs 170a-170e for sequentially storing and sequentially outputting AMT cells received from the delay unit according to a control signal; And a control signal for selecting a register value to the comparator according to a setting value of the control register, a control signal to the delay unit, and receiving a comparison result from the comparator and receiving the comparison result from the FIFO of the selected port. And a controller 140 that provides a control signal to store the ATM cell.

Therefore, the present invention can easily implement the broadcast and multicast functions using the GFC bit in the AT cell separation device.

Description

A demultiplexer for ATM cells

The present invention relates to an ATM cell separation apparatus for separating sequentially received ATM cells to the corresponding subscriber port (PORT) according to the header (HEADER) of the cell.

In general, in ATM networks, ATM cells are delivered through various paths through connections established according to VPI / VCI values. To this end, cells in each node are multiplexed or demultiplexed to perform cell switching. As such, the AMT cells reaching the network termination system through each node are delivered to the end subscriber station through the subscriber port according to the contents of the header. As described above, in the ATM technology, it is necessary to appropriately separate the cells according to the header contents of the ATM cell, and this function is achieved in the ATM cell separator.

By the way, the conventional AT cell separation device is to output a cell through a plurality of output ports, receives information about the output port of the cell from the system through a separate control path and generates a signal for specifying the cell output port Logic is required, and there was a problem in that it does not support broadcast or multicast functions.

Accordingly, the present invention has been made in order to solve the problems of the prior art, and an object thereof is to provide an ATM cell separation apparatus capable of broadcasting and multicasting.

In order to achieve the above object, the apparatus of the present invention separates the AT cells received from the network according to the control data transmitted from the host controller, and transmits the corresponding AT cells to N ports of the subscribers, respectively. A separator, comprising: a control register set according to control data transmitted from the host controller; N-1 port registers set according to the control data transmitted from the host controller; A broadcast register set according to the control data transmitted from the host controller; Utopia interface unit for receiving the cells received from the network side; A delay unit delaying a predetermined clock delay according to the control signal; A comparator for comparing the received header of the AT cell with a setting value of the port register or a setting value of the broadcast register and outputting a result according to a control signal; N FIFOs sequentially storing and sequentially outputting AMT cells received from the delay unit according to a control signal; N utopia interface units for delivering the output of the FIFO to the subscriber side; And a control signal for transmitting a control signal for selecting a register value to the comparator according to a setting value of the control register, and a control signal to a delay unit, receiving a comparison result from the comparator, and receiving the received FIFO from the selected port. And (ATM) a control unit for providing a control signal to store the cell.

1 is a block diagram showing an ATM cell separation apparatus according to the present invention,

2 is a configuration example of a register shown in FIG. 1;

Figure 3 is a configuration diagram to increase the port by expanding the AT cell separation apparatus according to the present invention,

4 is a format diagram of a general ATM cell.

* Explanation of symbols for main parts of the drawings

110: host interface unit 121: control register

122-125: port register 126: broadcast register

130: comparator 140: control unit

150: utopia interface unit 160: delay unit

170a ~ 170e: FIFO 180a ~ 180e: Utopia Interface

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, referring to FIG. 4, the structure of a general ATM cell is divided into a 5-byte header (H: header) section and a 48-byte user information section. The 5-byte header is a user network interface (UNI). There is a header structure in. The header structure of the user interface (UNI) is that the first byte consists of 4 bits of Generic Flow Control (GFC) and 4 bits of Virtual Path Identifier (VPI), and the second byte. Is composed of a 4-bit Virtual Path Identification Number (VPI) and a 4-bit Virtual Channel Identifier (VCI), and the third byte consists of an 8-bit Virtual Channel Identifier (VCI). Byte consists of 4-bit Virtual Channel Identification Number (VCI), 3-bit Payload Type (PT) and 1-bit Cell Loss Priority (CLP). It consists of Header Error Control (HEC).

Typically, the path of a cell is determined by VPI / VCI, but in the present invention, GFC bits are used for the multicast (MULTICAST) and broadcast (BROADCAST) functions. For example, in the embodiment of the present invention as described below, the port can be determined by the GFC bit as shown in Table 1 below.

GFC (4-bit) Cell type 0000 to 1100 Multicast 1111 Broadcast

As shown in Table 1, if the GFC bit is "1111" in the header of the ATM cell, it is a broadcast cell delivered to all ports, and if it is "1000-1100", it is a multicast cell delivered to designated ports. The GFC bit value specifying the broadcast cell is stored in the broadcast register (126 in FIG. 1), and the GFC value specifying the multicast is stored in the GFC area of the corresponding port register.

1 is a block diagram illustrating an AT cell detachment apparatus 100 according to the present invention, in which five ports are provided. Referring to FIG. 1, the ATM cell separator 100 includes a host interface unit 110, a control register 121, a port 1 register 122, a port 2 reg 123. , Port 3 register (Port3 Reg: 124), port 4 register (Port4 Reg: 125), broadcast register (Broadcast Reg: 126), comparator 130, control unit 140, utopia interface unit 150, delay unit (160), five first-in, first-out buffers (FIFO1-FIFO5: 170a-170e) and five utopian interface units (180a-180e) are configured to receive control data from the host control unit through the host interface unit 110 and registers. After setting, the received cell data is separated according to the register value and transmitted to the subscriber side through the corresponding port.

2 is a configuration example of the register shown in FIG. 1, (a) shows an example of the control register 121, (b) shows an example of each port register 122-125, and (c ) Shows the broadcast register 126. As shown in FIG. 2A, the control register 121 has "VPI / VCI", "VCI", "VPI", "BROAD & MULTI" bits, and when the corresponding bit is set to "1". Comparators 130 compare the corresponding values. For example, when using multicast or broadcast in accordance with the present invention, the " BROAD & MULTI " bit is set to " 1 " so that the comparator 130 can set the GFC bit in the header of the input cell and the port register or broadcast. The GFC bits in the registers are compared to determine the port to which the input cell will be sent. Similarly, if the "VPI" bit is set to "1", only VPI (8 bits) are compared in the ATM header, and if the "VCI" bit is set to "1", the VCI is in the ATM header. Only compare (16 bits). If the "VPI / VCI" bit is set, both VPI and VCI are compared.

Referring to (b) of FIG. 2, the port registers 122-126 are composed of 4 bits of GFC, 8 bits of VPI, and 16 bits of VCI to store header information of a cell to be transmitted to a corresponding port. Referring to Fig. 2 (c), the broadcast register 126 is composed of 4 bits of GFC to store a broadcast value. The value of such a register is set or changed from the host controller through the host interface 110.

Referring back to FIG. 1, the control register 121 indicates whether to perform multicast and broadcast on the received cell and determines which part of the header of the ATM cell to be compared. The value of this control register is set by a host controller (not shown) via the host interface.

The control unit 140 provides a control signal to the comparator 130 according to the set value of the control register 121 so that the comparator 130 selects a value to be compared. The input result of the comparison is received from the comparator 130 and the input ATM cell is stored in the FIFO of the selected port.

The comparator 130 reads the GFC, VPI, and VCI bits of the port 1 to port 4 registers 122-125 according to the control signal, and compares the result with the GFC, VPI, and VCI bits of the received AT cell header, respectively. Output to the controller 130. At this time, the comparison object is determined by the control signal of the controller 140 according to the setting value of the control register as described above.

The delay unit 160 delays the flow of the receiving cell by a predetermined clock for header comparison, and there is a difference in time for delaying data according to the comparison target of the header. For example, delaying two clocks when comparing only VPI and delaying four clocks when comparing only VCI.

The FIFOs 170a-170e sequentially store ATM cells delivered for each port to buffer the transmission rate difference between the input and output cells. The utopia interface units 180a-180e provide a UTOPIA interface, and the "UTOPIA (the Universal Test & Operations PHY Interface for ATM)" is a standard for connecting the ATM layer and the physical layer.

That is, the signals used for the transmission interface in the utopia interface are "TxData [7: 0]", "TxSoc", "TxEnb *", "TxFull * / TxClav", "TxClk", and the signals used for the receiving interface are " RxData [7: 0] "," RxSoc "," RxEnb * "," RxEmpty * / RxClav ", and" RxClk ".

Here, "TxData [7: 0]" is 8 bits wide as transmission data, and "TxSoc" is asserted at the first byte of the transmission cell by the ATM layer as the transmission cell start signal. "TxEnb *" is a transmit enable signal and is asserted when cell data is transmitted in the ATM layer. "TxFull *" asserts at the physical layer when the physical layer element receives 4 bytes or less in octet-level transmission, and "TxClav" indicates that the physical layer is capable of accommodating one complete cell in cell-level transmission. Assert And "TxClk" is a transmission clock supplied from the ATM layer to the physical layer for data transmission and signal synchronization. And " RxData [7: 0] " is 8 bits wide as received data, and " RxSoc " is asserted in the first byte of the receiving cell by the physical layer as the receiving cell start signal. &Quot; RxEnb * " asserts when cell data can be received at the ATM layer as an enable signal. "RxEmpty *" is asserted by the physical layer when there is no data to transmit to the ATM layer in octet level transmissions, and "RxClav" is asserted by the physical layer when there is a complete cell to transmit in the cell level transmission. And "RxClk" is a reception clock supplied by the ATM layer to the physical layer in order to synchronize the physical layer to transmit data and sample a signal.

Next, the operation of the embodiment according to the above configuration will be described by dividing into multicast and broadcast.

1. For broadcast (BROADCAST),

First, the "BROAD & MULTI" bit of the control register 121 is set to 1 by the host controller, so that the comparator 130 sets the GFC bit and the broadcast register 126 of the input cell, and each port register 122-. Compare the GFC bit of 125).

When the receiving cell is input via the utopia interface, the comparator 130 reads the GFC bit of the input cell header and compares it with the value stored in the broadcast register 126. In the embodiment of the present invention, as shown in Table 1, when the GFC bit is set to "1111", it is defined as broadcast. Therefore, "1111" is stored in the broadcast register 126. Therefore, when the GFC bit of the input cell header is "1111", the comparator 130 detects that the broadcast register value matches and notifies the control unit 140 of this. The controller 140 recognizes that the input cell is a broadcast cell according to the comparison result signal of the comparator 130, and stores all of the input cells in the FIFOs 170a to 170e of the ports 1 through 5 through the delay unit 160. do. In this way, the broadcast cells are stored in the FIFOs of all ports, and are then delivered to each subscriber via the utopia interface units 180a-180e of each port.

2. For multicast (MULTICAST)

Even in the case of multicast, the " BROAD & MULTI " bit of the control register 121 is set to " 1 ", so that the comparator 130 can input the GFC bit and the broadcast register 126 of the input cell and each port register 122. -125) compares the GFC bits. In multicast, unlike broadcast, the input cell must be delivered to several designated ports, so you will need to specify the port. In an embodiment of the present invention, the GFC value of a port for transmitting multicast is previously stored in the GFC bit area of the corresponding port by the host controller. For example, when using "1000" for multicast, the GFC of the receiving cell for multicast is set to "1000", and the GFC bit area is set to "1000" in the port register of the port to receive the cell. . If the user wants to transmit the multicast cell to port 2 and port 4, "1000" is stored in the GFC bit of the port 2 register 123 by the host controller, and "GFC bit" of the port 4 register 125 is also stored. 1000 "is stored.

When the receiving cell is input via the utopia interface 150, the comparator 130 reads the GFC bit of the input cell header and compares it with the value stored in the broadcast register 126. As described above, in the embodiment of the present invention, "1111" is stored in the broadcast register 126, and the GFC of the reception cell header is "1000" in case of multicast, so it will not match the broadcast register value. .

The comparator 130 compares the GFC bits of the port 1 register 122 to the port 4 register 125 with the GFC bits of the receiving cell, detects a match, and then outputs the result to the controller 140. In the embodiment of the present invention, since the GFC bits of the port 2 register 123 and the port 4 register 125 coincide with the GFC bits of the receiving cell, the receiving cell has the FIFO 170b of the port 2 and the FIFO 170d of the port 4. It is stored in and delivered to the subscriber side through each of the utopia interface unit (180b, 180d).

Meanwhile, in the embodiment of the present invention, the GFC bits are divided into multicast, broadcast, and designated ports, but this definition can be easily changed by changing the values of the corresponding registers in the host controller. In other words, if "10" is set in the broadcast register, the cell whose GFC bit is "10" will be the broadcast cell. If "1100" is stored in the GFC area of port 1, the GFC bit is received in the received cell. Cells having a value of "1100" will be output to port 1.

In the case of multicast and non-broadcast, the port can be designated by comparing VCI or VPI. This operation is similar to that described above except that the value being compared is not GFC but VCI or VPI. I will omit it.

Figure 3 is a block diagram to increase the port by expanding the ATM cell separation apparatus according to the present invention. In the embodiment of the present invention, when one cell separator supports five ports, as shown in FIG. 3, another cell separator having the same configuration may be connected to port 5 to expand to eight or more ports.

As described above, according to the present invention, since the broadcast and multicast functions can be easily implemented using GFC bits in an ATM cell separator, a device configuration for processing a receiving cell can be simplified and additionally. It is effective to provide functions.

Claims (3)

In the ATM cell separation apparatus for separating the ATM cells received from the network according to the control data transmitted from the host control unit and delivers the corresponding ATM cells to the N port of the subscriber, respectively. A control register 121 set according to the control data transmitted from the host controller; N-1 port registers 122-125 set according to the control data transmitted from the host controller; A broadcast register 126 set according to the control data transmitted from the host controller; Utopia interface unit 150 for receiving the cells received from the network side; A delay unit 160 delaying a predetermined clock cell according to the control signal; A comparator (130) for comparing the header of the received AT cell with the setting value of the port register or the setting value of the broadcast register according to a control signal and outputting the result; N FIFOs 170a-170e for sequentially storing and sequentially outputting AMT cells received from the delay unit according to a control signal; And ATM received a FIFO of the selected port by transmitting a control signal for selecting a register value to the comparator according to the setting value of the control register and a control signal to the delay unit, receiving a comparison result from the comparator Atm cell separation apparatus comprising a control unit 140 for providing a control signal to store the (ATM) cell. The method of claim 1, wherein the control register An ATM cell separator, characterized in that an area for selecting multicast and broadcast is defined. According to claim 1, wherein the AMT cell separator ATM cell separation device characterized in that the port can be expanded by connecting the devices of the same configuration in multiple stages.