KR100268500B1 - Wait signal generating circuit - Google Patents

Abstract

PURPOSE: A wait signal generation circuit is provided to use interface circuit and micom with different wait interfacing in one drive by generating wait signal with system clock stop signal. CONSTITUTION: An interface circuit(20) generates a system clock stop signal depending on the system clock stop module. A latch generates a wait signal including wait window region by output latch of the system clock stop signal when there occurs a determined edge at the input system clock from the interface circuit(20). A micom(10) temporarily stops the ongoing control process during the wait window region included in the wait signal. This wait signal generation circuit can be used in the regeneration drive of an optical disk.

Description

Waiting Signal Generation Circuit {WAIT SIGNAL GENERATING CIRCUIT}

The present invention relates to an interface circuit for generating a wait signal, and more particularly to a circuit for generating a wait signal using a system clock stop signal.

In optical disc playback drives such as CD-ROM (Compact Disc Read Only Memory) and DVD-ROM (Digital Video Disc Read Only Memory) drives, the microcomputer controls the overall operation of the drive, and signals transmitted and received between the microcomputer and the host computer. An interface circuit for interfacing is provided. Since the microcomputer and the interface circuit have different signal processing speeds, the weight interface method is adopted to solve the inconsistency in the operation time. The weight interface method includes a system clock stop method and a wait signal method. The system clock stop method suspends the generation of the output system clock and waits for the operation of the microcomputer. The standby signal system generates a standby signal between the interface circuit and the microcomputer to suspend signal processing on the other side. Hereinafter, the system clock stop method and the standby signal method described above with reference to FIGS. 1 and 2 will be described in detail. First, FIG. 1 is a block diagram illustrating a wait interface method. A timing diagram for explaining the type of weight interface method is shown. In FIG. 1 and FIG. 2, the SCS signal represents a system clock stop signal. The SCS signal is generated by the interface unit 20 and output to the microcomputer 10 as shown in FIG. 1. During the period in which the generation of the SCS signal is stopped, the microcomputer 10 maintains the ongoing control operation (for example, data reproducing operation) in a standby state and resumes the suspended control operation when the SCS signal is input again. Meanwhile, the standby signal illustrated in FIG. 2 is a signal generated from each of the microcomputer 10 or the interface unit 20 and output to the interface unit 20 or the microcomputer 10 as shown in FIG. 1, and the microcomputer 10 or the interface. Each of the sections 20 temporarily stops the control operation currently being processed in response to the waiting signal for requesting the temporary stop of the ongoing control operation. If the standby signal being input is input in an inactive state, the control operation which is suspended is resumed in response.

On the other hand, a general optical disc reproducing drive uses an AT ATTACHMENT PACKET INTERFACE interface. The ATAPI interface is an interface standard that supports a DVD-ROM drive by adding SCSI (SCSI) packet commands to the interface of the HDD. However, since the ATAPI interface outputs a wait signal according to the wait signal method to the microcomputer, the system clock stop method cannot be adopted.

Accordingly, an object of the present invention is to generate a standby signal regardless of the weight interface method between the microcomputer that controls the overall operation of the drive and the interface circuit for interfacing the data transmitted and received between the drive in the optical disc playback drive. It is to provide a standby signal generation circuit that can be.

It is still another object of the present invention to provide a standby signal generation circuit that can use a microcomputer and an interface circuit for changing a weight interfacing method by generating a standby signal using a system clock stop signal.

The present invention for achieving the above object in the standby signal generation circuit,

An interface circuit for generating and outputting a system clock stop signal according to a system clock stop method;

And latching the system clock stop signal at a predetermined edge of the system clock inputted from the interface circuit to generate a wait signal including a weight window section.

1 is a block diagram for explaining a weight interface method.

2 is a timing diagram for explaining the type of a weight interface method.

3 is a configuration diagram of a weight signal generation circuit according to an embodiment of the present invention.

4 is a timing diagram according to the configuration of FIG.

Hereinafter, the configuration and operation of a standby signal generating circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

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를 2입력으로 하고 있다. 그리고 마이컴(10)은 웨이트 인터페이스방식으로서 대기신호방식을 채용하도록 설계된 광 디스크 재생 드라이브의 제어부로서 P3단자를 통해 대기신호가 입력되는 경우 진행중인 제어동작을 일시 중지한다.3 is a block diagram of a weight signal generation circuit according to an exemplary embodiment of the present invention, and FIG. 4 is a timing diagram according to the configuration of FIG. 3. First, referring to FIG. 3, the interface unit 20 is an ATAPI interface generally used in an optical disc reproducing drive, and outputs a system clock stop signal SCS by the system clock stop method to the standby signal generation circuit 30 through the P1 terminal. do. At this time, the system clock stop signal SCS is applied to the D input terminal of the D flip-flop 36 in the standby signal generation circuit 30. The system clock SCLK output through the P2 terminal of the interface unit 20 is inverted and output from the inverter 32 to the clock terminal CLK of the D flip-flop 36. Accordingly, the D flip-flop 36 latches the system clock stop signal SCS through the Q terminal at the rising edge of the system clock SCLK input to the clock terminal CLK. At this time, the latch output signal through the Q terminal becomes a standby signal input to the P3 terminal of the microcomputer 10. The set terminal S of the D flip-flop 36 is connected to an output terminal of the NAND gate 34, and the NAND gate 34 is a read / write control signal.

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Is 2 inputs. The microcomputer 10 is a control unit of the optical disk reproducing drive designed to employ the standby signal method as the weight interface method, and suspends the ongoing control operation when the standby signal is input through the P3 terminal.

의 라이징 에지시에 래치출력되는 대기신호가 D플립플롭(36)의 출력단자(Q)를 통해 도 4에 도시한 바와 같이 "하이"레벨로 출력되다가 B시점에서 반전되어 D구간동안 "로우"레벨을 유지한다. 이때 상기 D구간이 바로 웨이트 윈도우 구간이되며, 상기 D구간동안 마이컴(10)은 진행중인 제어동작을 일시 중지한후 D구간 이후에 중지중인 제어동작을 재개한다.Hereinafter, the operation of the standby signal generating circuit 30 having the above-described configuration will be briefly described with reference to FIG. 4. First, the system clock stop signal SCS for stopping the control operation of the microcomputer 10 during the A timing section is connected to the P1 terminal. If it is output from the interface unit 20, the inverted system clock through the inverter 32

The wait signal latched at the rising edge of D is output to the "high" level through the output terminal Q of the D flip-flop 36 as shown in FIG. Keep your level. At this time, the section D becomes a weight window section, and during the section D, the microcomputer 10 pauses the ongoing control operation and resumes the suspended control operation after the section D.

As described above, the standby signal generation circuit 30 inputs the system clock stop signal SCS output from the interface unit 20 and converts it into a standby signal having a weight window section. It can be usefully used between the microcomputer and the interface circuit.

As described above, since the present invention can convert the system clock stop signal into a wait signal having a weight window section, two circuit elements having different weight interface methods can be connected to each other without being bound to the weight interface method. There is an advantage.

Claims (3)

In the standby signal generation circuit, An interface circuit for generating and outputting a system clock stop signal according to a system clock stop method; A latch unit for latching the system clock stop signal at a predetermined edge of the system clock input from the interface circuit to generate a wait signal including a weight window section; And a microcomputer for suspending a control operation currently in progress during a weight window period included in the wait signal. According to claim 1, The latch unit; An inverter for inputting and inverting the system clock; And a flip-flop for latching the system clock stop signal at the rising edge of the system clock inverted by the inverter. An interface circuit for generating and outputting a system clock stop signal according to the system clock stop method, and a standby signal generating circuit of an optical disc reproducing drive having at least a controller for stopping a control operation currently in progress when a standby signal having a weight window section is input; To And latching the system clock stop signal at a predetermined edge of the system clock output from the interface circuit so as to generate at least the wait signal including the weight window section and to output the signal to the controller. Standby signal generation circuit for a disc playback drive.

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