KR0157586B1 - Circuit for generating a control signal - Google Patents

Abstract

DAT-DS can be used alternately during recording and playback by using two DSP chips, and the operation of the DSP chip should be synchronized by delaying the drum head by 90 ° after writing. Generate and operate the DSP, and generate FRSYNCR and FRSYNCP, which are the criteria for determining the input and output data of the buffer controller, and the buffer controller determines the position of Wo of the data transmitted from the DSP through the signal, and switches the head of the RF amplifier. The signal SWHPA and the playback / recording switching signal PB can be supplied to the generated RF amplifier so that one-chip can be achieved with a simple configuration.

Description

RF Amplification Control Signal Generation Circuit of DAT-DS System

1 is a block diagram according to the present invention.

2 is a concrete circuit diagram of the timing signal generator 106 of FIG.

3 to 6 are operational timing diagrams in accordance with the present invention.

The present invention relates to an RF amplification control signal generation circuit in a DAT-DS system.

Recently, a DAT-DS (Digital Audio Tape Data Storage) system using DAT technology has been announced as a data backup device.

FIG. 1 is a block diagram of the DAT-DS system, which describes the function and operation relationship of the lead head A 'of the mechanism 101 (not shown: the light heads A, B lead heads A', B 'are shown in the drum). Read) and is inputted from the RF amplifier 122 to the data strobe unit 108 through the EQOUT stage. This signal is supplied to the recording processing unit 105 constituted by the DSP through the data bus PDATA in synchronization with its clock generator clock stage PDCK in the data strobe unit 108. The data that has undergone error correction or the like in the recording processing unit 105 is determined by the frame synchronizing signal FRSYNCP, which is a signal generated by the timing signal generating unit 106, and is synchronized with the MPXP through the output terminal SOUT. Supplied to. The microcomputer 110 selects the recording / playback processing units 105 and 107 and the head servo unit 109 through CTRLP and CTRL, and transmits control data through CDATAI and CDATAO.

On the other hand, the head servo unit 109 receives the RF signal from the RF amplifier 102 to perform an ATF servo and the like, and receives the DFG, CFG, DTP signals, etc. from the mechanism 101 and performs the mechanism servo. At this time, PDCK, SREF, and PARITY signals, which are reference signals, are supplied from the recording / reproducing processing units 105 and 107. This is an example of playback.

When writing, the buffer controller 103 determines the data by FRSYNCR, and transmits the data to be recorded on the tape to the recording processing unit 107 via SIN in synchronization with the MPXP supplied from the recording processing unit 105. The data is to be recorded on the tape by the control of the RF amplifier 102 via RDATA.

At this time, the recording / reproducing switching signal PB and the head switching signal SWHPA are generated and supplied by the timing signal generator 106, and the microcomputer 110 and the serial communication interface controller 104 are clocked and controlled by data. The transmission is done.

As described above, the DAT-DS is used to write or read data on a tape by using a digital signal. Recently, the DAT-DS is used as an external memory expansion device of a computer.

In order to exchange data with a computer when using DAT-DS, a signal conforming to a certain time standard requires a control signal for data exchange. In this case, the signal is controlled by a signal generated by a timing signal generator using various signals (for example, MPXP: 48 Hz, FS4: 192 Hz, etc.) used in the DAT-DS driver part as shown in FIG. Since the generators have different characteristics and specifications of the timings and most are custom ICs, it is impossible to analyze each characteristic.

Therefore, in order to drive the driver of the DAT-DS, signals (STRG, SWHR) for controlling two DSP chips (lead and write) 105 and 107, and RF amplifiers for inputting and outputting data to and from data during recording and playback on a tape 102) (PB, SWHPA) to control the output of the signal amplification and processing from the head, and the DAT-DS reads or writes data in units of 2880 words at 90 ° rotation of the drum. Therefore, a buffer controller 103 (RAM-Controller) is required, and the data is transferred from the recording and reproducing processing units 105 and 107. In order to perform the transfer, the first word of data (Wo) ), Reference signals FRSYNCP and FRSYNCR for determining the position of?

However, the conventional timing signal generator is not one-chip, but consists of TTL, which is complicated in configuration and occupies a large system area.

Therefore, an object of the present invention is to stabilize the driving of the mechanism through the servo circuit by the control signal of the microcomputer, and control the two DSP (playback, recording) circuit with the signal of the timing generator so that the drum head is transferred from the tape to the host computer. The present invention provides a circuit that accurately records data and controls timing so that data read through an RF amplifier and data strobe circuit can be accurately transmitted to a host computer.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram according to the present invention, in which the reproduction processing unit 107 receives the FSYNCP and MPXP signals, latches them in the flip-flops DF1 and DF2, and inputs the data to the buffer controller 103 for the first time of the input data word 2880. The first processing means for generating a reference signal to determine the position of the word (Wo) and the recording of the recording processing portion 105 by latching the NAND gate NA5 which receives the SWHP signal generated by the head servo portion 105. The second means for generating a signal as a reference for the signal output position, the signal of the reproduction / recording selection signal terminal RPSEL and the signal of FayncY of the recording processing unit 105 are latched by the flip-flop DF3 and the AND gate ( The third means for generating the recording / reproducing switching signal (PB) of the RF amplification unit 102 and the FS4 of the recording processing unit 105 through the counter CNT1 through the counter AN2). The counter is counted at the counter and the SWHP signal of the head servo unit 109 is passed through the NOA gate NOR1. Fourth means for inputting to CNT1-CNT3 to decode through inverters N1-N17, AND gates AN1-AN17, and OR gates OR1-OR3, and latching them in the flip-flops DF5 and DF6; Fifth means for generating the RF amplifier 102, the head switching signal SWHPA, and the NAND gates NA1-NA3 by the output of the fourth means and the output of the flip-flop DF3; Inverted by the flip-flop DF14 according to the SYNCR and MPXR signals of 105 and counted by the counters CNT5 and CNT6 through the AND gate AN4 to the inverters N2, N18, AND gate AN4 and deflip. Sixth means for latching in the flop DF5 and generating a reference signal FRSYNCR for determining the position of the first word Wo of the input data 2880 words when data is input from the buffer controller 103 to the write processor 105; The output of the AND gate AN4 of the sixth means is counted by the counter CN8 and inverted by the inverter N3 to be transmitted to the regeneration processor 107. 90 ° to delay consists of a seventh means for generating a signal (STRG) for synchronizing.

Therefore, when a specific embodiment of the present invention is described in detail with reference to FIGS. 1 to 4, the flip-flops DF1 and DF2 in FIG. 2 are operated without reset.

The MPXP (48 의) of FIG. 3B is used as the clock of the deflip-flops DF1 and DF2. When the FSYNCP of FIG. 3A falls, the output stage of the deflip-flop DF1 The output of Q1) is delayed by one clock as in (3c) and input to the data terminal D of the flip-flop DF2, and again by the MPXP 3b, the output of the output terminal Q2 of the flip-flop DF2. One clock of silver is delayed like (3d) and the output of the deflip-flop (DF2) of FIG. ), The output of the FRSYNCP is obtained as (3c) at the output terminal Q of the flip-flop (DF3) as shown in (3e). Get a signal of the form. On the rising edge of this signal, the buffer controller 103 recognizes the Wo position following W2879, like the serial output stage Sout 3f. A signal in the form of -pb or FIG. 4, which is a record and play switching signal of the RF amplifier 102, is required. That is, a delaying signal is generated at a falling edge of the SWHP of (4a) by about 0.16 ms, and a falling edge signal is generated as shown in (4d), and a reversal occurs at a cycle of 7.5 msec. A binary counter CNT1-CNT4, a four-input gate (AN1-AN7), three ora gates (OR1-OR3), and a flip-flop (DF5) are used to generate the signal.

First, input FS4 clock (192㎑ → 5.20μsec) to counter CNT1 to make delay signal of 0.16msec (initial value with counter is to flip-flop (DF4) and noar gate (NOR1) using SWHP. Cleared every 30 msec). When the count value of the counter CNT1 becomes full, it is transferred to the input clock of the counter CNT2 (CNT2? CNT3? CNT4). When the output decoding value of each counter value is matched with Table 1 (eg, C30, C1470, C2910, C4350), 4-input AND gate 1 pulse is generated.

The binary values of the counters (CNT1-CNT4) are as above, and when the counters (CNT1-CNT4) match the decoding values above, each 4-input endgate (AN1-AN17) is output. do. Counting the clock of FS4 30 counts 30 × 5.20μsec = 0.156msec 0.16msec clock is generated or 1440 × 5.20μsec = 7.488msec 7.5 msec, 2910 × 5.20 μsec = 15.132 msec 15.16 msec, 4350 × 5.20 μsec = 22.620 msec A clock of 22.5 msec or the like is generated, and this clock is input to the clock of the flip-flop DF5 via three orifices OR1-OR3 in FIG. Since the flip-flop DF5 is connected to the data terminal D and the output terminal Q, the flip-flop DF5 operates in the form of a T-flip flop in which an inversion occurs every time the clock is input.

Therefore, whenever the outputs of the three oragates OR1-OR3 occur, the flip-flop DF5 is inverted, and the counters CNT1-CNT4 are cleared every 30 msec to repeat the above operation. When the RPSEL PLAY and RECORD selection signal is low, the output signal is output through the AND gate AN5 to keep the -pb signal low.

SWHPA uses -pb (4d) as a clock to configure T-F / F using the flip-flop (DF6) to invert at every rising edge of -pb (4d) to obtain a signal of (4d). This signal is output to the NAND gates NA1-NA2, which are MPX when the RPSEL is high, and has the same shape as the SWHP 4c through SWHP when low.

The SWHR 4b uses a latch circuit using two NAND gates NA4 and NA5 as a signal generated by using a pulse generated when the count value of the counters CNT1-CNT4 becomes 4320. It is set at the fall of SWHP and remains high, but becomes a value of 4320 of the counters CNT1-CNT4. When a pulse is generated, it is reset to generate SWHR and repeat it.

The STRG is a signal that requires a shape as shown in FIG. 5, and is generated using a clock generated when the output of three counters CNT5, CNT6, and CNT8 reaches 2048 as shown in FIG. The output terminal Q of the counter CNT8 uses the FSYNCR 5a and the MPXP 5b to generate a clear signal by using the flip-flop DF4 and the AND gate AN4 to set the signal of the STRG 6b. When the values of the counters CNT5, CNT6, and CNT8 reach 2048, the counters are reset.

That is, the FRSYNCR 5b serves as a reference for determining the position of Wo of the buffer controller 103. After the counters (CNT5, CNT6, CNT8) are cleared by FSYNCR (at rising edge) and the output value of the counts (CNT5, CNT6, CNT8) reaches 718 counting values, the 8-input end (AN4) and the inverter (N2) This signal is inputted to the flip-flop DF5 and delayed by one clock with MPXR (5d) to generate FRSYNCR (5f).

As described above, the DAT-DS can be alternately used during recording and playback using two DSP chips, and the operation of the DSP chip should be synchronized by delaying the drum head by 90 ° after writing. Generate STRG to operate the DSP, and generate FRSYNCR and FRSYNCP, which are the criteria for determining the input / output data of the buffer controller, and the buffer controller determines the position of Wo of the data transmitted from the DSP through the signal. Since the head switching signal SWHPA and the playback / recording switching signal PB of the RF amplification part can be supplied to the generated RF amplification part, there is an advantage that it can be one-chip with a simple configuration.

Claims (1)

In the RF amplification control signal generation circuit of the DAT-DS system having an RF amplifier 102, a recording and playback processor 105, 107, a head servo 129, and a buffer controller 103, the playback processor 107 Receives the FSYNCP and MPXP signals and latches them in the flip-flop (DF1, DF2) to generate a reference signal for determining the position of the first word (Wo) of the input data word (2880) when data is input to the buffer controller (103). One means, second means for receiving a SWHP signal generated by the head servo portion 105 and generating a signal serving as a reference of the recording signal output position of the recording processing portion 105 by a latch of the NAND gate NA5; The signal of the reproduction / record selection signal terminal RPSEL and the signal of Fsynck of the recording processing unit 105 are latched in the flip-flop DF3 and the recording and reproduction switching of the RF amplifier 102 is performed through the AND gate AN5. The third means for generating the signal PB and the FS4 of the recording processing section 105 are inputted to the counter CNT1. The counters CNT2-CNT3 are counted and the SWHP signal of the head servo unit 109 is inputted to the counters CNT1-CNT3 through the NOA gate NOR1 to the inverters N1-N17 and AND gates AN1-AN17. And a fourth means for decoding through the oragates OR1 to OR3 and latching in the flip-flops DF5 and DF6, and the NAND gate NA1 by the output of the fourth means and the output of the flip-flop DF3. -NA3) latches in the flip-flop DF14 in accordance with the fifth means for generating the RF amplifier 102, the head switching signal SWHPA, and the FSYNCR and MPXR signals of the recording processing unit 105. Counting at counters CNT5 and CNT6 via AN4 and latching at inverters N2 and N18, AND gate AN4 and deflip-flop DF5 to data from buffer controller 103 to write processor 105. Sixth means for generating a reference signal FRSYNCR for determining the position of the first word Woo of the input data 2880 words upon input; And a seventh means for counting the output of the gate AN4 at the counter CN8 and inverting it at the inverter N3 to delay the signal 90 ° in the regeneration processor 107 to generate a signal STRG for synchronization. RF amplification control signal generation circuit in a DAT-DS system.