JPH07281999A - Data transfer method and reception circuit - Google Patents

Abstract

PURPOSE:To shorten the time required for data transfer by confirming whether a terminal equipment is just under processing or not corresponding to a busy signal, outputting data from a host device to an I/O port when the terminal equipment stops processing, transferring those data to the terminal equipment and inverting a strobe signal. CONSTITUTION:The host device confirms a busy signal BUSY showing whether the terminal equipment is under processing or not and since the terminal equipment is under processing when the busy signal BUSY is at a high level, the processing of confirmation is repeated until that signal is turned to a low level. When the busy signal BUSY is turned to the low level, data DATA1-DATA8 of one byte are outputted to an I/O port 26 and a strobe signal STROBE-N is inverted for reporting the outputs of the data DATA1-DATA8 to the terminal equipment. Then, the data DATA1-DATA8 for one block are transferred while repeatedly inverting the strobe signal STROBE-N.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer method and a receiving circuit.

[0002]

2. Description of the Related Art Conventionally, when transferring data from a host device to a terminal device, an interface is provided between the host device and the terminal device so that control signals can be transmitted and received and data can be transferred through the interface. It has become. Then, for example, when a Centronics compliant parallel interface (hereinafter referred to as “Centro interface”) is used as one of the interfaces, data is transferred by a processor instruction of the host device.

FIG. 2 is a time chart of the host device in the conventional data transfer method. First, the host device has a busy signal BUS indicating whether the terminal device is processing.
Check Y. When the busy signal BUSY is at a high level (busy state), the terminal device is processing,
The confirmation process is repeated until the busy signal BUSY becomes low level (EVENT # 1).

Next, the host device receives the busy signal BUS.
When Y becomes low level, 1-byte data DATA1
~ DATA8 is output to the I / O port (EVENT #
2) together with data DATA1 to DATA in the terminal device
Strobe signal S to notify that 8 has been output.
Set TROBE-N to low level (EVENT #
3).

1-byte data DATA1 to D
When ATA8 is transferred to the terminal device, strobe signal S
Set TROBE-N to high level (EVENT #
4). In this way, 1-byte data DATA1
The transfer of ~ DATA8 is completed. Then, the transfer is repeated by the number of bytes of the data DATA1 to DATA8 to be transferred.

Usually, in the host device, the transfer procedure of the data DATA1 to DATA8 is controlled by driver software. The procedure will be described with reference to FIG. FIG. 3 is a flowchart showing the operation of the conventional host device. Step S1 The I / O port of the busy signal BUSY is accessed to read the busy signal BUSY. In step S2, it is determined whether the read busy signal BUSY is at high level. If it is at the high level, the process returns to step S1, and if it is not at the high level, the process proceeds to step S3. Step S3 1-byte data DATA1 to DATA
8 is written to the I / O port of data DATA1 to DATA8. In step S4, the strobe signal STROBE-N is set to the low level and the I / O of the strobe signal STROBE-N is set.
Write to port. In step S5, the strobe signal STROBE-N is set to the high level and the I / O of the strobe signal STROBE-N is set.
Write to port. Step S6: It is judged whether or not the transfer of all the data DATA1 to DATA8 is completed. All data DA
If the transfer of TA1 to DATA8 has been completed, the process is terminated, and if the transfer of all data DATA1 to DATA8 has not been completed, the process returns to step S1.

Next, a conventional terminal device will be described.
FIG. 4 is a block diagram of a main part of a conventional terminal device. As shown in FIG, 1 byte eight multiplexers M ₁ ~M ₈ so as to correspond to the data DATA1~DATA8 of are arranged, each of the data DA to each multiplexer M ₁ ~M ₈
TA1 to DATA8 are input. The multiplexers M _{1 to} M ₈ have flip-flops F ₁ to
F ₈ is connected to each latch data LTD1~LTD8 from the flip-flop F ₁ to F ₈ is outputted.

Further, the strobe signal STROBE-
N is input to the flip-flop F1, the output SG1 of the flip-flop F1 is input to the inverter INV and the flip-flop F2, and the output of the inverter INV and the output SG2 of the flip-flop F2 are input to the NAND gate G1. The output SG3 of the NAND gate G1 is the multiplexer M ₁ ~ as the selection signal
It is input to M ₈ and the DMA acknowledge signal D
It is input to the NAND gate G2 together with MAACK-N.
Further, the output SG4 of the NAND gate G2 is input to the flip-flop F3 as a control input and to the OR gate G3.

An internal control signal BUFFUL is output from the inverting output terminal of the flip-flop F3 based on the output SG4, and the internal control signal BUFFUL is input to the flip-flop F4 and the OR gate G3. Then, the flip-flop F4 outputs the DMA request signal DMAREQ-N, and the OR gate G3 outputs the busy signal BUSY. The DMA acknowledge signal DMAACK-N is a flip-flop F5.
And the output of the flip-flop F5 becomes an acknowledge signal ACK-N.

Next, the operation of the terminal device in the conventional data transfer method will be described. FIG. 5 is a time chart of the terminal device in the conventional data transfer method. Normal,
In the terminal device, the strobe signal STROBE-N
There is a mode in which the operation is started at the falling edge and a mode in which the operation is started at the rising edge, and either mode can be selected. In this case, the mode in which the operation starts at the falling edge will be described.

First, when the falling edge of the strobe signal STROBE-N is detected by the NAND gate G1 at the timing t1, the output SG3 of the NAND gate G1 becomes low level, the output SG4 of the NAND gate G2 becomes high level, and the data DATA1 is output. ~ DATA8 is latched, the internal control signal BUFFUL becomes high level, and the busy signal BUSY indicating that the terminal device is processing becomes high level.

Next, when the rising of the internal control signal BUFFUL is detected, the DMA request signal DMAREQ-
N becomes low level, and latch data LTD1 to LTD
8 is DMA-transferred to a RAM (not shown). And D
When the MA transfer is completed and the DMA acknowledge signal DMAAC
When K-N goes low, the internal control signal BUFFU
L becomes low level and DMA request signal DMARE
Q-N goes high.

Subsequently, the acknowledge signal ACK-N for indicating to the host device that the reception of the data DATA1 to DATA8 is completed becomes low level, and the busy signal B is received.
USY goes low and acknowledge signal ACK-
N goes high again. In this way, the reception of the data DATA1 to DATA8 for 1 byte is completed.
Then, every time the falling edge of the strobe signal STROBE-N is detected, reception is repeated by the number of bytes of the data DATA1 to DATA8.

[0014]

However, in the above-mentioned conventional data transfer method, the data DATA1 to DATAD are not used.
Since the transfer procedure of ATA8 is controlled by the driver software, data DATA1 to DATAD
ATA8 cannot be transferred to the terminal device at high speed.
That is, when transferring 1-byte data DATA1 to DATA8 to the terminal device, the processor of the host device must execute the processor instructions of steps S1 to S5 of FIG. Will be long.

It is an object of the present invention to provide a data transfer method and a receiving circuit capable of solving the problems of the conventional data transfer method and shortening the time required for data transfer.

[0016]

Therefore, in the data transfer method of the present invention, the host device confirms by the busy signal whether or not the terminal device is processing, and when the terminal device is not processing, the host device In the device, the data is output to the I / O port to be transferred to the terminal device and the strobe signal is inverted.

On the other hand, in the terminal device, each time the strobe signal is inverted, the received data is latched and the latched data is DMA-transferred. In the receiving circuit of the present invention, the data transferred from the host device is received. An edge detection circuit that detects both edges of the strobe signal and generates an internal control signal, a data latch circuit that receives the internal control signal and latches the received data into latch data, and the internal control In response to a signal, the latch data is set to R
And a DMA request generation circuit for generating a DMA request signal for DMA transfer to AM.

[0018]

According to the present invention, as described above, in the data transfer method, whether or not the terminal device is processing is confirmed by the busy signal in the host device. The data is output to the I / O port, transferred to the terminal device, and the strobe signal is inverted.

On the other hand, in the terminal device, each time the strobe signal is inverted, the received data is latched and the latched data is DMA-transferred. In this case, the rising edge and falling edge of the strobe signal are used for data transfer. In the receiving circuit of the present invention, the data transferred from the host device is received. An edge detection circuit that detects both edges of the strobe signal and generates an internal control signal, a data latch circuit that receives the internal control signal and latches the received data into latch data, and the internal control A DMA request generation circuit for receiving a signal and generating a DMA request signal for DMA-transferring the latch data to the RAM.

In this case, each time the strobe signal is inverted, an edge is detected and an internal control signal is generated. The received data is latched each time the internal control signal is generated, and the latched data is DMA-transferred to the RAM.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 6 is a block diagram of the host device in the embodiment of the present invention. In the figure, 21 is a processor, and 22 is a RAM storing driver software 23 and data DATA1 to DATA8.

The processor 21 reads and executes the instruction of the driver software 23 in the RAM 22. The driver software 23 uses the data DATA1
~ DATA8 is read by the processor 21, and the strobe signal STROBE- connected to the I / O port 26 is read.
The signal is transferred to the terminal device by controlling the signal lines such as N and the busy signal BUSY.

Next, the data D is sent from the host device to the terminal device.
A procedure for transferring ATA1 to DATA8 will be described. FIG. 7 is a time chart of the host device in the embodiment of the present invention. First, the host device confirms a busy signal BUSY indicating whether the terminal device is processing. If the busy signal BUSY is at the high level, the terminal device is processing, so the confirmation process is repeated until the busy signal BUSY goes to the low level (EVENT).
# 1).

Next, the host device sends the busy signal BUS.
When Y becomes low level, 1-byte data DATA1
~ DATA8 is output to the I / O port 26 (EVEN
T # 2) and data DATA1 to DA to the terminal device
The strobe signal STROBE-N is inverted to notify that TA8 has been output (EVENT # 3).

Then, the strobe signal STROBE-
While repeatedly inverting N, one block of data DA
Transfer TA1 to DATA8. In this case, one block consists of multiple bytes, and one block of data DATA
The host device keeps busy signal BUSY indicating whether the terminal device is processing until the transfer of 1 to DATA8 is completed.
Is not checked. Therefore, the data DATA1 to D
The time required to transfer the ATA 8 can be shortened accordingly.

Further, each time the strobe signal STROBE-N is inverted, 1 byte of data DATA1 to DATA is output.
8 are transferred, the rising edge and the falling edge of the strobe signal STROBE-N can be used, and the data DATA1 to DATA can be used.
It is possible to shorten the time required for the transfer of eight.

Therefore, high-speed transfer is possible without adding special hardware to the host device. In this way, one block of data DATA1 to DAT
When the transfer of A8 is completed, the data DA of all blocks
The above process is repeated until the transfer of TA1 to DATA8 is completed.

Data DATA constituting each block
The number of bytes 1 to DATA8 is set in correspondence with the capacity of a reception buffer (not shown) arranged in the terminal device.
The larger the number of bytes of the data DATA1 to DATA8 forming each block is, the more the data can be transferred continuously, but the larger the number of bytes is, the higher the rate at which the buffer area of the reception buffer is lost becomes. When the buffer area of the reception buffer is exhausted, the terminal device will receive the busy signal BUSY.
To the high level to notify the host device. in this case,
The host device suspends the transfer of the data DATA1 to DATA8 until a buffer area of a predetermined amount or more is formed in the reception buffer.

By performing bidirectional communication and notifying the host device of the free space in the buffer area from the terminal device, the data D which constitutes one block in the host device.
The number of bytes of ATA1 to DATA8 can be changed. In this case, the waiting time in the host device can be shortened accordingly. Next, a flowchart of the driver software will be described.

FIG. 1 is a flow chart showing the operation of the host device in the embodiment of the present invention. Step S11: Access the I / O port of the busy signal BUSY to read the busy signal BUSY. In step S12, it is determined whether the read busy signal BUSY is at high level. If it is high level, the process returns to step S11, and if it is not high level, the process proceeds to step S13. Step S13 1-byte data DATA1 to DAT
A8 is the data DATA1 to DATA8 I / O port 2
Write to 6. Step S14: The strobe signal STROBE-N is inverted and written to the I / O port 26 of the strobe signal STROBE-N. Step S15 One block of data DATA1 to DA
It is determined whether the transfer of TA8 is completed. When the transfer of the data DATA1 to DATA8 of one block is completed, the process proceeds to step S15 and the data DAT of one block
If the transfer of A1 to DATA8 has not been completed, the process returns to step S13. Step S16 Data DATA1 to DATA of all blocks
It is determined whether the transfer of DATA8 is completed. When the transfer of the data DATA1 to DATA8 of all blocks is completed, the processing is terminated, and the data D of all blocks is transferred.
If the transfer of ATA1 to DATA8 has not been completed, the process returns to step S11.

Next, the terminal device will be described. FIG. 8 is a block diagram of essential parts of the terminal device in the embodiment of the present invention. As shown in the figure, the terminal device includes a data latch circuit 31 that latches data DATA1 to DATA8 as an interface signal into latch data LTD1 to LTD8, an edge detection circuit 32 that detects both edges of a strobe signal STROBE-N, and And a DMA request generation circuit 33 for generating a DMA request signal DMAREQ-N for DMA-transferring the latch data to a RAM (not shown).
Consists of.

In the data latch circuit 31, 1
Eight multiplexers M ₁ ~M ₈ in response to byte data DATA1~DATA8 are arranged, each of the data DATA1~DATA to each multiplexer M ₁ ~M ₈
8 is input. Then, each multiplexer M _{1 to} M ₈
Flip-flops F _{1 to} F ₈ are connected to the
Each latch data LTD1~LTD8 from the flip-flop F ₁ to F ₈ is outputted.

In the edge detection circuit 32, the strobe signal STROBE-N is input to the flip-flop F11, and the output SG11 of the flip-flop F11 is passed through the buffer 34 to the flip-flop F1.
2 and the output of the buffer 34 and the output SG12 of the flip-flop F12 are input to the AND gate G11.
Entered in.

The output SG of the AND gate G11
13 is further input to the flip-flop F13, and the output SG13 and the output of the flip-flop F13 are input to the OR gate G12. Output SG14 of the OR gate G12 is, it becomes the selection signal of the multiplexer M ₁ ~M _8, becomes the internal control signal BUFFUL.

Further, in the DMA request generation circuit 33, the output SG14 is the DMA acknowledge signal D.
It is input to the NAND gate G13 together with MAACK-N,
The output SG15 of the NAND gate G13 is input to the flip-flop F14, and the output SG16 of the flip-flop F14 is input to the multiplexer M1. And
The DMA acknowledge signal DMAACK-N serves as a selection signal for the multiplexer M1. Further, the output of the multiplexer M1 is input to the flip-flop F15, and the output of the flip-flop F15 becomes the DMA request signal DMAREQ-N.

In the host device, data DATA1 to DAT are checked while checking the busy signal BUSY.
Since A8 is not transferred, busy signal BUSY,
A circuit for generating the acknowledge signal ACK-N or the like becomes unnecessary. Next, the operation of the terminal device in the data transfer method of the present invention will be described. FIG. 9 is a time chart of the terminal device in the embodiment of the present invention.

When the strobe signal STROBE-N is input to the flip-flop F11 (FIG. 8) and the output SG11 of the flip-flop F11 is input to the flip-flop F12 via the buffer 34, the output SG13 of the AND gate G11 changes. The waveform is as shown in the figure. The strobe signal STROBE-N is output by the output SG13.
The rising edge and the falling edge can be detected (strobe STROBE-N-div pulse).

The output SG13 and the output of the flip-flop F13 are input to the OR gate G12, and the output SG14 of the OR gate G12 is input to the internal control signal BUF.
Become FUL. The internal control signal BUFFUL is output to the data latch circuit 31 and the DMA request generation circuit 33, and in the data latch circuit 31, while the output SG14 rises at timing t2, t3, ... data DATA1~DATA8 is latched by the multiplexer M ₁ ~M _8, respectively latched flip-flops F ₁ to F ₈ data L
TD1 to LTD8 are output.

On the other hand, the internal control signal BUFFUL input to the DMA request generation circuit 33 is supplied to the NAND gate G13,
DMA request signal DM via flip-flop F14, multiplexer M1 and flip-flop F15
Outputs AREQ-N and latches data LTD1 to LTD
8 is transferred to RAM by DMA. When the DMA acknowledge signal DMAACK-N indicating the end of the DMA transfer becomes low level, the DMA request signal DMAREQ
-N goes high, and 1-byte data DATA1
The transfer of ~ DATA8 is completed.

Then, the strobe signal STROBE
-N is repeatedly inverted, and the data DATA1 to DATA8 of all blocks are received, and the data DATA
When 1 to DATA8 are DMA-transferred to the RAM, the processing is ended. It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made based on the spirit of the present invention, and they are not excluded from the scope of the present invention.

[0041]

As described above in detail, according to the present invention, in the data transfer method, the host device confirms whether or not the terminal device is processing by the busy signal, and the terminal device is processing. Then, the host device outputs the data to the I / O port, transfers the data to the terminal device, and inverts the strobe signal.

On the other hand, in the terminal device, each time the strobe signal is inverted, the received data is latched and the latched data is DMA-transferred. In this case, the host device does not confirm the busy signal until the transfer of the predetermined number of data is completed. Therefore, the time required for data transfer can be shortened accordingly.

Since the rising edge and the falling edge of the strobe signal are used for data transfer, the time required for data transfer can be shortened accordingly. In the receiving circuit of the present invention, the data transferred from the host device is received. An edge detection circuit that detects both edges of the strobe signal and generates an internal control signal, a data latch circuit that receives the internal control signal and latches the received data into latch data, and the internal control DMA for receiving the signal and DMA-transferring the latch data to RAM
And a DMA request generation circuit for generating a request signal.

In this case, each time the strobe signal is inverted, an edge is detected and an internal control signal is generated. The received data is latched each time the internal control signal is generated, and the latched data is DMA-transferred to the RAM. Therefore, since the rising edge and the falling edge of the strobe signal are used for data transfer, the time required for data transfer can be shortened accordingly.

[Brief description of drawings]

FIG. 1 is a flowchart showing an operation of a host device according to an embodiment of the present invention.

FIG. 2 is a time chart of a host device in a conventional data transfer method.

FIG. 3 is a flowchart showing the operation of a conventional host device.

FIG. 4 is a block diagram of a main part of a conventional terminal device.

FIG. 5 is a time chart of the terminal device in the conventional data transfer method.

FIG. 6 is a block diagram of a host device according to an embodiment of the present invention.

FIG. 7 is a time chart of the host device according to the embodiment of the present invention.

FIG. 8 is a block diagram of a main part of the terminal device according to the embodiment of the present invention.

FIG. 9 is a time chart of the terminal device according to the embodiment of the present invention.

[Explanation of symbols]

 26 I / O Port 31 Data Latch Circuit 32 Edge Detection Circuit 33 DMA Request Generation Circuit BUSY Busy Signal SG11 to 16 Output DATA1 to DATA8 Data STROBEN-N Strobe Signal LTD1 to LTD8 Latch Data DMAREQ-N DMA Request Signal

Front page continued (72) Inventor Hiroshi Sakaino 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Hirohiko Nakazato 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. In-house (72) Inventor Nobuo Wakasugi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (2)

[Claims] 1. (a) The host device confirms by a busy signal whether or not the terminal device is processing,
(B) When the terminal device is no longer processing, the host device outputs the data to the I / O port and transfers the data to the terminal device and inverts the strobe signal. (C) In the terminal device, the strobe signal is A data transfer method characterized in that the received data is latched each time it is inverted and the latched data is DMA-transferred. 2. A receiving circuit for receiving data transferred from a host device, (a) an edge detection circuit for detecting both edges of a strobe signal to generate an internal control signal, and (b) the internal control signal. A data latch circuit that receives and latches the received data into latched data; and (c) a DMA request that receives the internal control signal and generates a DMA request signal for DMA-transferring the latched data to RAM. A receiving circuit having a generating circuit.