KR100266165B1 - Method of accessig dram for processing error correction code - Google Patents

Abstract

PURPOSE: A DRAM access method for an error correction code process is provided to efficiently perform a block code ECC process and adapt a fast page mode to both of inner code and outer code in a block code ECC process. CONSTITUTION: A row address, a row count and a count, and a column address and a column count are initialized to 0, and a first cluster is recorded into a column continuous from a start address. A 1-byte data is recorded into start addresses(0,0) and a column and a column count are increased by 1, and a data of 16-byte corresponding to the first cluster are sequentially recorded. When the column count value is 15, namely, when the recording of the first cluster is ended, the next process is performed. The row address is increased by 7 and the row count is increased by 1, and the second cluster is recorded. The column is decreased by 15 for the second cluster recording, and the column count is cleared to 0. When the row count is 10 after the repeated operation of S2 through S5, namely, when the recording of the 11th cluster is ended, the next process is performed. The count is increased, and the row address is decreased by 70, and the 12th cluster is recorded into the next column of the first cluster. It is checked whether the data are all recorded.

Description

Method of Accessing DRAM for Processing Error Correction Code

The present invention relates to a dynamic random access memory (DRAM) access method, and more particularly, to a DRAM access method capable of efficiently performing error correction code (ECC) processing.

In general, digital recording / storage media such as Digital Video Cassette (DVC), Compact Disc-Read Only Memory (CD-ROM), Digital Versatile Disc (DVD), etc., block-code error correction to increase the accuracy of storage and playback. Code processing (Error Correction Code: hereinafter referred to as ECC) is adopted. Here, the block code refers to an error correction method of grouping data for ECC into a block shape and then performing a specific kind of ECC processing on each of rows and columns. Accordingly, in the above-described block code method, inner encoding / decoding (i.e. code for one row) and outer encoding / decoding (i.e. code for one column) are performed sequentially. Therefore, all data corresponding to the entire block must be stored in the memory.

Fig. 1 shows the configuration of the ECC block adopted in the DVD-RAM system. The ECC block of FIG. 1 is a data region having a size of 172 bytes * 192 rows, and an outer parity code (Outer Parity Code) added to the lower end of the data region with a size of 172 bytes * 16 rows by encoding of a column of data. Inner Parity Code (hereinafter, referred to as PI) added to the right side of the data and PO areas by a size of 10 bytes * 208 rows by encoding of data and PO rows. The area is configured.

The efficiency of ECC processing is governed by how quickly the required data can be read from the memory having the above-described configuration, that is, DRAM.

On the other hand, a typical DRAM provides several methods for reading or writing (ie, accessing) data, which are largely divided into a random access mode and a fast page mode. The random access mode is a method of reading data stored at a specific location designated by a row address and a column address on a DRAM one word at a time or writing a word at that location. . Here, a word refers to a storage unit of a specific DRAM and generally refers to 8-bit or 16-bit data. The fast page access mode is a method of reading or writing a plurality of words having the same row address consecutively.

2 is a timing diagram showing a method of writing data in a fast page mode in a typical DRAM.

First, after generating the low access signal RAS to the DRAM, the low address is applied to the DRAM with a predetermined time difference. Subsequently, the column access signal CAS in a high state is continuously generated, and a column address having a predetermined time difference from the column access signal CAS is successively applied to the DRAM. At this time, by applying the write enable signal in the row state corresponding to the column address to the DRAM continuously, a plurality of words (data 1, data 2, data 3) having the same row address in one ECC block are DRAM. The images are recorded continuously.

On the other hand, if the read enable OE signal in the low state instead of the write enable signal WE is continuously applied to the DRAMDP, data can also be read in the fast lazy mode.

Therefore, in order to increase the efficiency of ECC processing, it is desirable to make good use of the fast page mode as described above. However, the biggest problem in using the fast page access mode in ECC processing is that the mode is applied only to a plurality of words having the same row address. In other words, fast page mode access is not supported for multiple words having the same column address.

Accordingly, when the ECC of the block code method as shown in FIG. 1 is to be processed, only one code of an inner code and an outer code may be read / write using the fast page mode. . Therefore, the other code is forced to use the random access mode, so the efficiency of ECC processing is significantly reduced.

Accordingly, it is an object of the present invention to provide a DRAM access method capable of efficiently performing block code ECC processing.

Another object of the present invention is to provide a DRAM access method in which fast page mode can be used for both inner code and outer code in block code ECC processing.

1 is a block diagram of an ECC block in a conventional DVD-RAM.

2 is a signal timing diagram showing a fast page mode write method of a DRAM.

3 is a diagram illustrating a form in which an ECC block of FIG. 1 is divided using a cluster to apply to an access method according to the present invention.

4 is a flowchart for explaining a DRAM access method according to the first embodiment of the present invention.

5 is a block diagram showing the configuration of a DRAM access device for the DRAM access method of the present invention.

6 is a configuration diagram of an ECC block by the DRAM access method of FIG.

7 is a block diagram of an ECC block according to a second embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

10: data input unit 12: O / I (Outer / Inner) encoder

14: Data MUX (Multiplexer) 16: Controller

18: row address generator 20: column address generator

22: address MUX 24: DRAM control signal generator

26 DRAM 28 data output unit

In order to achieve the above object, the DRAM access method for error correction code processing according to the present invention comprises the steps of sequentially writing the clusters in increasing row address at regular intervals in the i-th column address column, and K clusters Once written, step 2 of sequentially writing at increasing row addresses at regular intervals in the i + 1 < th > column address column; and performing steps 1 and 2 by sequentially increasing the column address column, and repeating the m-th column Sequentially recording clusters up to an address column; and sequentially recording clusters at a row address that is sequentially adjacent to the row address in the i-th column address column and increases at regular intervals. Repeat step 4 and step 4 to repeat the cluster Characterized in that it comprises the five steps to complete the recording.

In addition, the DRAM access method for error correction code processing according to the present invention comprises the steps of sequentially recording clusters in a row address sequentially increasing in the first column address column of the i-th small block, and if K clusters are recorded, Writing the clusters to sequentially increasing row addresses in the column address column sequentially adjacent to the column address column, repeating the steps, and sequentially writing the clusters to the m th column address column; and i + 1 th small block And sequentially recording the clusters in the same manner as in steps 1 and 2, and repeating the above steps to complete recording of the clusters.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

A major feature of the DRAM access method according to the present invention is that the fast page code of the DRAM can be used for both the inner code and the outer code when processing the ECC of the block code method. To make this possible, we first introduce the cluster concept. Here, the cluster refers to a bundle that is accessed at a time when the DRAM is accessed in the fast page mode, and its size may be determined according to a user's needs. For example, the size of the cluster can be set to any value less than or equal to the length corresponding to the maximum section of the fast page mode allowed by DRAM, such as 10 bytes, 20 bytes, and 50 bytes. In the present embodiment, for convenience, 16 bytes and 12 bytes will be described as one cluster.

FIG. 3 illustrates the ECC block illustrated in FIG. 1 by introducing the above-described cluster.

As shown in Fig. 1, one ECC block having a size of 172 bytes * 208 rows is divided into 2288 clusters in total. Here, each cluster is 16 bytes. However, clusters 11, 22, 33, ..., 2288, etc. for the rightmost column of the ECC block have 12 bytes. This is because the PI area in Fig. 3 does not need to be stored in the memory due to the ECC processing structure. In other words, the PI code is added by coding when reading data.

In addition, in order to access the DRAM in the fast page mode during the outer coding as well as the inner coding using the cluster concept described above, the clocksters must be rearranged in a proper manner on the DRAM as shown in FIGS. 6 and 7.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 7.

4 is a block diagram showing the configuration of a DRAM access apparatus for explaining a DRAM access method for ECC processing according to an embodiment of the present invention.

The DRAM access device of FIG. 4 outputs data input from the data input unit 10 or the O / I encoder 12 to the DRAM 16 according to the data input unit 10 and the control signal of the controller 20, or the DRAM ( The data multiplexer 14 (hereinafter referred to as mux) for outputting the data input from the 16 to the O / I encoder 12 and the data input from the data mux 14 according to the control signal of the controller 20. An outer / inner (hereinafter referred to as O / I) encoder 12 and controller 20 for outputting to the data mux 14 or the data output unit 18 by performing outer coding or inner coding, respectively. A row address generator 22 generating a row address according to a control signal of the control signal and outputting it to the address mux 26, and a column address generating a column address according to the control signal of the controller 20 and outputting the column address to the address mux 26. Depending on the generator 22 and the control signal of the controller 20 For access operation according to the address mux 26 which applies the row address from the la row address generator 22 or the column address from the column address generator 24 to the DRAM 16, and the control signal of the controller 20, And a DRAM control signal generator 16 for generating various necessary signals and applying them to the DRAM 16.

5 is a flowchart illustrating a DRAM access method for ECC processing according to the first embodiment of the present invention. This is performed by the control operation of the controller 20 of FIG.

Fig. 6 shows the structure of one ECC block stored in DRAM by the above method. 6 is a two-dimensional representation of 4Mbit (5412K * 8bit) DRAM, in which data is stored in cluster units.

First, in the first step, the row address (hereinafter referred to as a row), row count, count, column address (hereinafter referred to as a column), and column count are initialized to 0, and cluster 1 is recorded in a continuous column from the start address. . In detail, one byte of data is recorded at the start address (0, 0), and 16 bytes of data corresponding to the first clockster are sequentially recorded while increasing the column and the column count by one (second step). When the column count value reaches 15 in this step, that is, when the recording of cluster 1 is completed, the process proceeds to the next step. (Step 3) In the 5th step, increase the Loo by 7 and increase the Loo counter by 1, and then record the Clockster No. 2. The column is reduced by 15 and the column count is cleared to 0 for cluster number 2, and the above steps 2 and 3 are repeated. When the low count reaches 10 by repeating steps 2 to 5, that is, when the recording is completed up to 11 clocksters, the process proceeds to the next step.

In step 8, after increasing the count by 1, the number of rows is decreased by 70, and the return is returned to the first row, and the next cluster, that is, cluster 12, is recorded in the column after cluster 1. To this end, the column count and row count are cleared to zero, and the process is repeated by returning to the second step. When the count reaches 15 (step 6) by repeating steps 2 to 8, it is checked whether all the data has been recorded in the ninth step. If data to be recorded remains, steps 2 to 8 are repeated. When the count reaches 31, that is, when the recording of cluster 352 is completed, the count, row count, and column count are cleared to 0 in step 10, and the next cluster (# 53) is recorded. At this time, the column is reduced to zero, and the row is reduced by 69, and then returns to the second step to record from the second row.

Storing clusters in DRAM in this way has the effect of operating in fast page mode for both inner code and outer code directions.

First, referring to inner coding, in order to perform inner coding of the first row, all clusters 1 to 11 in Fig. 3 must be read from the DRAM. In Fig. 4, clusters 1 to 11 are scattered in various places, but this can be read in the fast page mode by properly controlling the loo address, that is, 16 bytes or 12 bytes of data according to the above-described accent method. . Similarly, in order to perform inner coding of the second row, clusters 12 to 22 must be read, which can also be read in fast page mode by the above-described access method.

Referring to the following outer coding, in order to perform the outer coding of the first column, all 192 bytes of data of B (0,0) to B (191, 0) in FIG. 1 should be read. 3, the first byte of cluster 1, the first byte of clockster 12, the first byte of cluster 23, ..., the first byte of cluster 2102. In the DRAM shown in Fig. 6, since clusters 1, 12, 23, etc. all have the same row address, only the column address is changed appropriately, so that the first byte of each cluster is read in the fast page mode. You can do outer coding.

FIG. 7 illustrates a second embodiment of the DRAm access method according to the present invention, in which the DRAM of FIG. 7 divides the clusters into small blocks and records clusters in increasing order. The DRAM shown in FIG. 7 can also perform data processing using the fast page access mode for both inner coding and outer coding in the same manner as the DRAN of FIG.

As described above, according to the DRAM access method according to the present invention, by grouping and rearranging data in cluster units, inner coding and outer coding can be performed by accessing the DRAM in the fast page mode. Accordingly, efficient ECC processing can be performed.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (8)

A method of recording data sequentially input to a DRAM having n row addresses and m column address columns in cluster units of a predetermined size, wherein the clusters increase the row addresses at regular intervals in the i th column address column. Step 1 of sequentially writing in the step; and in step 2, if K clusters are written in the step; 3 to sequentially perform the steps 1 and 2, repeating the steps, and sequentially record the clusters up to the m th column address column; Cluster at increasing address DRAM access for the error correction code processing, characterized in that it comprises the four steps of sequentially recording the steps and repeating the steps 2 and 3, and the step of repeating the step 4 to complete the recording of the clusters Way. 2. The DRAM access of claim 1, wherein the clustering data is written in the step 1 by sequentially increasing column addresses constituting the i-th column address column in byte units. Way. The method of claim 1, wherein an inner coating is performed by accessing data in the cluster in a fast page mode while controlling a row address so as to increase the predetermined interval at the K cluster units. DRAM access method. The error correction method of claim 1, wherein the data is corrected by accessing the data in the cluster in the fast page mode one byte at a time while controlling the column address to be increased with the cluster interval at the same row address. DRAM access method for code processing. A method of writing data sequentially input to a DRAM composed of small block units having n row addresses and m column address columns in cluster units of a predetermined size, wherein the clusters include the first column address of the i th small block. Step 1 of sequentially writing to the row address sequentially increasing in the column, and if the K clusters are written in the step, write the clusters to the row address sequentially increasing in the column address column sequentially adjacent to the column address column and Repeat step 2 to sequentially record the clusters up to the m th column address column, and sequentially record the clusters in the same manner as steps 1 and 2 in the i + 1 th small block, and repeat this. Complete the recording of the clusters DRAM access method for an error correction encoding process comprising the step of. 6. The DRAM access of claim 5, wherein the data constituting the cluster is recorded in byte units while sequentially increasing the column addresses constituting the first column address column in byte units. Way. 6. The DRAM access method of claim 5, wherein inner coating is performed by accessing data in the cluster in a fast page mode while controlling a row address to sequentially increase the K clusters. The error correction method of claim 5, wherein the data is corrected by accessing the data in the cluster in the fast page mode by one byte while controlling the column address to be increased with the cluster interval at the same row address. DRAM access method for code processing.

Images