KR100265555B1 - Method for fabricating thin film transistor - Google Patents

Abstract

PURPOSE: A method for manufacturing a TFT(thin film transistor) is to easily control resistance value of an LDD(lightly doped drain) region or an offset region using a counter-doping when the TFT is formed with polysilicon. CONSTITUTION: An active layer(42) is formed on a semiconductor substrate(40). The active layer defines a channel region, source/drain regions and the first region between a portion between the channel region and the source region and a portion between the channel region and the drain region. A gate electrode(44) is formed on the channel region of the active layer. A gate insulating layer(43) is interposed in the gate electrode. The first conductive impurity is doped to the source region, the drain region and the first region. The second conductive impurity is counter-doped to the doped source region, drain region and the first region. On the counter-doped source region, the drain region and the first region, the first conductive impurity is counter-doped again.

Description

Method of manufacturing thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, to a method for manufacturing a thin film transistor, in which an LDD region or an offset region can be easily formed using counter-doping. .

The polysilicon thin film transistor has a higher current driving ratio in the on state than the amorphous silicon thin film transistor, but a large leakage current in the off state. Therefore, when the switching element of the pixel portion is formed of a polysilicon thin film transistor, the value of the signal stored in the pixel electrode is changed due to the large leakage current in the off state, thereby reducing the screen display performance of the liquid crystal display device. Therefore, in the case of the polysilicon thin film transistor, a technique of setting the switching element of the pixel portion as an LD or an offset structure has been proposed to solve such a problem.

1A to 1C are views for explaining a method of manufacturing a thin film transistor having an LED structure according to the prior art.

Referring to FIG. 1A, after the buffer film 11 and the active layer 12 are sequentially formed on the insulating substrate 10, the gate electrode 14 is formed on the active layer 12 with the gate insulating film 13 interposed therebetween. do. The active layer 12 is formed by using a polycrystalline silicon layer. An amorphous silicon layer is formed on the complete layer 11, and dehydrogenation and laser processes are performed to crystallize the amorphous silicon, and then photograph the crystallized silicon layer. It can be formed by performing an etching process. In this case, the buffer layer 11 is to prevent impurities from the insulating substrate from penetrating into the silicon layer during the crystallization of the amorphous silicon layer, and is formed using an insulating material such as silicon oxide. The gate insulating film 13 and the gate electrode 14 are formed by conventional deposition and etching techniques.

Referring to FIG. 1B, a photoresist pattern PR for blocking the gate electrode 14 and a portion of the active layer 12 surrounding the gate electrode 14 is formed. Thereafter, an ion doping process using a high concentration of n-type ions is performed on the entire surface to form a source region 12S and a drain region 12D in the exposed portion of the active layer 12.

Referring to FIG. 1C, after removing the photoresist pattern PR, an ion doping process using a low concentration of n-type ions is performed on the entire surface to form an LED region 12L on the undoped active layer 12. At this time, since the source region 12S and the drain region 12D are already in a high concentration n-type ion region n +, there is almost no change in ion concentration in this step of doping n-type ions at low concentration.

However, in the prior art as described above, precise work is required for the process of forming the LED area. This is to form this region to have a predetermined resistance value, which will be described below with reference to FIG.

Figure 2 shows the change in the resistance size according to the doped ion concentration in the polycrystalline silicon and single crystal silicon.

As the concentration of the doped ions increases, the resistance value decreases slowly in monocrystalline silicon, while the resistance decreases in a steep slope in polycrystalline silicon. That is, in polycrystalline silicon, since the change in resistance value is severe compared to the ion concentration doped, the change in resistance value can be increased even if the concentration change of impurities is small. Accordingly, in order to form an impurity region having a predetermined resistance value in polycrystalline silicon, an impurity doping process has to be performed precisely. The LED area of a thin film transistor is usually in the order of several tens of kΩ / □ to several MΩ / □ (0.001Ω · cm to severalΩ · cm), especially hundreds of kΩ / □ (O.O1Ω · cm ~ 1ΩΩcm) In order to form an LED area having a predetermined resistance by performing an ion doping process using a single ion, as in the conventional technique described above, considerable care and precision are required. Do.

The present invention is to provide a thin film transistor manufacturing method that can easily adjust the resistance value of the ion region, in particular, the LED region or the offset region by using the counter doping when forming a thin film transistor using polycrystalline silicon.

The present invention provides a process for forming an active layer on a substrate, the active layer defining a first region positioned between a channel region, a source region and a drain region, between the channel region and the source region, and between the channel region and the drain region; Forming a gate electrode through a gate insulating film on the channel region of the active layer, doping a first conductive impurity into the source region, the drain region and the first region, and selectively forming the first region in the first region Provided is a method of manufacturing a thin film transistor, including a step of counter-doping two conductive impurities.

In this case, the first impurity region may be used as a source region and a drain region in a normal case, and the resistance size of the second impurity region may be appropriately set as the LED region or the offset region.

The present invention also provides a process for forming an active layer on a substrate, the active layer defining a channel region, a source and drain region, a first region located between the channel region and the source region and between the channel region and the drain region. Forming a gate electrode through a gate insulating film on the channel region of the active layer, doping a first conductive impurity into the source region, the drain region and the first region, and doping the first conductive type. Counter doping the second conductive impurity into the source, drain, and first conductive regions, and recounting the first conductive impurity into the source and drain regions that are counter-doped with the first conductive type. It provides a method of manufacturing a thin film transistor comprising a process.

In this case, the second impurity region may be used as a source region and a drain region in a normal case, and the resistance size of the first impurity region may be appropriately set as the LED region or the offset region by setting the resistance of.

1A to 1C are manufacturing process diagrams of a thin film transistor having an LED structure according to the prior art.

2 is a graph showing a change in resistance value according to ion concentration in polycrystalline silicon and single crystal silicon.

3A to 3D are views for explaining a first embodiment of a manufacturing process of an LED structure thin film transistor according to the present invention;

4a to 4d are views for explaining a second embodiment of the manufacturing process of the LED structure thin film transistor according to the present invention.

5a to 5f are views for explaining the type of the LED structure thin film transistor manufactured according to the present invention.

In general, an ion region (hereinafter referred to as [A] region) formed by highly doping n-type ions is an n-type carrier (electron) whose main carrier is derived from n-type ions. However, when the counter doping continues with a high concentration of p-type ions in the [A] region, the number of n-type carriers, which are the main carriers, gradually decreases, and at any point, the p-type carriers (holes) induced by the p-type ions Becomes Then, the number of p-type carriers, which are main carriers, gradually increases as the counter-doping process using p-type ionol is continued. This is due to the combination of n-type and p-type carriers, which results in the disappearance of carrier properties. In this case, when the resistance value is changed in the area [A], the resistance value gradually increases as the number of carriers (in this case, the primary carrier is an n-type carrier) decreases with counter doping. (In this case, the main carrier is a p-type carrier), the number increases again, and the resistance value tends to decrease gradually.

However, in the case of counter doping as described above, the rate of change of the resistance becomes gentle even though the ions of the opposite conductivity type are doped at a large concentration. As such, the large resistance of the ions does not change significantly due to the reduced mobility due to scattering of the carrier. When a large amount of ions are doped into the polycrystalline silicon, this generates a large amount of carriers, but these carriers are scattered in a large amount of ionic particles doped and positioned in the polycrystalline silicon to reduce their mobility. Such a decrease in the mobility of the carrier can lower the rate at which the resistance due to the ion doping is reduced, thereby smoothly controlling the change in the resistance value of the ion region. Therefore, in the case of counter doping, an ion region having a predetermined resistance value can be easily formed.

3A to 3D illustrate a first embodiment of the present invention, and show a manufacturing process diagram of an LED structure thin film transistor.

Referring to FIG. 3A, after the buffer layer 41 and the active layer 42 are sequentially formed on the insulating substrate 40, the gate electrode 44 interposed between the gate insulating layer 43 is formed on the active layer 42. do. The active layer 42 may be formed by forming an amorphous silicon layer on the buffer layer 41, dehydrogenation and laser processes to crystallize the amorphous silicon, and then performing a photolithography process on the crystallized silicon layer. In this case, the complete layer 41 is formed to prevent impurities from the insulating substrate from penetrating into the silicon layer during the crystallization of the amorphous silicon layer, and may be formed using an oxide insulating material such as silicon oxide. The gate insulating film 43 and the gate electrode 44 are formed by conventional deposition and etching techniques.

Referring to FIG. 3B, a high concentration n-type ion region 42H having a first size resistance is formed in the exposed active layer 42 by performing an ion doping process in which the n-type ions are heavily doped on the entire surface. At this time, the n-type ions are doped so that the concentration of the highly concentrated n-type ion region (four tails) is about 10 ¹⁹ to 10 ²¹ / cm 3, which is a range of a typical high concentration ion region.

Referring to FIG. 3C, after the photoresist film is formed on the entire surface, photolithography is performed to form the photoresist pattern PR to expose only the portion defined by the LED area 42L. Subsequently, a portion of the high concentration n-type ion region 42H that is selectively exposed by the photosensitive film pattern PR, that is, the LED region 42L is subjected to ion doping, that is, counter doping, using a high concentration of P-type ions on the entire surface. ) Is converted into a low concentration n-type ion region having a second size of resistance. That is, the doped p-type ion is appropriately doped in the high concentration n-type ion region so that the LED region has a second size of resistance. At this time, the resistance in the LED area (resistance of the second size) is made larger than the resistance in the high concentration ion area (resistance of the first size).

In this process, the LED area may be easily formed by counter doping. As described above, carriers induced from p-type ions participating in counter doping in the n-type ion region are scattered on the p-type ion particles, thereby reducing their mobility. Such reduction in mobility of the carrier can lower the rate at which the resistance decreases due to ion doping, thereby smoothly controlling the change in the resistance value of the ion region.

Unexplained reference numerals 42S and 42D denote source and drain regions, which are portions of the high concentration n-type ion region that are not counter-doped with p-type ions. As can be seen from the above description, the source region and the drain region have a resistance of a first size.

Referring to FIG. 3D, when the photosensitive film pattern is removed, the cross-sectional structure of the thin film transistor of the LED structure is shown. This structure is similar to the thin film transistor of the conventional LED structure.

4A to 4D illustrate a second embodiment of the present invention, and show a manufacturing process diagram of an LED structure thin film transistor.

Referring to FIG. 4A, after the buffer film 41 and the active layer 42 are sequentially formed on the insulating substrate 40, the gate electrode 44 is formed on the active layer 42 with the gate insulating film 43 interposed therebetween. The active layer 42 is formed by forming an amorphous silicon layer on the buffer film 41, dehydrogenation and laser processing to crystallize the amorphous silicon, and then performing a photolithography process on the crystallized silicon layer. In this case, the complete layer 41 is formed to prevent impurities from the insulating substrate from penetrating into the silicon layer during the crystallization of the amorphous silicon layer, and may be formed using an oxide insulating material such as silicon oxide. . The gate insulating film 43 and the gate electrode 44 are formed by conventional deposition and etching techniques.

Referring to FIG. 4B, the exposed active layer 42 is doped in high concentration by performing an ion doping process in which the n-type ionol is doped in high concentration on the front surface. At this time, the n-type ionol can be doped to about 10 ¹⁹ to 10 ²¹ / cm 3, which is a range of a typical high concentration ion region. Reference numeral 42H, which is not described, denotes an active layer portion which is heavily doped with n-type ions.

Referring to FIG. 4C, four active layer portions doped with high concentrations of n-type ions by performing ion doping, that is, counter-doped, with high concentrations of p-type ions are formed on the entire surface thereof. Switch to) At this time, as described above, the concentration of the p-type ion is determined to be a value for the LED region can have a predetermined resistance value, the concentration can be changed according to the manufacturing conditions (at this time, the resistance of the LED region Is the size of the first resistor).

As described above, carriers induced in p-type ions participating in counter-doping are scattered on p-type ion particles and their mobility is reduced. Such a decrease in the mobility of the carrier can lower the rate at which the resistance due to the ion doping decreases, thereby smoothly controlling the change in the resistance value of the ion region. Therefore, the present invention has an advantage that the LED area can be easily formed by counter doping.

Referring to FIG. 4D, after the photoresist film is formed on the entire surface, a photolithography process is performed to form the photoresist pattern PR covering the portion defined by the LED region 42L and the gate electrode 44. Subsequently, an ion doping process using a high concentration of n-type ions is performed on the entire surface, so that the source region 42S and the drain having a high concentration n-type ion region are selectively exposed to a portion selectively exposed by the photosensitive film pattern PR among the low concentration n-type ion regions. The area 42D is formed. The resistance of the source region 42S and the drain region 42D has a second resistance size smaller than the first resistance size.

Then, when the photoresist pattern is removed, a thin film transistor showing the cross section shown in the first embodiment is manufactured.

In the above-described first and second embodiments of the present invention, a high concentration of n-type ion regions is formed first, followed by counter-doping with high concentration of p-type ions to form a low concentration of n-type ion regions. By the way, according to the concentration of the ion-doped ions, it is possible to manufacture a thin film transistor having a variety of LED structures according to the type of ions to be ion-doped first. 5A to 5F show various embodiments. (In the drawings below, the structure of the thin film transistor is the same as that shown in Figs. 3D and 4D, and only the source and drain regions and the LED region are shown. Since it is easy to describe embodiment of the present invention, the reference numeral is omitted.

Referring to Fig. 5A, the description thereof is omitted because it is a result of the above-described embodiment.

Referring to FIG. 5B, in the process of doping p-type ions, which are counter doping processes in the above-described first and second embodiments, at high concentration, an n-type carrier which is initially doped with n-type active layer is almost canceled. Doping the p-type ion to a concentration sufficient to produce a thin film transistor having an offset structure, as shown in the figure.

Referring to FIG. 5C, in the process of doping at a high concentration of p-type ionol, which is a counter-doping process in the above-described first and second embodiments, the n-type carrier that is initially doped with n-type active layer is offset. Rather, when the p-type ion is doped at a concentration such that the p-type carrier induced by the p-type ion becomes the main carrier, as shown in the drawing, a thin film transistor having a low concentration of the p-type ion region as an LED region can be manufactured.

Referring to FIG. 5D, if the process proceeds in the same order as the fabrication process in the first and second embodiments described above, and the doping is performed by changing n-type ions and p-type ions, as shown in the drawing, a high concentration p-type ion region A thin film transistor having a source region and a drain region and a low concentration p-type ion region as an LED region can be manufactured.

Referring to Fig. 5E, the process proceeds in the same order as the fabrication process in the first and second embodiments described above, except that the n-type ions and the p-type ions are doped, but the counter-doping process almost cancels the p-type carriers. Doping n-type ions at a concentration sufficient to produce a thin film transistor having an offset structure, as shown in the figure.

Referring to FIG. 5F, the process proceeds in the same order as the fabrication process in the above-described first and second embodiments, except that the n-type ions and the p-type ions are doped, but the p-type carrier is canceled in the counter-doping process. On the contrary, when the n-type ions are doped at a concentration such that the n-type carriers induced by the n-type ions become the main carrier, as shown in the drawing, a thin film transistor having a low concentration of the n-type ion region as the LED region can be manufactured. .

As described above, the present invention can easily form an LED region or an impurity region having a predetermined resistance size by using a moderate resistance change rate of the portion to be counter-doped. Thus, in the case of counter doping, the resistance is much more elastic in the resistance control than in the ion area control by the number of carriers.

In the present invention, it is easy to control the resistance value of the ion region when forming the ion region of the thin film transistor. In particular, since the resistance change rate is gentle, the LED area or the offset area can be easily formed.

Claims (12)

(Correction) forming an active layer on the substrate, the active layer defining a first region located between a channel region, a source region and a drain region, between the channel region and the source region, and between the channel region and the drain region; Forming a gate electrode through a gate insulating film on the channel region of the active layer, doping a first conductive impurity into the source region, the drain region and the first region, and selectively forming the first region in the first region A thin film transistor manufacturing method comprising the step of counter-doped two-conducting impurities. (Correction) The method according to claim 1, wherein, as a result of the counter doping, the first region becomes an LED region with respect to the source region and the drain region. (Correction) The method according to claim 1, wherein, as a result of the counter doping, the first region becomes an offset region with respect to the source region and the drain region. The method of manufacturing a thin film transistor according to claim 1, wherein the first conductive dopant is doped to a concentration size of about 10 ¹⁹ to 10 ²¹ / cm 3. (Correction) The method of manufacturing a thin film transistor according to claim 2, wherein, as a result of the counter doping, the source region, the drain region, and the first region have the same conductivity type. (Correction) The method of manufacturing a thin film transistor according to claim 2, wherein, as a result of the counter doping, the source region, the drain region, and the first region have different conductivity types. (Correction) forming an active layer on a substrate, the active layer defining a first region located between a channel region, a source and a drain region, between the channel region and the source region, and between the channel region and the drain region, and Forming a gate electrode on the channel region of the active layer via a gate insulating film, doping a first conductive impurity into the source region, the drain region and the first region, and a source doped with the first conductive type Counter-doping a second conductive impurity in a region, a drain region, and a first conductive region, and recounting a first conductive impurity in a source region and a drain region counter-doped with the first conductive type. Method of manufacturing a thin film transistor comprising. (Correction) The method of manufacturing a thin film transistor according to claim 7, wherein, as a result of the recounter doping, the first region becomes an LED region with respect to the source region and the drain region. (Correction) The method of manufacturing a thin film transistor according to claim 7, wherein, as a result of the recounter doping, the first region becomes an offset region with respect to the source region and the drain region. The method of claim 7, wherein the first conductive impurity ions are doped with a concentration of about 10 ¹⁹ to 10 ²¹ / cm 3. (Correction) The method of manufacturing a thin film transistor according to claim 8, wherein, as a result of the recounter doping, the source region, the drain region, and the first region have the same conductivity type. (Correction) The method of manufacturing a thin film transistor according to claim 8, wherein, as a result of the recounter doping, the source region, the drain region, and the first region have different conductivity types.

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