KR100264721B1 - Training kit for digital circuit design and processor control and utilization - Google Patents

Abstract

PURPOSE: A training kit for designing a digital circuit and controlling a processor is provided to enable a circuit designed by a user to be verified, without need for assembling the designed circuit practically. CONSTITUTION: A processor(3), connected to design logic parts(1,2), performs an arithmetic operation. A control block(4) transmits the design circuit data inputted via a program input part to the design logic parts(1,2), and selects a transmission mode of the design circuit data and a clock frequency in response to the selection of a user clock frequency. A memory block(6), connected to the design logic parts(1,2), is used for implementing a logic that needs a memory and a database such as a lookup table. An input output block(7) inputs and outputs the circuit data formed in the design logic parts(1,2). Switching blocks(5-1,5-2,5-3) switches the design logic parts(1,2), the processor(3) and the input output block(7) to each other. Ports(9,10) utilize eternal input output data.

Description

Training kit for digital circuit design and processor control and utilization

The present invention relates to a digital circuit design method and a training kit for controlling and using a digital circuit, which makes it possible to easily learn and control a digital circuit design method and a processor through practice without configuring an actual circuit.

With the development of semiconductor technology, as a large number of transistors are integrated on one chip and the operation of the chip is highly developed, it is important to judge the normal operation of the chip on the actual system after designing the digital circuit. As the application specific integrated circuit (ASIC) is expensive, it is important to determine the actual operation of the chip in advance.

Therefore, it is not necessary to simply satisfy the simulation on the circuit design tool, but it is necessary to actually make the designed logic into hardware to check the operation. For this, a hardware emulator or an FPGA ( Field Programmable Gate Array.

Hardware emulator equipment is expensive and not readily available, but FPGAs can be used to verify ASICs at the lab level at a low cost, and there are many processors that are commonly encountered, and many test equipment for controlling and utilizing these processors are available. It is.

However, there is a problem that requires a lot of time and effort to approach and feel some difficulty in utilizing and using the above-described processor.

In addition, the use of the above-described FPGA and processor is a new type of ASIC that enables an electronic circuit designer to design and implement an integrated circuit in the field. Therefore, it is difficult to implement a general-purpose circuit and has a small capacity. We solved the shortcomings and disadvantages of costly ASICs, and built a processor's peripheral interface to make the processor more accessible and understandable.

However, because FPGAs have significantly lower operating speeds and densities than ASICs, applications in which FPGAs are primarily used are used for fast verification and short-cycle ASIC replacement of designed ASICs.

There are many types of FPGAs currently available, including Xilinx, ALTERA, Actel, and Quick Ligic, and the types of processors include Intel's 8051, 8751, Zyllo's Z8O, and many of the same series of processors. Among FPAG, ALTERA's products have more than 50% market share in Korea, and the processors are most commonly used by Intel's 8051 series and Zyllogue's Z8O, so it is effective digital design practice using ALTERA's products and Intel's 8051 series and Gil Logic's Z80 makes training on digital circuit design and processor control and utilization in college courses easier and more hands-on, with training kits to help you control and use this digital circuit design and processor. The purpose is to develop a training kit.

According to the present invention, a beginner or a general company learning digital circuit design at a university does not directly manufacture TTL, logic circuits, or application circuits of a processor according to the purpose of use. The C language and assembly language, which can be used to directly control the processor using the developed user interface, make it easy to understand and acquire digital design methods and processors. In addition to several digital example circuits, it also provides hands-on practice for 10-15 digital application circuits and interface circuits for processor control.

The present invention is a design circuit program input means for inputting the circuit designed by the user using the FPGA design tool of MAX + PLUSII individually or after designing the peripheral interface circuit for controlling and utilizing the processor, and the received TTL level and digital circuit. Logic design block that plays the same role as real circuit, control block for selecting input mode and used clock frequency of design circuit program input means, and input / output block for outputting the circuit configured in logic design block to the outside. And a switching block for input and output for applying the use selection input to the logic design block.

1 is a block diagram of the present invention.

* Explanation of symbols for main parts of the drawings

1: FLEX Logic Design Block 2: MAX Logic Design Block

3: processor 4: control block

5: switching block 6: memory block

7: I / O block 8: External expansion port block

9: VGA port (port connected to the monitor of the computer)

10: PS II port (port that connects to the keyboard or mouse of the computer)

11: download port

12: RS232 port (port for serial communication with computer)

13: Clock Generation Block 14: EPROM

15: PROM

The present invention provides a logic design block (1, 1), which uses a FPGA design tool of MAX + PLUSII of ALTERA and performs a role as a circuit composed of an actual circuit consisting of an interface circuit for a TTL level or a digital logic processor. 2) a control block 4 for transmitting a user-designed circuit to the logic design blocks 1 and 2 and selecting a clock frequency to be used;

A control block 4 for transmitting a user-designed circuit to the logic design blocks 1 and 2 and selecting a clock frequency to be used;

Input / output blocks (7) for inputting / outputting user circuits entered in the logic design blocks (1, 2),

A switching block 5-1 for input / output control for setting a data address line,

A memory block 6 used when a logic such as a database related logic or a look up table is implemented when the logic design block 1, 2 is used,

A download port 11 using a byte blaster for transmitting a circuit designed by a user to a logic design block (1, 2) through a personal computer;

EPROM 14 used for independent control without a personal computer in a parallel ROM for transferring a circuit designed by a user to the logic design blocks 1 and 2,

PROM (15) which is exclusive ROM of ALTERA company,

This is achieved by having an external expansion port block 8 that extends the input and output of the logic design blocks 1 and 2.

In addition, the present invention includes a power switch for selecting power on / off together with a power jack for receiving power from a power adapter, and RS232C 12 for bidirectional communication and interface with a personal computer.

In the present invention, the logic design block (1) is composed of SRAM Base and is the most important block in which a user-written program is executed by using the FPGA design tool of MAX + PLUSII. -4 is built in and is housed in 1,344 registers and a 12K RAM bit block.

The logic design block (2) of the present invention is composed of EPROM Base and is the most important block in which a user-written program is executed using the FPGA design tool of MAX + PLUSII. The EPM7128LC84 can accommodate approximately 2,500 XOR gate logics. -10 is installed and 128 registers are built in.

The logic design block (1) can be designed for up to 40,0000 Gates and contains 2,576 registers and 16K RAM bit blocks.

In the logic design block (1), the total number of input / output pieces that can be used by the user is 134, all of which can be connected to the processor, the switching block, and the external expansion port block.

In the logic design block (2), there are a total of 68 input / output pins available to the user, all of which can be connected to the processor's switching block and external expansion port block.

The control block 4 transmits the circuit designed by the user to the logic design blocks 1 and 2 and selects the clock frequency to be used. The selection of the transmission mode and the clock frequency of the design circuit are performed by the control block 4. To be selected.

Here, the clock uses an 80MHz oscillator, and the switch operation enables the generation of a frequency that meets the user's needs and the selection of the external clock frequency (CLK-EXT).

According to the present invention, the operation mode of the training kit for digital circuit design and processor control and utilization includes a byte blaster mode when directly controlled by a personal computer, a passive paraller synchronous mode (PPS) when controlled by parallel ROM, and a built-in ROM. There is an EPC1 mode when controlling with a control block.

First, the byte blaster mode is a mode in which a circuit designed on MAX + PLUSII, an exclusive ALTERA tool, is directly implemented in the logic design block (1, 2) through the download port 11 using the byte blaster. This is the fastest and easiest way to implement in logic design blocks (1, 2).

However, this method cannot be used without the personal computer since the personal computer must be connected to the download port 11 using the byte blaster.

Next, the PPS mode is implemented by transferring data stored in the EPROM 14 to the logic design block 1 in parallel, and can be implemented with the EPROM 14 without a personal computer. A ROM writer should be provided to store the designed data.

Since the PPS mode can be implemented using the EPROM 14 in which user-designed circuits are stored, a personal computer is not required, but a ROM writer must be provided.

In addition, the EPCI mode requires a ROM writer that stores data in ALTERA's dedicated ROM, PROM (15) .In the case of the Byteblaster mode, it is inconvenient to reload when power is turned off and on. ) Has the advantage of easy operation.

The control block (4) selectively controls the download port (11), EPROM (14), PROM (15) to download and clock control to replace the user-designed digital circuit with the actual circuit in the logic design block (1) In the meantime, the clock frequency is selected.

The logic design block 1 uses embedded RAM to implement a user-designed digital circuit, but uses a memory block 6 when a large amount of database related logic or a lookup table is implemented.

In addition, the logic design blocks 1 and 2 are capable of bidirectional communication and interface with the personal computer through the RS232C 12.

In the logic design block (1, 2), the output of the circuit designed by the user is applied to the input / output block (7) through the switching block (5-1) for controlling the input / output, and the input / output block (7) is displayed on the LCD, 7 It consists of eight segments and eight LEDs.

The LCD, 7-segment, and LED of the input / output block 7 are previously selected as output devices.

In addition, the input / output block 7 is a part for the user to input to the logic design block (1, 2) is composed of a 16-bit dip switch and 25 keypads.

The external expansion port block 8 is used when the circuit designed by the user does not match the input / output block 7 or the input / output block 7 in which it is built or a separate interface board is manufactured.

In the present invention, when designing a circuit using a text editor or graphic editor of MAX + PLUSII and using it in the byte blaster mode, the design circuit is loaded to the logic design blocks (1, 2) through the download port (11), and the PPS. When used in the mode, the design circuit is stored in the EPROM 14 using the ROM writer, and when using in the ECP1 mode, the design circuit is stored in the PROM 15 using the ROM writer.

The byte blaster mode, the PPS mode, and the EPC1 mode are set by operating the mode selection switch of the control block 4 as previously set.

The logic design blocks 1 and 2 function as if the circuit designed by the user is configured as an actual circuit and display the result through the input / output block 7 according to the setting of the switching block 5-1.

The present invention can verify the design circuit without actually configuring the circuit designed by the user, and in particular, can verify the control and utilization of digital circuits and processors learned in the university course is an effective invention for education and verification.

Claims (8)

The PLD design tool performs the same function as the program input means for inputting the user-designed circuit into the logic block and the actual circuit including the input TTL level and the digital logic circuit and the circuit for the peripheral interface of the processor. Design block (1,2), the 8051 series or Z80 series of processors (3) connected to the logic design block (1,2) to perform the operation, and the design circuit received through the program input means logic design block (1) 2) control block (4) which selects the transmission mode and the clock frequency of the design circuit by selecting the clock frequency to be used, and implements a logic such as a database and memory such as a lookup table. The memory block 6 connected to the logic design blocks 1 and 2 and the output and input of the circuit configured in the logic design blocks 1 and 2 are made. Is an input / output block (7), a logic design block, a switching block (5-1, 5-2, 5-3) for switching between input / output blocks, and a VGA port (9) for using external input / output; Training kit for digital circuit design and processor control and utilization, comprising a PSII port (10). The design circuit program input unit of claim 1 includes: a download port (11) using a byte blaster for receiving a circuit designed by a personal computer, an EPROM (14) in which user design circuits are stored, and a logic design block (1). Training kit for digital circuit design and processor control and utilization, consisting of PROM (15), a dedicated ROM in. The training kit for digital circuit design and processor control and utilization of claim 1, wherein the processor (3) is configured for its own operation and control and utilization of the processor through logic design blocks (1,2). 2. The logic design block (1, 2) and processor (3), memory block (6), input / output block (7), external expansion port block (8), VGA port (9), PSII port (10). Training kit for digital circuit design and processor control and utilization, configured using switching-only devices that exchange devices. The digital circuit design according to claim 1, configured to select an input mode of the design circuit program input means by setting of the control block 4, while freely selecting a used clock frequency by clock adjustment of the control block 4 And training kits for processor control and utilization. In claim 1, the logic design block (1, 2) is a training kit for digital circuit design and processor control and utilization configured to input and output to the input and output block (7) through a switching block (5-1) for controlling the input and output . 2. The logic design block (1, 2) is characterized in that the memory block (6) and the external expansion port block (8) is provided while the RS232C (12) for interface and bidirectional communication with the personal computer Training kit for digital circuit design and processor control and utilization. 2. The digital circuit design and processor control of claim 1, wherein the logic design blocks 1 and 2 are provided with a VGA port 9 for an external monitor output and a PSII port 10 for an external input. Training kit for use.

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