KR100264381B1 - The test method of high capacity ipc processor board - Google Patents

Abstract

PURPOSE: A method for testing an IPC processor board is provided to offer the interpretation to a tester by testing the hardware functions of the IPC processor board and providing the test result therefor. CONSTITUTION: An SRAM is tested by writing an arbitrary bit value on the SRAM, reading the bit value after 1 second and comparing the read bit value with the written bit value whether these values are conformed to each other. A maintenance bus is tested by transmitting a plurality of packets through the maintenance bus and identifying the packets returned therethrough. An IPC path is tested by transmitting a multiplicity of packets through the IPC path and identifying the packets returned therethrough. A coupling/decoupling sensing is tested by comparing status information of the IPC processor board read from a memory with actual status information thereof. A DPRAM communication is tested by writing an arbitrary bit value on the DPRAM, reading the bit value after 1 second and comparing the read bit value with the written bit value whether these values are conformed to each other.

Description

Test Methods for High Capacity IPC Processor Boards

The present invention relates to a test method of a processor board for inter-processor communication (IPC) used in Personal Communications Services (PCS) systems, and in particular, to test the full hardware functions of a high-capacity IPC processor board. It is about a test program that can be done.

In general, a PCS system has a processor board that manages a node (NODE) in charge of the IPC path and manages a relay line board to a base station. When production of the high capacity IPC processor board for the PCS system is completed, a test is performed to determine whether the produced processor board is operating normally.

Looking at the prior art for this purpose is as follows. 1 is a flowchart illustrating a test method of an IPC processor board according to the related art. As illustrated, a test method of a high-capacity IPC processor board is mainly divided into an IPC path test, a detach / mount detection test, and a dual port random access (DPRAM). Memory) It is divided into communication test.

For the IPC path test, first connect the IPC path node board to the IPC processor board, and then output the packet through the IPC path node node board. By repeating the procedure of looping back and outputting the packet output as described above, it is possible to confirm whether the IPC processor board normally performs the IPC function through the node by observing whether the packet is normally looped back through the node. If the IPC function is normal, it is considered good, and if it is not normal, it is considered bad.

For the unmount / detection test, assign a unique address to the IPC processor board, and then check the mounting status information for that address. By comparing the checked mounting state information with the actual mounting state of the board corresponding to each bit of the mounting state information, it is determined whether the detach / mount detection function is normally performed. If the removal / mounting detection function is normal, it is considered good, and if it is not normal, it is considered bad.

For the DPRAM communication test, a relay board is mounted on a back board on which an IPC processor board is installed, and the IPC processor board continuously reads the DPRAM of the relay board. As a result of reading the DPRAM, it is checked whether the board type, transmission data, reception data and other DPRAM values are normal. If the result of reading the DPRAM is normal, it is determined to be good, and if not, it is determined to be defective.

In the test method of FIG. 1, the IPC path test can be performed only through a board having a node having an IPC path, and it is difficult to ensure the accuracy of the test if the board is not in a normal state.

The detach / mount detection test has to read the memory in byte units to determine the bit position of each board, and to check whether each bit is 1 (hernia) or 0 (mounting). there was.

The DPRAM communication test examines a board type, transmission data, and reception data with respect to byte data read from the DPRAM by giving an address, and wherein each of the examined values is an octet. For example, it is necessary to check whether 52 or 53 is indicated, and furthermore, there is a burden of checking whether the value of inverting the transmission data matches the value of the received data.

Therefore, the above method not only reduces the mass productivity for mass production of the IPC processor board, but also requires testing the IPC processor board using another board (such as an IPC path node board and a trunk line board). There is a problem that the reliability of the test is inferior, and the full function test of the board cannot be performed.

The present invention was devised to solve the problems of the prior art as described above, and it is possible to test all the hardware functions of the high-capacity IPC processor board, and the test results are automatically output on the screen so that the tester can easily test the results. The aim is to provide a test method for high-capacity IPC processor boards that is understood.

1 is a flowchart illustrating a test method of an IPC processor board according to the related art.

2 is a flowchart illustrating a test method of a high capacity IPC processor board according to the present invention.

In order to achieve the above object, a preferred embodiment of the SRAM test method of the high-capacity IPC processor board according to the present invention manages a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and returns to a base station. CLAIMS 1. A method for testing an IPC processor board for managing a trunk line board, the method comprising: a tester instructing a static RAM (SRAM) test of the IPC processor board; Writing an arbitrary bit value into SRAM of the IPC processor board; After waiting for one second, reading the value of the SRAM again; Checking whether a value read from the SRAM matches the written value; Determining that the SRAM of the IPC processor board is normal if the read value is the same as the recorded value, and determining that the SRAM of the IPC processor board is normal; And printing the test result on the screen.

A preferred embodiment of the maintenance bus test method of the high-capacity IPC processor board according to the present invention is an IPC that manages a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and manages a relay line board to a base station. CLAIMS 1. A method for testing a processor board, comprising: a tester instructing a maintenance bus test of the IPC processor board; Generating a plurality of packets for testing a maintenance bus of the IPC processor board; Transmitting the generated packet to a maintenance bus continuously through an SCC2 port of a CPU; Looping back packets sent to the maintenance bus through a backboard; Comparing the returned packet with the generated packet; Determining that the maintenance bus of the IPC processor board is normal if the returned packet is the same as the generated packet; And printing the test result on the screen.

An exemplary embodiment of the IPC path test method of the high-capacity IPC processor board according to the present invention is an IPC processor managing a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and managing a relay line board to a base station. CLAIMS 1. A method for testing a board, comprising: a tester indicating an IPC path test of the IPC processor board; Generating a plurality of packets for testing an IPC path of the IPC processor board; Transmitting the generated packet to the IPC path continuously through the SCC1 port of the CPU; Looping back a packet transmitted on the IPC path through a backboard; Comparing the returned packet with the generated packet; And if the returned packet is the same as the generated packet, screen printing that the IPC path of the IPC processor board is normal.

According to an embodiment of the present invention, there is provided a method for detecting / mounting a high-capacity IPC processor board to manage a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and managing a relay line board to a base station. CLAIMS 1. A method for testing an IPC processor board, the method comprising: a tester indicating a detach / mount detection test of the IPC processor board; Reading unmount / mount state information data for a plurality of IPC processor boards; Printing the read / unmount state information on a screen; Comparing the actual detach / mount state of the plurality of IPC processor boards with the read detach / mount state information data; And if the actual detach / mount state and the detach / mount state information coincide with each other, screen printing may indicate that the detach / mount detection is normal.

In a high-capacity IPC processor board according to the present invention, a preferred embodiment of the DPRAM access test method for a trunk line board is to manage a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and to connect a trunk line board to a base station. A method for testing an IPC processor board, the method comprising: a tester indicating a DPRAM access test of the trunk line board; Determining a location where the relay line board is mounted; Reading the IPC processor board type, transmission data, and reception data stored in the DPRAM using the identified trunk line board position; Checking whether the read data is normal; Determining that the DPRAM access of the relay line board is bad if the read data is not normal; If the read data is normal, writing an arbitrary bit value to the DPRAM; After waiting for one second, reading the data value of the DPRAM again; Confirming that the value read from the SRAM matches the written value; Determining that the DPRAM of the relay line board is normal if the read value is the same as the recorded value, and determining that the DPRAM of the relay line board is bad; And printing the test result on the screen.

The present invention divides the test method of the high-capacity IPC processor board into SRAM test, IPC fest, maintenance bus test, board detach / mount test, and DPRAM communication test with the trunk line board. Proceed the test and display the test result.

Hereinafter, a detailed operation principle of the present invention will be described with reference to the drawings. 2 is a flowchart illustrating a test method of a high capacity IPC processor board according to the present invention. As shown in the drawing, the tester divides the test types into five types to test the high capacity IPC processor board. When the tester selects a test type, the CPU of the IPC processor board performs the test according to a predetermined flow.

The first test is the static RAM (SRAM) test method, the second test is the maintenance bus test method, the third is the IPC path test method, the fourth is the unmount / mount detection test method, and the fifth is the relay board's test method. DPRAM access test method.

Selecting the first test performs an SRAM test of the IPC processor board, which writes a random value, i.e., 1 or 0, to the SRMA for an SRAM test, waits for one second, and then writes the recorded data from the SRAM. Reread At this time, if the read value is the same as the recorded value, the screen is printed OK. If not, it is determined as bad and the screen is printed.

If the second test is selected, 20 packets are generated in 32-byte units and continuously transmitted through the maintenance bus for the maintenance bus test, and the packet is looped back using the back board of the IPC processor board. . The packet is then sent to the maintenance bus through the SCC2 port of the MC68360 CPU.

When the transmitted packet is looped back, the packet returned through the SCC2 port is checked. If the data of the packet returned through the maintenance bus is not deformed and is the same as the previous packet, the test OK is printed on the screen, and if it is not the same, the test OK is determined and the test NOK is printed on the screen.

If the third test is selected, 20 packets are generated in 32-byte units and continuously transmitted through the IPC path for the IPC path test, and the packet is looped back using the backboard of the IPC processor board. At this time, the packet is transmitted to the IPC path through the SCC1 port of the MC68360 CPU.

When the transmitted packet is looped back, the packet returned through the SCC1 port is checked. If the data of the packet returned through the IPC path is not changed and is the same as the previous packet, the test OK is screen printed. If the data is not the same, the test OK is determined and the test NOK is screen printed.

If the fourth test is selected, the IP address of each IPC processor board is polled in a polling manner using an address allocated to obtain the detach / mount status information for the detach / mount detection test of the board. Next, after analyzing the imported / unmounted state information, the board marks the location information on which each board is mounted, and prints the location information on the screen.

For example, if bit '1' means board mounting, bit '0' means board herding, and the data representing unmounting / mounting status information of four IPC processor boards is '1011', the second IPC processor board Determining that all IPC processor boards are mounted except for “IPC Processor Board # 1 = Mounting, IPC Processor Board # 2 = Mounting, IPC Processor Board # 3 = Mounting, IPC Processor Board # 4 = Mounting”. Print the screen.

Next, it is checked whether the detach / mount state information of the imported IPC processor board matches the actual detach / mount state. That is, in the above example, it is checked whether all the IPC processor boards except the second IPC processor board among the four IPC processor boards are mounted. If the removal / mounting state information matches the actual removal / mounting state, the screen prints a test OK, and if it is not the same, it is determined to be defective and screen prints a test NOK.

When the fifth test is selected, for the DPRAM access test of the trunk line board, the relay terminal board grasps the location information on which the trunk line board is mounted in a polling manner, gives the DPRAM address of the respective boards with the determined position information, and provides the DPRAM data, That is, after reading the board type, the transmission data and the reception data, it is checked whether the read DPRAM data is normal. At this time, the board type is a predetermined value, that is, 01010010 or 01010011, and it is checked whether the value inverting the transmission data matches the value of the received data.

If the read DPRAM data is not normal, it is determined to be defective and screen prints a test NOK, and if it is normal, an arbitrary value, i.e., 0 or 1, is written to the DPRAM. After writing an arbitrary value to the DPRAM and waiting for one second, if the value read back from the DPRAM coincides with the recorded value, the test OK is screen printed, otherwise it is judged as bad and the screen NOK is printed.

As described above, when the tester selects an item to be tested, the present invention automatically performs a test of the corresponding item and screen prints the result. Thus, the examiner can reliably determine whether or not it is normal by looking at the last printed screen. In addition, the present invention further reduces the range of error by testing without passing through other boards, and repairing the board is simple and fast.

Therefore, in the present invention, the tester can easily know the test result in testing the high-capacity IPC processor board, thereby increasing the reliability and mass productivity of the board and reducing the error range, thereby simplifying repair.

Claims (14)

A method for testing an IPC processor board for managing a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and managing a relay board to a base station, wherein the tester has a static RAM of the IPC processor board. Instructing a test; Writing an arbitrary bit value into SRAM of the IPC processor board; After waiting for one second, reading the value of the SRAM again; Checking whether a value read from the SRAM matches the written value; And determining that the SRAM of the IPC processor board is normal when the read value is the same as the recorded value, and determining that the SRAM of the IPC processor board is normal, and to determine that the SRAM of the IPC processor board is bad. The method of claim 1, further comprising printing the test result on a screen. A method for testing an IPC processor board for managing a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and managing a relay board to a base station, wherein the tester tests a maintenance bus of the IPC processor board. Indicating; Generating a plurality of packets for testing a maintenance bus of the IPC processor board; Transmitting the generated packet to a maintenance bus continuously through an SCC2 port of a CPU; Looping back packets sent to the maintenance bus through a backboard; Comparing the returned packet with the generated packet; And determining that the maintenance bus of the IPC processor board is normal if the returned packet is the same as the generated packet, and determining that the maintenance bus is normal if it is not the same. Testing method. The method of claim 3, wherein the generating of the packet comprises generating a packet in units of 32 bytes. 4. The method of claim 3 wherein the generating step generates twenty packets. 6. The method of any one of claims 3 to 5, further comprising the step of printing the test results on a screen. A method for testing an IPC processor board for managing a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and managing a relay board to a base station, wherein the tester performs an IPC path test of the IPC processor board. Instructing; Generating a plurality of packets for testing an IPC path of the IPC processor board; Transmitting the generated packet to the IPC path continuously through the SCC1 port of the CPU; Looping back a packet transmitted on the IPC path through a backboard; Comparing the returned packet with the generated packet; And if the returned packet is the same as the generated packet, printing the screen indicating that the IPC path of the IPC processor board is normal and printing the screen if it is not the same. Testing method. The method of claim 7, wherein the generating of the packet comprises generating a packet in units of 32 bytes. A method for testing an IPC processor board that manages a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and manages a relay board to a base station, wherein a tester detects detachment / mounting of the IPC processor board. Instructing a test; Reading unmount / mount state information data for a plurality of IPC processor boards; Printing the read / unmount state information on a screen; Comparing the actual detach / mount state of the plurality of IPC processor boards with the read detach / mount state information data; And screen printing indicating that the detach / mount detection is normal when the actual detach / mount state and the detach / mount state information match, and screen print that the defect is not matched. Test method for unmount / mount detection The method of claim 9, wherein the reading / unmounting status information data is read, using the address in which the removal / mounting status information data is stored, to read the data in a polling manner. De-installation test method. A method for testing an IPC processor board that manages a node (NODE) in charge of an IPC path in a personal mobile communication (PCS) system and manages a relay board to a base station, wherein the tester has a dual port RAM of the relay board. Instructing an access test; Determining a location where the relay line board is mounted; Reading the IPC processor board type, transmission data, and reception data stored in the DPRAM using the identified trunk line board position; Checking whether the read data is normal; Determining that the DPRAM access of the relay line board is bad if the read data is not normal; If the read data is normal, writing an arbitrary bit value to the DPRAM; After waiting for one second, reading the data value of the DPRAM again; Confirming that the value read from the SRAM matches the written value; And determining that the DPRAM of the relay line board is normal if the read value is the same as the recorded value, and determining that the DPRAM of the relay line board is normal, and to determine that the DPRAM of the relay line board is bad. Way. The method of claim 11, wherein the determining of the location where the trunk line board is mounted comprises determining a location where the trunk line board is mounted by using a polling method. The method of claim 11, wherein the reading of the data value of the DPRAM is performed by using an address of the DPRAM of each of the trunk line boards. The method according to any one of claims 11 to 13, further comprising the step of printing the test result on a screen.

Images