KR100263589B1 - Apparatus for recongnizing extension boards connectable to a progammable logic controller - Google Patents

Abstract

PURPOSE: An apparatus for recognizing an expanded board of a programmable logic control device and method thereof are provided to recognize the bus expander automatically and stabilize the recognition of input/output allocation of corresponding address, thereby stabilizing the control operation of the PLC. CONSTITUTION: The device includes a main processor(112) and bus expanders(114,122,132,...,144). The apparatus according to the present invention recognizes individual PLC(programmable logic controller) expanded board which is to be connected to the PLC. The main processor generates allocated address code so as to indicate each PLC expanded board(120,130,...,140) and the generated code is provided to the corresponding PLC expanded board sequentially. The bus expanders provides PLC expanded board recognition information which indicates the existence of the corresponding PLC expanded board with response to the address code to the main processor.

Description

Expansion board recognition device and method of programmable logic controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable logic controller (hereinafter, referred to as a PLC), and more particularly, to an extended board recognition apparatus and method for a PLC that automatically recognizes an expandable bus expansion device in a PLC.

As is well known in the art, a PLC can connect each bus expansion device designed to directly control an input / output device belonging to it without using a separate data link.

The conventional technology in which the main computing unit of the PLC recognizes each bus expansion unit connected to the PLC allows the expansion of the bus expansion unit to be recognized by allocating an address space by using a jumper or a dip switch. have.

However, in the case of recognizing the bus expansion device by the above-described method, the same address space may be repeatedly allocated due to a mistake of the PLC operator. In addition, the PLC operator must designate the expansion device every time the system is initialized. If a problem occurs in the electrical contact of the designated dip switch and jumper, the address space is changed and an error occurs.

Therefore, the present invention has been made to solve the above-mentioned drawbacks of the prior art, and an object thereof is to provide an apparatus for recognizing each PLC expansion board connected to a PLC.

According to the present invention for achieving the object, the device for recognizing each PLC expansion board that can be connected to the PLC generates an address code assigned to designate each PLC expansion board and sequentially provide to the corresponding PLC expansion board And a bus expansion unit for providing the PLC expansion board recognition information for confirming its existence in response to the address code in each PLC expansion board to the main calculation unit.

1 is a block diagram of a device suitable for recognizing a plurality of bus expansion device in the programmable logic control expansion board recognition device according to the present invention,

FIG. 2 is a block diagram illustrating a portion of the bus extension shown in FIG. 1; FIG.

3 is a circuit diagram showing in detail an embodiment of the adder shown in FIG.

4 is a flowchart illustrating a step of recognizing a plurality of bus expansion devices in the programmable logic control expansion board recognition device according to the present invention.

<Description of the code | symbol about the principal part of drawing>

112: main operation unit 114: main board bus expansion unit

122, 132, ..., 142: bus extension 110: main board

124, 134, ..., 144: external input / output unit 120, 130, ..., 140: bus expansion board

31: decoder 32: adder

33: control unit 34: display operation unit

35: display unit

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings.

1 shows a block configuration of a PLC system suitable for recognizing a plurality of bus extensions in accordance with the present invention.

The PLC includes a PLC main board 110 and n PLC expansion boards 120, 130,... 140 of the same configuration connectable to the PLC main board 110.

PLC main board 110 is one main operation unit 112, main board bus expansion unit 114 and the main operation unit for recognizing each PLC expansion board (120, 130, ..., 140) connected to the PLC A data bus D0 providing a data movement path between the 112 and the main board bus extension 114, and an address bus A0 providing address information from the main board bus extension 114 to the main operation unit 112. ), And a control bus C0 for transmitting an active state signal and PLC expansion board recognition information between the main computing unit 112 and the main board bus expansion unit 114.

The first to nth PLC expansion boards 120, 130,..., 140 having the same configuration are respectively corresponding to the first to nth bus extensions 122, 132,..., 142 and the first. To the nth external input / output units 124, 134, ..., 144, and the PLC expansion boards 120, 130, ..., 140 by bus extension cables 116, 126, ... Are interconnected.

External input / output units 124, 134, ..., 144 extend their respective buses through data buses D1, ..., address buses A1, ..., and control buses C1, ... It is connected to the parts 122, 132, ..., 142. In addition, each of the external input / output units 124, 134, ..., 144 has an external input / output port (not shown), such as an external input device such as a sensor, a push button switch, an electronic switch, an electronic valve, an indicator light, or the like. An external output device is connected.

In operation, the main operation unit 112 in the PLC main board 110 generates an address code corresponding to each of the bus expansion units 114, 122, 132, ..., 142 that are expanded, and generates the generated address. The code is provided to the respective bus extensions 114, 122, 132, ..., 142 sequentially corresponding to the corresponding addresses through the bus extension cables 116, 126, .... For example, assuming that a total of eight boards are expandable, including the main board bus extension 114 in the PLC main board 110, the address codes of each board are binary, 000, 001, 010, 011, 100 , 101, 110, and 111 can be allocated to these eight, and these address codes are sequentially assigned signals indicating the PLC main board 110 and the remaining seven PLC expansion boards (120, 130, ..., 140) Used.

The main board bus extensions 114 and the bus extensions 122, 132, ..., 142 in the respective PLC expansion boards 120, 130, ..., 140 are bus extension cables 116, 126,. Receives an address code provided from the main operation unit 112 through ..) and internally performs a logical operation to generate PLC expansion board recognition information indicating its existence. The PLC expansion board recognition information generated in each of the bus expansion boards 120, 130,..., 140 is transmitted to the main operation unit 112, whereby the main operation unit 112 transmits the PLC expansion boards 120, 130,. .., 140 so as to recognize whether the connection.

When the main operation unit 112 recognizes the existence of the corresponding PLC expansion boards 120, 130, ..., 140, the corresponding external input / output units 124, 134 through the bus extension cables 116, 126, ... The control signal including the address of the input / output device connected to the ..., 144 is transmitted to the corresponding PLC expansion board (120, 130, ..., 140).

FIG. 2 is a detailed block diagram showing one of the bus extensions 114, 122, 132, ..., 144 of the same configuration as shown in FIG. 1, for example, the second bus extension 122. As shown in FIG. 31), an adder 32, a control unit 33, and a display operating unit 34.

The adder 32 according to the present invention receives an address code, for example, "1" provided from the main operation unit 112, and adds it repeatedly, thereby generating a bus extension control signal "0". The bus extension device control signal " 0 " generated in the adder 32 is used as a signal for activating the decoder 31.

The decoder 31 is activated by the bus expansion device control signal provided from the adder 32 and transmits an activation state signal to the control unit 33 via the control line 312.

The control unit 33 connects the PLC expansion board recognition information of the first bus expansion board 122 to the display operating unit 34 and the line 212 in response to the activation state signal from the decoder 31. It is transmitted to the main operation unit 112 through). When the main operation unit 112 recognizes the bus expansion board connected to the PLC from the PLC expansion board recognition information, the main operation unit 112 decodes the data through the bus extension control input bus 200 connected to the bus extension cable 116. At 31, address information is provided.

The decoder 31 decodes the address information provided from the main operation unit 112 through the bus expander control input bus 200, and outputs the decoded address information to the first external input / output unit 124. The address information decoded by the decoder 31 is used as a signal for activating the input / output port of the external input / output unit 124.

The display operating unit 34 transmits the PLC expansion board recognition information provided from the control unit 33 to the display unit 35 configured as the display elements of the light emitting diodes (LEDs) or the liquid crystal display elements (LCDs), thereby allowing the operator to perform the first operation. It can be seen that the bus extension 122 is automatically recognized automatically.

Referring to FIG. 3, a detailed circuit diagram of the adder 32 shown in FIG.

At the first input of the NAND gates 402, 404, 406 and the NOR gates 410, 412, 414 of the adder 32, a code “1” provided from the main operation unit 112 is lined 40, 41, 42. Are sequentially input through the second input terminal of the NAND gates 402, 404, 406 and the NOR gates 410, 412, 414. In turn). In addition, a signal " 0 " used as an enable signal is applied to the inverter 408.

"0" and "1" on lines 40 and 44 are output to the value of "1" through NAND gate 402 and back to the value of "1" through NOR gate 410 and NOT gate 416. Is output.

The values of "0" and "1" on the lines 41 and 45 are output as the value of "1" through the NAND gate 404 and are output as "0" through the NOR gate 412.

The values of "1" and "1" on the lines 42 and 46 are output as "0" through the NAND gate 406 and as "0" through the NOR gate 414.

Each "0" output from each NOR gate 412 and 414 is output as "1" through each NOT gate 418 and 420, respectively.

When "0" on the line 43 is input, it is output as "1" through the NOT gate 408.

Meanwhile, "1" output through the NOT gate 416 and "1" output from the NAND gate 402 are output as "1" through the AND gate 422.

"1" output from the NAND gate 404 and "0" output from the NOR gate 414 are output as "0" through the AND gate 424.

Then, "1" output from the NAND gate 404, "0" output from the NAND gate 406, and "1" output from the NOT gate 408 are inputted to the AND gate 426 to "0". Is output.

The above-described values of "0" output from the NOR gate 412, "0" output from the AND gate 424, and "0" output from the AND gate 426 are "1" through the NOR gate 436. Is output as.

A value of "1" output from the NOR gate 436 and a value of "1" output from the AND gate 422 are output as a value of "0" through an exclusive OR gate.

"1" output from the NAND gate 404 and "1" output from the NOT gate 418 are output as a value of "1" through the AND gate 428.

Values of "0" output from the NAND gate 406 and "1" output from the NOT gate 408 are input to the AND gate 430 and output as "0".

A value of "0" output from the NOR gate 414 and "0" output from the AND gate 430 are input to the NOR gate 438 and output as "1".

"1" output from the AND gate 428 and "1" output from the NOR gate 438 are output as "0" through the exclusive OR gate 442.

"0" output from the NAND gate 406 and "1" output from the NOT gate 420 are output as the value of "0" on the line 47 through the AND gate 432.

The value of "1" output from the NOT gate 408 is again output as the value of "0" on the line 48 through the NOT gate 434.

Then, "0" output from the NOT gate 434 and "0" output from the AND gate 432 are output as "0" through the exclusive OR gate 444.

As a result, the logically calculated value in the adder 32 is output as the value of the bus extension control signal " 0 " on the output lines 47, 48 and 49.

Output "0" of the adder 32 is a value that can be obtained by removing the number of ^23-digit code at address "1", that can be obtained by adding the setting code "111", "1000". That is, the adder 32 is configured to logically calculate a 3-bit address code represented by a binary number and a setting code "111" output from the adder 32 without repeating it and output it as "0".

Therefore, when the bus extension control signal "0" output from the adder 32 activates the decoder 31 and the decoder 31 transmits an active state signal indicating that the decoder 31 is activated, the controller 33 controls the controller 33. By transmitting the PLC expansion board recognition information to the main operation unit 112, the main operation unit 112 recognizes the bus expansion unit (114, 122, 132, ..., 144).

A process of recognizing a plurality of bus expansion devices in the programmable logic control expansion board recognition device according to the present invention will be described in detail with reference to FIG. 4.

First, in step 502, the main operation unit 112 in the main board 110 generates an address code corresponding to the corresponding PLC Dean boards 120, 130, ..., 140 and the PLC corresponding to the generated address code. The expansion boards 120, 130, ..., 140 are provided in sequence.

The decoder 31 in the corresponding PLC expansion boards 120, 130, ..., 140 receives the provided address code (step 504).

In step 506, the decoder 31 determines whether the received address code is a bus extension device control signal. If it is determined that the received address code is a bus extender control signal, the process proceeds to step 514 where the decoder 31 is activated by the bus extender control signal, and the control unit 33 receives a signal from the decoder 31. In response to an activation state, the PLC expansion board recognition information is transmitted to the main operation unit 112 to inform that the PLC expansion board is recognized and terminated. Otherwise, the process proceeds to 508 to transmit the address code to the adder 32. (Step 508).

In step 510, the adder 32 adds the received address code and a preset setting code to output a new address code.

In step 512, the new address code output in step 510 is provided back to the decoder 31 to proceed to step 504 described above.

As described above, the present invention can automatically recognize the bus expansion device without an external additional device and stably recognize the input / output arrangement of the corresponding address space, so that the control operation of the PLC can be more stably operated.

Claims (4)

In a device that recognizes each PLC expansion board (120, 130, ..., 140) that can be connected to a programmable logic controller (PLC), Leading edges that are assigned to the PLC expansion board (120, 130, ..., 140) to generate an address code assigned to each of the PLC expansion board (120, 130, ..., 140) sequentially Mountain 112; Bus expansion units 114 and 122 for providing PLC expansion board recognition information to the main operation unit to confirm its existence in response to the address code in the respective PLC expansion boards 120, 130, ..., 140. Expansion board recognition device for a programmable logic control device, including; The method of claim 1, Each of the bus extensions 114, 122, 132, ..., 144, An adder (32) for generating a bus extension device control signal by repeatedly performing logical operations between the address code and the preset code provided to the corresponding expansion board; A decoder (31) activated by the bus expander control signal generated by the adder (32); And a control unit (33) for transmitting the PLC expansion board recognition information to the main operation unit (112) in response to an active state of the decoder (31). The method of claim 1, The address code is an expansion board recognition device of a programmable logic control device, characterized in that the value corresponding to the value of the number of PLC expansion board (120, 130, ..., 140) sequentially expressed. In the expansion board recognition method of a PLC comprising a programmable logic controller (PLC) main board and an expansion board connectable to the PLC main board, Providing each corresponding expansion board with an address code assigned to designate each expansion board connected to the PLC in the main board of the PLC; Generating a bus extension device control signal satisfying a preset value by repeatedly performing a logical operation between the address code and a preset logic code in an expansion board connected to the PLC main board; And providing the generated bus expansion device control signal to the PLC main board to recognize the connection of the expansion board to the PLC main board.