KR100262957B1 - Cross-talk compensation circuit - Google Patents

Abstract

PURPOSE: A crosstalk compensation circuit is provided to discharge the charge amount accumulated in an integrator periodically by using an initiation controller to compensate for a constant common voltage. CONSTITUTION: The circuit includes a differential amplifier(12), a charge accumulator(14), an adder and an initiator. The differential amplifier receives the first common voltage applied on a common electrode of an LCD panel and the second common voltage which was applied on the common electrode previously and amplifies the difference between the first and second common voltages. The charge accumulator accumulates the amplifier output signal from the differential amplifier and outputs the result. The adder receives the output signal from the charge accumulator and a predetermined common voltage initial value to generate the first common voltage with response to the signals. The initiator is connected to the charge accumulator so as to initialize the accumulator value of the charge accumulator.

Description

Circuit for Crosstalk Compensation

The present invention relates to a crosstalk compensation circuit, and more particularly, to a crosstalk compensation circuit for compensating a uniform common voltage by periodically discharging the amount of charge accumulated in an integrator of a crosstalk compensation circuit using an initialization controller, and a liquid crystal display device using the same. It is about.

In general, the liquid crystal panel displays an image corresponding to the video signal on the screen by adjusting the transmission amount of the light beam from the light source according to the video signal. To this end, the liquid crystal panel is composed of a plurality of liquid crystal cells arranged in a matrix form and a plurality of control switches for switching the video signal to be supplied to each of these liquid crystal cells. In addition, the liquid crystal panel driving apparatus for driving the liquid crystal panel should apply a pixel signal corresponding to each of the plurality of liquid crystal cells. In addition, the liquid crystal panel driver changes the video signal to have a positive (+) and a negative (−) polarity based on a constant voltage level in order to lower the driving voltage of the liquid crystal panel. Accordingly, the liquid crystal panel driver must supply voltage signals for controlling the control switches included in the liquid crystal panel, and additionally supply a common voltage V _COM having a constant voltage level to the liquid crystal cells. In addition, the liquid crystal panel compensates for the common voltage V _COM by using a crosstalk compensation circuit.

A crosstalk compensation circuit according to the related art will be described with reference to FIGS. 1 to 2.

1 is a block diagram of a crosstalk compensation circuit according to the prior art. In the configuration of FIG. 1, the crosstalk compensation circuit according to the prior art receives a differential signal of a common voltage V _COM as an input. (2), an integrator 4 for applying the output signal of the differential amplifier to its input, and an adder 6 for inputting the output signal of the integrator 4 and the common voltage control signal. The input terminal of the differential amplifier 2 receives the common voltage V _COM1 before being applied to the panel 8 and the distorted common voltage V _COM2 applied to the panel 8 to input the difference signals between V _COM1 and V _COM2 . By amplifying and outputting the difference signal. In the integrator 4, the signal output from the differential amplifier 2 is maintained to have a proper amount for a predetermined period. In the adder 6, the horizontal common signal crosstalk of the liquid crystal panel is applied by applying the compensated common voltage V _COM , which is output by adding the voltage having the appropriate magnitude and the common voltage control signal output from the integrator 4, to the liquid crystal panel. To improve.

FIG. 2 is a detailed circuit diagram of FIG. 1, wherein the crosstalk compensation circuit according to the related art in the configuration of FIG. 2 includes a third resistor R3 connected between the first node 11 and the seventh node 17, and FIG. The inverting terminal of the first operational amplifier A1 connected to the seventh node 17, the second resistor R2 located between the panel 8 and the eighth node 18, the eighth node 18 and the ground; A differential amplifier having a first resistor connected between the voltage source GND, a fourth resistor R4 and a first capacitor C1 connected in parallel between the seventh node 17 and the second node 12; 2) is provided. The common constant voltage V _COM1 is applied to the seventh node 17, and the distorted common voltage V _COM2 output from the panel 8 is applied to the eighth node 18, so that the first operational amplifier A1 is applied. The difference signal between V _COM1 and V _COM2 is amplified to an appropriate size and output, and the fourth resistor R4 and the first capacitor C1 return their own output signal to the seventh node 17. As a result, the differential amplifier 2 extracts the difference of the common voltage V _COM2 distorted by the panel 8.

In addition, the crosstalk compensation circuit according to the related art includes a fifth resistor R5 connected between the second node 12 and the third node 13, and a third node 13 and the base voltage source GND. An integrator 4 having a connected second capacitor C2 is provided. Referring to the operating principle of the integrator 4, when the time constant τ having the form of the product of the resistor R and the capacitor C is sufficiently large for the signal period, the output signal is a voltage waveform obtained by integrating the input signal. Indicates. The time constant may be adjusted according to the values of the fifth resistor R5 and the second capacitor C2, and the capacitor is used as a voltage storage means for storing a voltage having an appropriate magnitude for a predetermined time. Meanwhile, charges are continuously accumulated in the voltage accumulating means, that is, the second capacitor C2 by a feedback circuit formed internally.

In addition, the crosstalk compensation circuit according to the related art includes a sixth resistor R6 connected between the third node 13 and the fourth node 14, and a fourth node 14 and the fifth node 15. A seventh resistor R7 connected to the eighth resistor R8 connected between the common voltage control signal line and the fourth node 14, and a second operational amplifier A2 connected to the fifth node 15; ), A non-inverting terminal of the second operational amplifier A2 connected to the reference voltage line, and a ninth resistor R9 connected in parallel between the fifth node 15 and the first node 11. And a tenth resistor R10 connected between the third capacitor C3, the sixth node 16 and the ninth node 19, and the first and second transistors connected to the ninth node 19. The base of Q1 and Q2, the collector of the first transistor Q1 connected to the high potential supply voltage Vcc, the emitter and the second transistor of the first transistor Q1 connected to the first node 11; Collector of second transistor Q2 connected to emitter at Q2 and low potential supply voltage (-Vcc) The provided with an adder (6) having. The sixth and seventh resistors R6 and R7 divide the compensation voltage and the common voltage control signal output from the integrator according to the ratio of the two resistance values. The two signals via the voltage divider resistors R6 and R7 are divided according to respective voltage division ratios and then input to the inverting terminal of the second operational amplifier A2. In addition, the reference voltage Vr is input to the non-inverting terminal of the second operational amplifier A2, and the second operational amplifier A2 differentially amplifies the signals input to its non-inverting terminal and the inverting terminal. . Meanwhile, the push-pull amplifier implemented with the first and second transistors Q1 and Q2 is a booster circuit for increasing the output current. In addition, the ninth resistor R9 and the third capacitor C3 allow the output signal of the push-pull amplifier to be fed back in order to reduce distortion of the output voltage waveform. Thus, the adder 92 adds the voltage compensated in the integrator 4 and the common voltage V _COM control signal to apply the appropriate waveform to the liquid crystal panel 8.

However, in the crosstalk compensation circuit as described above, since the charge direction accumulated in the capacitor of the integrator is continuously accumulated by the feedback circuit formed internally, distortion is generated by the amount of charge accumulated in advance, so that proper compensation is not achieved. In particular, increasing the ratio added to the panel causes crosstalk of the vertical synchronizing signal, which adversely affects the image quality of the liquid crystal panel.

Accordingly, an object of the present invention is to provide a crosstalk compensation circuit for compensating for a uniform common voltage by periodically discharging the amount of charge accumulated in an integrator of a crosstalk compensation circuit using an adjustable initialization controller and a liquid crystal display device using the same. .

1 is a block diagram of a crosstalk compensation circuit according to the prior art.

2 is a detailed circuit diagram of FIG.

3 is a block diagram of a crosstalk compensation circuit according to the present invention.

4 is a detailed circuit diagram of FIG.

5A is a logic circuit diagram of an initialization controller.

FIG. 5B illustrates another embodiment of FIG. 5A.

6 is a signal waveform diagram of FIG. 5A.

* Explanation of symbols for main parts of the drawings

2, 12: differential amplifier 4, 14: integrator

6, 16: adder 8, 18: liquid crystal panel

20: initialization control unit 22: delay unit

C1 to C13: Capacitors A1 to A4: Operational Amplifiers

Q1 to Q4: Transistor VR1, VR2: Variable resistor

I1, I2: Inverters EX1 to EX4: Exclusive logical sum

Vr: reference voltage Vcom: common voltage

V1: Initialization Control Signals R1 to R20: Resistance

In order to achieve the above object, the crosstalk compensation circuit of the present invention receives the first common voltage applied to the common electrode of the liquid crystal panel and the second common voltage already applied to the common electrode, respectively, and the first and second common electrodes. A differential amplifier for amplifying and outputting a difference value of? A charge accumulator for accumulating the amplified output signal from the differential amplifier and outputting the accumulated amplified output signal; An adder for receiving an output signal of the charge accumulator and a predetermined initial value of the common voltage, respectively, and generating and outputting a first common voltage corresponding to the two signals; And initialization means connected to the charge accumulator to initialize the amount of charge accumulated in the charge accumulator.

In addition, the liquid crystal display device of the present invention receives a predetermined liquid crystal panel for receiving the predetermined data, the first common voltage applied to the common electrode of the liquid crystal panel and the second common voltage already applied to the common electrode, respectively, A differential amplifier for amplifying and outputting a difference value between the first and second common voltages; A charge accumulator for accumulating the amplified output signal from the differential amplifier and outputting the accumulated amplified output signal; An adder for receiving an output signal of the charge accumulator and a predetermined initial value of the common voltage, respectively, and generating and outputting a first common voltage corresponding to the two signals; And an initialization control unit connected to the charge accumulator to initialize the amount of charge accumulated in the charge accumulator, and an initialization control unit connected to the initialization means to periodically control the initialization operation of the initialization means.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

With reference to Figures 3 to 6 will be described a preferred embodiment of the present invention.

FIG. 3 is a block diagram of a crosstalk compensation circuit according to the present invention. In the configuration of FIG. 3, the crosstalk compensation circuit according to the present invention includes a differential amplifier receiving a difference signal of a common voltage V _COM2 as an input. 12), an integrator 14 having a switch for applying an output signal of the differential amplifier 12 to its input and discharging the charge accumulated therein; and an output signal and common voltage control of the integrator 14; The adder 16 which inputs a signal is provided. Since the operating states of the differential amplifier 12 and the adder 16 are the same as those in FIG. 1, detailed descriptions thereof will be omitted. On the other hand, in the integrator 14, the signal output from the differential amplifier 12 is maintained to have an appropriate amount of magnitude for a predetermined period of time, and then the charge accumulated by the switching action is discharged.

4 is a detailed circuit diagram of FIG. 3. In the configuration of FIG. 4, the crosstalk compensation circuit according to the present invention includes a thirteenth resistor R13 connected between an eleventh node 21 and a seventeenth node 27, and An inverting terminal of the third operational amplifier A3 connected to the seventeenth node 27, a twelfth resistor R12 positioned between the liquid crystal panel 18 and the eighteenth node 28, and an eighteenth node 28; The eleventh resistor R11 connected between the base voltage source GND and the fourteenth resistor R14 and the eleventh capacitor C11 connected in parallel between the seventeenth node 27 and the twelfth node 22 are connected to each other. And a differential amplifier 12 having. Since the operation state and function of the differential amplifier 12 are the same as those of FIG. 2, detailed description thereof will be omitted.

In addition, the crosstalk compensation circuit according to the present invention is provided between the sixteenth resistor R16 connected between the thirteenth node 23 and the fourteenth node 24, and between the fourteenth node 24 and the fifteenth node 25. A seventeenth resistor R17 connected to the sixteenth resistor R18 connected between the common voltage control signal line and the fourteenth node 24, and a fourth operational amplifier A4 connected to the fifteenth node 25; ), The inverting terminal of the fourth operational amplifier A4 connected to the reference voltage line, the nineteenth resistor R19 connected in parallel between the fifteenth node 25 and the eleventh node 21, and The thirteenth capacitor C13, the twentieth resistor R20 connected between the sixteenth node 26 and the nineteenth node 29, and the third and fourth transistors Q3 connected to the nineteenth node 29. , The collector of the third transistor Q3 connected to the base of Q4, the high potential supply voltage Vcc, the emitter and the fourth transistor (of the third transistor Q3 connected to the eleventh node 21). Fourth transistor connected to the emitter of Q4) and the low potential supply voltage (-Vcc) It includes an adder 16 having a collector of the emitter (Q4). Since the operation state and function of the adder 16 are the same as those of FIG. 2, detailed description thereof will be omitted.

In addition, the crosstalk compensation circuit according to the present invention includes a fifteenth resistor R15 connected between the twelfth node 22 and the thirteenth node 23, and the thirteenth node 23 and the base voltage source GND. An integrator 14 having a connected twelfth capacitor C12 and an initialization means S1 is provided.

The time constant may be adjusted according to the values of the fifteenth resistor R15 and the twelfth capacitor C12, and the twelfth capacitor is used as a voltage accumulating means for storing a voltage having an appropriate magnitude for a predetermined time, and the initialization means. When S1 is turned on, a discharge path of the twelfth capacitor is formed to discharge the charge accumulated in the twelfth capacitor 12 to initialize the accumulated charge in the voltage storage means. On the other hand, when the initialization means S1 is off, charges are stored in the twelfth capacitor C12. In addition, the initialization means performs on or off by the initialization control signal V1. The initialization control signal V1 is generated by the initialization controller 20, and may control the discharge time of the amount of charge charged in the capacitor by the initialization controller 20. As a result, the amount of charge accumulated in the voltage storage means can be initialized by the switching operation of the initialization means, and the common voltage V _COM compensated by the crosstalk compensation circuit can be applied to the liquid crystal panel to properly compensate for the crosstop. .

FIG. 5A illustrates a logic circuit of an initialization control unit. In the configuration of FIG. 5A, the initialization control unit of the present invention is connected to a common voltage (V _COM ) control signal line to delay and output a common voltage control signal by a predetermined time. 22) and frequency integer multiplication means for applying an output signal of the delay unit and the common voltage control signal to generate an integer multiple of frequency.

Referring to the configuration of the delay unit, the input terminal of the first and third exclusive OR circuits EX1 and EX3 connected to the common voltage control signal line and the supply voltage VDD, the output terminal of the first exclusive OR circuit EX1, and the twenty-first embodiment are described. The first variable resistor VR1 connected between the nodes 31 and the thirty-first capacitor C31 connected between the twenty-first node 31 and the base voltage source GND and the twenty-first node 31 are connected to each other. A second exclusive OR circuit EX2 and an output terminal of the second exclusive OR circuit EX2. Since one side of the first and second exclusive OR circuits EX1 and EX2 is connected to the supply voltage VDD and high logic is applied, the first and second exclusive OR circuits EX1 and EX2 may be applied due to the characteristics of the exclusive OR circuit. When high logic is applied to one side of the circuit and low logic is applied to the other side, a signal having high logic is output to the output terminals of the first and second exclusive OR circuits due to the characteristics of the exclusive OR circuit. On the other hand, when high logic is applied to the other side, a signal having low logic is output to the output terminals of the first and second exclusive OR circuits, thereby performing a function of an inverter with respect to a signal applied from the other side. The common voltage V _COM control signal is applied to the first exclusive logical sum EX1 circuit to output a signal inverted by the inverter function of the first exclusive logical sum EX1 circuit. The waveforms of the common voltage V _COM control signal D and the output signal E at this time are shown in FIG. On the other hand, the output signal E via the output terminal of the first exclusive OR circuit is applied to the input of the second exclusive OR circuit and the signal G re-inverted by the inverter function of the second exclusive OR circuit is output. do. The waveform of the re-inverted signal G at this time is shown in FIG. The re-inverted signal has the same magnitude and direction as the common voltage control signal, but can obtain a waveform delayed by a predetermined time. Meanwhile, by adjusting the value of the variable resistor VR1, the pulse width of the output waveform may be adjusted by adjusting the amount of charge accumulated in the thirty-first capacitor C31. In addition, the waveform of the signal charged and discharged to the 31st capacitor C31 is shown in FIG.

In addition, the configuration of the frequency integer multiplier means includes a third exclusive OR circuit EX3 connected to an output terminal of the second exclusive OR circuit EX2 and a third exclusive OR circuit for generating an initialization control signal V1. An output end of EX3 is provided. A delayed common voltage control signal and a non-delayed common voltage control signal are simultaneously applied to an input terminal of the third exclusive OR circuit EX3. The output terminal of the third exclusive logical sum circuit EX3 generates the initialization control signal V1 having high logic only for the delay time of the two signals input from the input terminal between the third exclusive logic sum circuit EX3, and at this time, the zero of the wave H of the initialization control signal is generated. It is shown at 6 degrees. Since the initialization control signal V1 is generated at each timing of rising and falling of the common voltage V _COM control signal, the initialization control signal V1 becomes a signal having twice the frequency of the input signal. As a result, the initialization control circuit serves as a frequency integer multiple circuit to have twice the frequency.

FIG. 5B is a diagram illustrating another embodiment of FIG. 5A, and is a logic circuit diagram of the first and second exclusive OR circuits EX1 and EX2 in FIG. 5A by replacing the first and second inverters I1 and I2. to be. In the configuration of FIG. 5B, the switch control circuit of the present invention includes a first inverter I1 input terminal, a fourth exclusive logic sum circuit EX4 input terminal connected to a common voltage V _COM control signal line, and a first inverter I1. A second variable resistor VR2 connected between the output terminal and the twenty-second node 32, a second inverter I2 connected to the twenty-second node 32, and a second terminal connected to the output terminal of the second inverter I2. An input terminal of the fourth exclusive OR circuit EX4 and an output terminal of the fourth exclusive OR circuit EX4 for outputting the switch control voltage V1 are provided. Since the operation states and functions of the first and second inverters I1 and I2 and the fourth exclusive OR circuit are the same as those of FIG. 5A, detailed descriptions thereof will be omitted.

As described above, the crosstalk compensation circuit switch control circuit of the present invention has the advantage of compensating a uniform common voltage by periodically discharging the amount of charge accumulated in the integrator of the crosstalk compensation circuit using an initialization controller.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

In the crosstalk compensation circuit of a liquid crystal display device having a liquid crystal panel, A differential amplifier which receives a first common voltage applied to the common electrode of the liquid crystal panel and a second common voltage already applied to the common electrode, and amplifies and outputs a difference between the first and second common voltages; A charge accumulator for accumulating the amplified output signal from the differential amplifier and outputting the accumulated amplified output signal; An adder configured to receive an output signal of the charge accumulator and a predetermined common voltage initial value, respectively, and generate and output the first common voltage corresponding to the two signals; And initialization means connected to the charge accumulator to initialize the amount of charge accumulated in the charge accumulator. The method of claim 1, And the charge accumulator is configured of a capacitor. The method of claim 1, And the initialization means is switched by an initialization control signal having a high logic in a period in which a logic value of a predetermined common voltage initial value delayed by a predetermined time and an undelayed common common voltage initial value is different from each other. In the liquid crystal display device, A liquid crystal panel which receives predetermined data and displays it; A differential amplifier receiving a first common voltage applied to the common electrode of the liquid crystal panel and a second common voltage already applied to the common electrode, and amplifying and outputting a difference value between the first and second common voltages; A charge accumulator for accumulating the amplified output signal from the differential amplifier and outputting the accumulated amplified output signal; An adder configured to receive an output signal of the charge accumulator and a predetermined common voltage initial value, respectively, and generate and output the first common voltage corresponding to the two signals; Initialization means connected to the charge accumulator to initialize the amount of charge accumulated in the charge accumulator; And an initialization controller which is connected to the initialization means and periodically controls the initialization operation of the initialization means. The method of claim 4, wherein The initialization control unit A delay unit which receives the common voltage initial value and delays the common voltage initial value by a predetermined time; And a frequency integer multiplier for generating an initialization control signal for controlling the initialization means, the frequency multiplying with respect to the frequency of the common voltage initial value. The method of claim 5, The delay unit, First inverting means for inverting the common voltage initial value; And second inverting means for inverting the output signal of the first inverting means again. The method of claim 6, And each of the first and second inverting means comprises an inverter. The method of claim 6, The first and second inverting means, A first exclusive OR circuit for performing an exclusive OR operation on a predetermined supply voltage and the common voltage initial value; And a second exclusive OR circuit for performing an exclusive OR on the output signal of the first exclusive OR circuit and the supply voltage. The method of claim 6, A variable resistor connected between the output terminal of the first inverting means and the input terminal of the second inverting means; And a capacitor connected between said variable resistor and a ground voltage source. The method of claim 9, And the amount of charge accumulated in the capacitor is controlled according to the resistance of the variable resistor.

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