KR100261229B1 - Demodulator of pai/4 dqpsk - Google Patents

Abstract

PURPOSE: A demodulator for demodulating a pi/4 differential quadrature phase shift keying signal is provided which receives the pi/4 differential quadrature phase shift keyed signal and solves data transmission error due to multipath fading to demodulate the signal into original digital data. CONSTITUTION: A channel separator(101,102) multiplies a received signal by sine wave and cosine wave to shift the received signal to the base band and separate the signal into I-channel signal and Q-channel signal. A/D converters(105,106) convert the I-channel signal and Q-channel signal into digital signals, respectively. Buffer memories(107,108) buffer the output signals of the A/D converters. A time synchronizing unit(110) calculates a correlation function value between a pi/4 differential quadrature phase shift keyed signal for reference training data stream and the received signal stored in a dual-port memory to detect the position of the reference training data stream in the received signal to perform time synchronization. A channel characteristic estimator(115) performs a block estimation algorithm for the synchronized received signal to estimate a channel characteristic value. A viterbi equalizer(112) executes viterbi algorithm for the channel characteristic value to determine reception phase values. A differential phase demodulator(113) detects a difference between the reception phase values to output predetermined binary data corresponding to the difference.

Description

Demodulator for π / 4 Differential Quadrature Shift Keyed Signal

1 is a block diagram of a demodulator of a π / 4 differential quadrature phase shift keying (DQPSK) signal according to the present invention,

2 is a view showing an embodiment of a data configuration to be transmitted,

3 is a diagram illustrating a configuration according to an embodiment of an adaptive matching filter.

4 is a grid state diagram for explaining an algorithm performed in the Viterbi equalization means.

* Explanation of symbols for main parts of the drawings

109: digital signal processing unit

The present invention relates to a demodulator for [pi] / 4 differential quadrature phase shift keying (DQPSK) signal, which is one of digital demodulators used in a time division multiple access (TDMA) system for mobile wireless communications.

The π / 4 differential quadrature shift keying (DQPSK) method is a modulation method for digital data transmission. The modulated signal has a smaller maximum instantaneous transition value than the conventional quadrature shift keying (QPSK) method. It can transmit a large amount of data and has the advantage of using a relatively simple receiver. However, in the case of a system using a multipath transmission (for example, a wireless digital mobile communication system), a data transmission error is increased due to the multipath fading effect.

Accordingly, an object of the present invention is to overcome the data transmission error caused by the multipath fading effect as described above after receiving a signal modulated and transmitted by π / 4 differential quadrature phase shifting (DQPSK). The present invention provides a demodulator capable of performing demodulation on original digital data.

In order to achieve the above object, a demodulator of the π / 4 differential quadrature shift keying (DQPSK) signal of the present invention is a device for demodulating a π / 4 differential quadrature shift keying (DQPSK) signal. Channel separating means for shifting the received signal to the baseband by multiplying the signal and separating the received signal into an I channel signal and a Q channel signal; An A / D converter for converting the analog I channel signal and the Q channel signal into a digital form; A buffer memory for buffering the output of the A / D converter; By calculating the correlation function value of the π / 4 differential quadrature phase shift keyed (DQPSK) signal for the reference training data sequence and the received signal stored in the dual-port-memory, the time synchronization is detected by detecting the position of the reference training data sequence in the received signal. Time synchronous means for performing; Channel characteristic estimating means for performing a block estimation algorithm on the synchronized received signals to estimate and output channel characteristic values; Viterbi equalization means for performing a Viterbi algorithm on the channel characteristic value to determine reception phase values; And differential phase restoring means for detecting a difference between the received phase values and outputting predetermined binary data corresponding thereto.

That is, the present invention employs Viterbi equalization means to overcome errors in transmission data caused by multipath fading effects, and the training sequence portion of the received signal is processed to process synchronization in a more convenient manner. When detecting, a method of detecting a correlation point where a correlation value with a predetermined data string, that is, a reference training sequence, is maximized is used.

Next, the present invention will be described in more detail with reference to the accompanying drawings.

1 is a block diagram of a demodulator of a π / 4 differential quadrature phase shift keying (DQPSK) signal according to the present invention, and includes a first multiplier 101 and a second multiplier 102 and a low pass filter (LPF) 103 and 104. And A / D converters 105 and 106, buffer memories 107 and 108, and a digital signal processor 109. The digital signal processing unit 109 includes a time synchronization unit 110, an adaptive matching filter 111, a training waveform unit 114, a channel characteristic estimation unit 115, a Viterbi equalization unit 112, and a differential phase decoding unit 113. It is configured to include).

In FIG. 1, the first multiplier 101 and the second multiplier 102 convert a signal of a radio frequency (RF) band into a baseband signal and simultaneously synthesize the received signal as channel separation means. This function separates and outputs two channel signals existing in the form. That is, since the received signal is a quadrature shift-modulated signal, two carriers (cosω ₀ t and -sinω ₀ t) having mutual orthogonality are multiplied with the received signal to separate the received signal into I and Q channels. Do this. Here, ω ₀ represents 2πf ₀ when the frequency of the local carrier is f ₀ . A low pass filter (LPF) 103, 104 is present in the high pass component by passing only the low pass component of the signal converted into baseband and separated into I and Q channels through the first multiplier 101 and the second multiplier 102. Eliminate noise. In other words, it removes the carrier component having harmonic noise and high frequency generated during the transition of the signal to the baseband and prevents aliasing. The A / D converters 105 and 106 perform a function of converting an analog signal output from the low pass filter (LPF) 103 or 104 into a digital signal. At this time, the A / D converters 105 and 106 perform sampling by using a clock having a frequency corresponding to an integer multiple of the frequency of the original digital data (oversampling) and corresponding to the integer multiple of the transmitted data. Output the data. For example, when a period in which 1 bit of data is transmitted is T, sampling is performed using a clock having a frequency of an integer k times of 1 / T, and one sample is quantized to n bits. When one time slot of the transmitted data is L × T, that is, when the data included in the time slot is an L symbol, the signal output from the A / D converters 105 and 106 is one time slot. k × L × n (where k means a positive integer) bit. In this case, n is 1 when performing hard decision, and has an integer value of 2 or more when performing soft decision. For example, it can be quantized to 8.

That is, the A / D converter uses a clock of K × (D-CK) when the data clock used when converting the original digital data into an analog signal is called D-CK and K is a natural number. Oversampling.

The buffer memories 107 and 108 perform a function of storing signals output from the A / D converters 105 and 106, which are signal processing speeds of the digital signal processor 109 located at a rear end and the A / D. Since the signal processing speeds in the converters 105 and 106 are different, the function of temporarily storing data is performed. In this case, the buffer memories 107 and 108 are configured using dual port memory to be accessible in both directions. That is, the clock values used in the read and write operations to the buffer memories 107 and 108 may be used differently, so that the A / D converters 105 and 106 and the digital signal processor 109 Configure the operation to be independent of each other.

The digital signal processing unit 109 performs a demodulation algorithm on a π / 4 differential quadrature phase shift keyed (DQPSK) signal and implements the operation by software using a general digital signal processing (DSP) chip. Alternatively, proprietary VLSI chips can be designed and implemented. Here, the function of the digital signal processing unit 109 will be described with reference to the block diagram shown in FIG.

In FIG. 1, the time synchronous means 110 is received with π / 4 differential digitally modulated data for a predetermined reference training sequence, quadrature shifted, demodulated, and then converted to digital. The function of detecting the position of each data in the timeslot is calculated by calculating the correlation function value with the data stored in the data slot.

In other words, when the length of the received timeslot is L × T, the data sequence oversampled from the A / D converters 105 and 106 and digitally converted is divided into k sets for each channel as follows.

Here, the subscript means an A / D conversion order for each channel. As described above, the data sequence divided into k sets calculates a correlation function value with the π / 4 differential digital modulation waveform of a predetermined reference training sequence stored in each set and the receiver. One set in which the peak value of the correlation function is the largest among each of the k sets of correlation functions is selected as a reception sequence of one time slot, and the reception data at the point representing the peak value is detected as reference training sequence data. If this is explained in more detail as follows.

Receive sequence of received baseband digital I, Q channels

Π / 4 differential digital modulation waveform of the reference training sequence

(However, the S value means the number of bits constituting the reference training sequence. If soft decision is performed, the reference training sequence is also converted accordingly and the number of bits is also an integer multiple of S (nS).) The peak value of is obtained by the following procedure.

First, a correlation function value for each channel is calculated according to equations (3) and (4).

The value obtained by the above formulas (3) and (4) is obtained according to the following formula (5).

When the part that is R [J] the value obtained through the process as described above represents the maximum value J _P, and detects J _P in J _P ± 1 of the reference point, a time synchronization as the time t _P. This is to locate the reference training sequence in the received digital signal for one time slot. In this case, the set to which the data detected by t _P belongs is selected as a received data sequence, and the time synchronization means 110 applies it to the adaptive matching filter 111. In addition, the time synchronization means 110 applies a vector P _C , which consists of correlation function values between the reference training sequence modulation waveform and the received training sequence modulation waveform, to the channel characteristic estimating means 115. The reference training sequence modulation waveform is 0, -π / 4, π / 2, π / 4, π / 2, -3π / 4, π / 2, -3π / 4, π / 2, π / When 4, π, -3π / 4, π, and 3π / 4 are represented, the following values are represented, respectively.

m _I [i] = 1, 1 / √2, 0, 1 / √2, 0, -1 / √2, 0, -1 / √2, 0, 1 / √2, -1, -1 / √ 2, -1, -1 / √2

m _Q [i] = 0, -1 / √2, -1, 1 / √2, 1, -1 / √2, 1, -1 / √2, 1, 1 / √2, 0, -1 / √2, 0, 1 / √2

Such a waveform is stored in the training waveform section 114 to be used in each block.

The channel characteristic estimating means 115 is a means for estimating the impulse response characteristic of the channel, and the vector R _C composed of the vector P _C output from the time synchronization means 110 and the autocorrelation function values of the reference training sequence modulation waveform. Calculates H _C , the dot product of the inverse vector. This is expressed as follows.

The H _C value is referred to as a coefficient vector of a discrete time model.

The adaptive matching filter 111 performs a filtering function for maximizing the signal-to-noise ratio of the received signal. The coefficient vector of the discrete time model output from the time synchronization means 110 is referred to as H _C , and the conjugate vector is H _C. When we say *, we perform matched filtering on H _C * (-t). At this time, the adaptive matching filter 111 performs the matching filter every time slot because the channel characteristics of the received signal change every time slot. When the adaptive matching filter 111 is not applied, the output of the time synchronization means 110 is directly applied to the Viterbi equalization means 112.

Viterbi equalization means 112 is one of digital equalization means, and has been transmitted from the transmitter using the channel characteristics estimated by the channel characteristic estimation means 115 for the signal output from the adaptive matching filter 111. A function of estimating and determining phase information of a π / 4 differential digital modulated signal having the highest probability is performed. The algorithm performed by the Viterbi equalization means 112 is already known from US Pat. No. 5,119,400, which is similar to the Viterbi decoding algorithm for decoding convolutional codes. In the π / 4 differential digital modulated signal, the value to be transmitted is a data string corresponding to the phase difference, and can be represented by drawing a lattice state diagram as shown in FIG. That is, each point can be roughly divided into an excellent point and an odd point, and the state of the excellent point and the odd point has a different characteristic. In addition, there are four possible state changes from excellent to radix, and four state changes from radix to excellent. In addition, the length of the traceback path is determined according to the delay spread due to the multipath fading phenomenon of the channel through which the signal passes.

Here, the phase difference value Δφ output from the Viterbi equalization means 112 is encoded in correspondence with predetermined data and its reverse process must be performed. This function is performed in the differential phase decoding means 113, which is shown in Table 1 below.

TABLE 1

FIG. 2 is a diagram showing an embodiment of a data structure to be transmitted. The data length of one time slot is represented by L bits and the length of the training sequence is represented by S bits. T shown in the figure indicates a period in which one bit of data is transmitted as described above. That is, the training sequence is transmitted for a predetermined period of time determined through mutual protocol at the transmitting and receiving side in one time slot. Information about each bit constituting the training sequence should be information known to both the transmitting and receiving sides.

3 illustrates a configuration of an adaptive matching filter, which includes a delay unit 301, two multipliers 302 and 303, and an adder 304.

In FIG. 3, the delay unit 301 performs a function of delaying the signal output from the time synchronization unit 110 once, and the multiplier 302 outputs the H _C outputted from the channel characteristic estimation unit 115. Vector autumn

In this case, the value h ₀ is multiplied by the data output from the time synchronous means 110, and the multiplier 302 multiplies the output signal of the delay unit 301 by the value h ₁ . The adder 304 performs the function of adding the outputs of the two multipliers 302 and 303.

As described above, the present invention uses a Viterbi equalization means to overcome the error caused by multipath fading instead of employing a complicated equalizer. The amount of computation allows the estimation of channel characteristics. That is, most of the demodulation process can be performed digitally, and it is configured to achieve accurate demodulation with a small amount of calculation. It is easy to interface with peripheral control circuits and also includes an A / D converter even in the case of small one chip. When configured, it has the advantage of implementing baseband processing on a single chip.

Claims (3)

A device for demodulating a π / 4 differential quadrature phase shift keying (DQPSK) signal, wherein the received signal is multiplied by a sine wave and a cosine wave, respectively, to shift the received signal to baseband and to separate the I-channel signal and the Q-channel signal. Channel separation means; An A / D converter for converting the analog I channel signal and the Q channel signal into a digital form; A buffer memory for buffering the output of the A / D converter; By calculating the correlation function value of the π / 4 differential quadrature phase shift keyed (DQPSK) signal with respect to the reference training data sequence and the received signal stored in the dual-port-memory, the time synchronization is detected by detecting the position of the reference training data sequence among the received signals. Time synchronous means for performing; Channel characteristic estimating means for performing a block estimation algorithm on the synchronized received signals to estimate and output channel characteristic values; Viterbi equalization means for performing a Viterbi algorithm on the channel characteristic value to determine a reception phase value and the like; And a differential phase recovery means for detecting a difference between the received phase values and outputting predetermined binary data corresponding to the received phase values. 2. The A / D converter according to claim 1, wherein the A / D converter is a data clock used for converting original digital data into an analog signal at D-CK and K is a natural number. A demodulator of π / 4 differential quadrature shift keying (DQPSK) signal, characterized in that oversampling is performed using a clock. [4] The? / 4 differential quadrature shift according to claim 1, wherein the demodulator further comprises an adaptive matched filter for performing adaptive matched filter on the signal of the time synchronization means in accordance with the output of the channel characteristic estimating means. Demodulator for modulated (DQPSK) signal.