JP2003037577A - Wireless communication device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption in receiving without degrading the receiving performance. SOLUTION: The device is composed of a synchronization means, which is a wireless communication device receiving orthogonal frequency division multiplexing which transmits data through multiple sub-carriers and outputs data with phase correction of received data after quadrature frequency detection, a Fourier transformation means which outputs received data on a frequency on-axis after the Fourier transformation of the received data after phase correction, a demodulation means which outputs received data on the frequency on-axis after demodulation, and a Viterbi decoding means which decodes and outputs received data after demodulation. The synchronization means, the demodulation means and the Viterbi decoding means are to calculate and output the amount of transmission channel distortion. Also the device is composed of a means for detecting the distortion amount in the transmission channel which generates data precision control signal based on at least one of the means, a data precision control means which changes bit width for processing received data according to the data precision control signal, and a data retention amount control means which changes retained data amount according to the data precision control signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wireless communication device that receives an orthogonal frequency multiplexed signal.

[0002]

2. Description of the Related Art In recent years, in digital audio broadcasting for mobiles, terrestrial digital television broadcasting, etc., Orthogonal Frequency Division Multiplexing,
In the following, communication using a signal (referred to as OFDM) is drawing attention. The OFDM signal is characterized by high frequency utilization efficiency, high-speed transmission of a large amount of data, and little characteristic deterioration due to reflected waves. Moreover, since the signal waveform has a shape close to random noise, it is difficult to give interference to other services.

FIG. 15 is a block diagram of a conventional OFDM signal receiving apparatus. This OFDM signal receiving device is intended to reduce power consumption during a receiving operation. In FIG. 15, the frequency conversion means 1 receives the received data as an input,
Frequency conversion processing is performed and the received data after frequency conversion is A /
Output to the D converter 2. The A / D converter 2 samples the input analog reception data, A / D converts it to obtain digital reception data, and outputs it to the quadrature detection means 3.
The quadrature detection means 3 down-converts the digital reception data into a baseband band, separates it into a real part (I reception data) and an imaginary part (Q reception data) on the time axis, and outputs it to the synchronization means 84.

The synchronizing means 84 reproduces the timing based on the I received data and the Q received data, and corrects the phases of the I received data and the Q received data. The synchronization means 84 is
The reproduction timing signal TS is output to the reception control means 91, and the phase-corrected I reception data IS and Q reception data QS are output to the Fourier transform means 85. Fourier transform means 85
The I-correction data IS and Q-correction data QS after the phase correction are subjected to Fourier transform to convert them into I-receipt data IF and Q-receipt data QF on the frequency axis of each carrier and output to the demodulation means 86. To do.

The demodulation means 86 determines the amplitude and phase on the complex plane for each carrier based on the I received data IF and the Q received data QF on the frequency axis, and converts them into complex data, as shown in FIG. The demodulated data is obtained with reference to the signal constellation diagram and output to the Viterbi decoding means 87. The Viterbi decoding means 87 performs error correction on the demodulated data and outputs a bit stream of the received data.

The reception control means 91 generates a reception operation control signal RC based on the reproduction timing signal TS and outputs it to the clock control means 92. The clock control means 92
A clock control signal CC based on the reception operation control signal RC
Is generated and output to the Fourier transform means 85, the demodulation means 86 and the Viterbi decoding means 87.

As described above, the processing for receiving an OFDM signal requires an enormous amount of calculation, and requires a large number of multipliers and adders and a memory that operates at high speed. For this reason, in the wireless communication apparatus of the OFDM system, power consumption is extremely large especially in the receiving operation.

Therefore, in the conventional OFDM signal receiving apparatus, even if the received data cannot be detected or even if the received data can be detected, the received power is temporarily set to the predetermined value before the data is received for the predetermined length. In the case where it becomes smaller, the reception control means 91 detects such a state and causes the clock control means 92 to stop the clock to reduce the power consumption.

[0009]

As described above, the conventional O
The FDM signal receiving device has a problem that the power consumption during the receiving operation is very large. Therefore, when the operation is not necessary, the clock is stopped to reduce the power consumption.

However, the power consumption during the receiving operation has not been reduced. For this reason, it has been desired to reduce the power consumption particularly during the receiving operation in the OFDM wireless communication device.

An object of the present invention is to provide an OFDM type wireless communication device in which the power consumption during the receiving operation is reduced without lowering the receiving performance.

[0012]

Means for Solving the Problems In order to solve the above-mentioned problems, the means of the invention of claim 1 is a radio communication apparatus for receiving an orthogonal frequency division multiplex signal for transmitting information by a plurality of subcarriers. In the process of obtaining the decoded bit stream from the received data after the quadrature detection, the processing accuracy is changed according to the amount of transmission path distortion obtained from the received data.

According to the first aspect of the present invention, it is possible to prevent the processing accuracy of the received data from becoming higher than necessary. Since the number of bits in which the signal level changes can be reduced, power consumption can be reduced in the process for obtaining the decoded bit stream.

According to a second aspect of the present invention, there is provided a radio communication device for receiving an orthogonal frequency division multiplex signal for transmitting information by a plurality of subcarriers, which is obtained by performing a phase correction on the received data after the quadrature detection. Along with outputting the received data after the phase correction is performed, the synchronization means for obtaining and outputting the amount of transmission path distortion based on the received data after the quadrature detection, and Fourier transforming the received data after the phase correction, Fourier transform means for outputting the received data on the frequency axis,
The received data on the frequency axis is demodulated, the obtained demodulated received data is output, and the amount of transmission path distortion is obtained based on the received data on the frequency axis and the demodulated received data. The demodulation means for outputting and the received data after the demodulation are decoded using a Viterbi algorithm, and the obtained decoded bit stream is output, and the amount of channel distortion is calculated based on the received data after the demodulation. Viterbi decoding means for outputting, the synchronization means, the demodulation means,
And a transmission path distortion amount detecting means for generating and outputting a data accuracy control signal based on at least one of the amounts of the transmission path distortion output by the Viterbi decoding means, and receiving in accordance with the data accuracy control signal. The synchronizing means, the Fourier transforming means, so as to change the bit width of data processing,
A data precision control unit that controls the demodulation unit and the Viterbi decoding unit, and a data holding amount control unit that controls the Viterbi decoding unit so as to change the received data holding amount according to the data precision control signal. It is a thing.

According to the second aspect of the present invention, the bit width of the received data processing can be changed according to the amount of transmission path distortion, and the received data holding amount in the Viterbi decoding means can be changed. Since the number of bits whose signal level changes can be reduced and the amount of calculation in Viterbi decoding can be reduced, power consumption can be reduced.

According to a third aspect of the present invention, in the wireless communication apparatus according to the second aspect, the synchronization means calculates a correlation value between the received data after the quadrature detection and a predetermined synchronization reference symbol pattern. A matched filter obtained as a correlation function, and a peak value difference detection means for obtaining and outputting the amount of the transmission path distortion from the difference between the second largest maximum value of the correlation function and a predetermined value in a period corresponding to one symbol period. With.

According to a fourth aspect of the present invention, in the wireless communication apparatus according to the third aspect, the synchronizing means stops the clock of the peak value difference detecting means during a period in which no synchronization reference symbol is input. .

According to a fifth aspect of the present invention, in the radio communication apparatus according to the second aspect, the synchronization means calculates a correlation value between the received data after the quadrature detection and a predetermined synchronization reference symbol pattern. A matched filter obtained as a correlation function and an integrated value of the correlation function in a period corresponding to one symbol period are sequentially obtained while moving the integration period, and the integration period is moved so that the integrated value becomes a predetermined value or more. And an integral calculating means for obtaining the amount of the transmission line distortion from the range and outputting the amount.

According to a sixth aspect of the present invention, in the wireless communication apparatus according to the fifth aspect, the synchronizing means stops the clock of the integration calculating means during a period in which no synchronization reference symbol is input.

According to a seventh aspect of the invention, in the radio communication apparatus according to the second aspect, the demodulation means is ideally corresponded to an actual signal point on a signal point arrangement diagram showing the phase and amplitude of each subcarrier. The distance to the signal point is output as the amount of transmission line distortion.

Further, in the invention of claim 8, in the radio communication device according to claim 2, the Viterbi decoding means has a difference between a branch metric of the maximum likelihood path and a branch metric other than the maximum likelihood path. The length of the received data holding period that is equal to or greater than a predetermined threshold value is obtained and output as the amount of transmission line distortion.

According to a ninth aspect of the present invention, in the radio communication apparatus according to the second aspect, when the reception data after the quadrature detection is input, the synchronization means generates a transmission line distortion based on the data. The bit width of the received data processing in the synchronizing means is changed in accordance with the amount, and the demodulating means receives the received data output from the Fourier transforming means based on the data. The amount of transmission line distortion is obtained, and the bit width of the received data processing in the demodulation unit is changed according to the amount of transmission line distortion obtained by the synchronization unit and the Viterbi decoding unit. When the received data output from the demodulation means is input, the amount of transmission line distortion is obtained based on the data, and the amount of transmission line distortion is determined according to this and the amount of transmission line distortion obtained by the synchronization means and the demodulation means. And the bit width of the received data processing in the bi decoding means, thereby changing the reception data holding amount.

According to a tenth aspect of the present invention, in the wireless communication apparatus according to the second aspect, the transmission path distortion amount detecting means includes a plurality of registers, and the synchronizing means and the aforesaid register among the plurality of registers. The value of the data precision control signal is stored in each of the demodulation means and the one corresponding to the combination of the respective amounts of transmission path distortion obtained by the Viterbi decoding means.

The invention of claim 11 is a radio communication apparatus for receiving an orthogonal frequency division multiplex signal for transmitting information by a plurality of subcarriers, which is obtained by performing phase correction on received data after quadrature detection. Synchronization means for outputting the received data after the phase correction, Fourier transform means for performing Fourier transform on the received data after the phase correction, and outputting the obtained reception data on the frequency axis, and receiving on the frequency axis Demodulating means for demodulating the data and outputting the obtained demodulated received data, and decoding the demodulated received data using a Viterbi algorithm, outputting the obtained decoded bit stream, Viterbi decoding means for detecting and outputting the modulation method of the carrier, and changing the bit width of the received data processing according to the modulation method of the subcarrier, Data precision control means for controlling the synchronization means, the Fourier transform means, the demodulation means and the Viterbi decoding means, and controlling the Viterbi decoding means so as to change the received data holding amount according to the modulation method of the subcarrier. And a data holding amount control means for controlling the data holding amount.

According to the eleventh aspect of the present invention, it is possible to change the bit width of the received data processing according to the modulation method of the subcarrier and change the received data holding amount in the Viterbi decoding means. Since the number of bits whose signal level changes can be reduced and the amount of calculation in Viterbi decoding can be reduced, power consumption can be reduced.

According to the invention of claim 12, the invention of claim 11
In the wireless communication device described in the paragraph 1, the Viterbi decoding unit changes the operating frequency according to the modulation method of the subcarrier.

Further, the invention of claim 13 is the radio communication apparatus according to claim 2 or 11, wherein the bit width of the received data processing is changed by fixing the value of a predetermined bit of the received data to zero. It is characterized by

According to a fourteenth aspect of the present invention, in the wireless communication device according to the second or the eleventh aspect, the clock for the circuit for processing a part of the bits of the data is stopped so that the received data is processed. The feature is that the bit width is changed.

In this specification, the processing accuracy indicates the bit width of the received data processing or the received data holding amount used for decoding.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a block diagram of a wireless communication device according to the embodiment of FIG. The wireless communication device of FIG. 1 includes a frequency conversion unit 1, an A / D converter 2, a quadrature detection unit 3, a synchronization unit 4, a Fourier transform unit 5, a demodulation unit 6, and a Viterbi decoding unit 7. , Reception control means 11 and clock control means 1
2, a transmission line distortion amount detection means 13, a data accuracy control means 14, and a data holding amount control means 15. A clock is input to each of these components.

In FIG. 1, the frequency conversion means 1 frequency-converts a reception signal received via a transmission line to shift the frequency, and outputs the obtained signal to the A / D converter 2. At this time, the received signal is converted into a received signal of intermediate frequency. The A / D converter 2 performs sampling and A / D conversion on the frequency-converted reception signal, and outputs the obtained digitized reception data to the quadrature detection means 3. Hereinafter, as an example, the A / D converter 2 performs sampling at 16 points per symbol. The quadrature detection means 3 performs quadrature detection on the digitized reception data and down-converts into a base band band a real part on the time axis (I reception data I
R) and the imaginary part (Q received data QR) are separated and output to the synchronization means 4.

The synchronizing means 4 detects the synchronization reference symbol added to the received data and reproduces the timing so that the device on the transmitting side and the device on the receiving side synchronize with each other. The synchronization means 4 reproduces the timing of the synchronization reference symbol from the reception data after the quadrature detection separated into the I reception data IR and the Q reception data QR, and outputs the obtained reproduction timing signal TS to the reception control means 11. Output. Further, the synchronizing means 4 carries out a phase correction on the I reception data IR and the Q reception data QR, and outputs the I reception data IS and the Q reception data QS after the phase correction to the Fourier transform means 5. Further, the synchronizing means 4 determines the first and second amounts of transmission line distortion.
The synchronous transmission path distortion amount detection signals D1 and D2 are obtained and output to the transmission path distortion amount detection means 13.

The Fourier transform means 5 Fourier transforms the phase-corrected I reception data IS and Q reception data QS (OFDM symbol on the time axis) synchronized with the synchronization reference symbol, and converts the data into data on the frequency axis. This makes O
The FDM symbol is separated for each subcarrier, and the phase and amplitude information of each subcarrier can be obtained. Hereinafter, as an example, it is assumed that each subcarrier is modulated by the 16QAM method. Fourier transform means 5
Outputs the obtained I reception data IF and Q reception data QF on the frequency axis to the demodulation means 6.

When there is channel distortion, each subcarrier of the OFDM signal causes phase rotation, and the phase shifts from the phase at the time of transmission. Since the phase of each subcarrier is responsible for the transmission of information, if the phase shifts, the transmission data will be erroneously reproduced. Even if there is a frequency shift or a time shift between the transmitter and receiver, the phase error of each subcarrier is corrected and
It is necessary to demodulate the FDM symbol.

The demodulation means 6 estimates the phase rotation error in the OFDM symbol, compensates the phase error of each subcarrier, and obtains the phase and amplitude of each subcarrier. That is,
After the synchronizing means 4 has achieved a certain degree of synchronization based on the synchronizing reference symbol, the demodulating means 6 performs phase compensation so that there is no phase shift that the synchronizing means 4 could not eliminate, and further improves the accuracy of demodulation. There is.

The demodulation means 6 demodulates the I reception data IF and the Q reception data QF on the frequency axis. That is, I reception data IF and Q reception data QF are converted into complex data (I after demodulation) corresponding to amplitude and phase for each subcarrier.
The received data ID and the Q received data QD) are converted and output to the Viterbi decoding means 7. The demodulation means 6 also outputs the demodulation transmission path distortion amount detection signal DD as the transmission path distortion amount based on the I reception data IF and Q reception data QF, and the demodulated I reception data ID and Q reception data QD. It is obtained and output to the transmission path distortion amount detection means 13.

The Viterbi decoding means 7 decodes the demodulated I received data ID and Q received data QD while performing error correction using the Viterbi algorithm, and obtains and outputs a decoded bit stream. Further, the Viterbi-decoded transmission channel distortion amount detection signal VD is obtained as the transmission channel distortion amount and is output to the transmission channel distortion amount detection means 13.

In the reception control means 11, which of the functional blocks such as the synchronization means 4, the Fourier transform means 5, the demodulation means 6 and the Viterbi decoding means 7 is processing data based on the reproduction timing signal TS. Knows.
This is because it is possible to know how far the received data has reached by the number of clock cycles after the reproduction timing signal TS is input. Reception control means 11
Generates a reception operation control signal RC indicating a functional block for which the clock should be stopped and outputs it to the clock control means 12 without processing data.

The clock control means 12 generates a clock control signal CC instructing to stop the clock of the functional block indicated by the reception operation control signal RC,
It outputs to the synchronizing means 4, the Fourier transforming means 5, the demodulating means 6 and the Viterbi decoding means 7.

The transmission path distortion amount detecting means 13 includes the first and second
Synchronous transmission path distortion amount detection signals D1 and D2, demodulation transmission path distortion amount detection signal DD, and Viterbi decoding transmission path distortion amount detection signal VD
Based on the above, a data precision control signal PC for controlling the bit width of the received data processing and the received data holding amount is generated and output to the data precision control means 14 and the data holding amount control means 15.

The transmission line distortion amount detecting means 13 includes a first synchronous transmission line distortion amount detection signal D1, a second synchronous transmission line distortion amount detection signal D2, a demodulation transmission line distortion amount detection signal DD, and a Viterbi decoding transmission line. The table has the values of the data precision control signal PC for the combinations of the values of the distortion amount detection signal VD. For example, the transmission line distortion amount detection means 13 is provided with a plurality of registers, and one of them, which corresponds to a combination of the values of these signals, stores the value of the data precision control signal PC. The transmission line distortion amount detection means 13 outputs a data accuracy control signal PC for instructing to increase the bit width of received data processing and the received data holding amount as the amount of transmission line distortion indicated by the input detection signal is larger. To do.

The data precision control means 14 determines the synchronization data precision control signal S based on the data precision control signal PC.
P, Fourier transform data precision control signal FP, demodulation data precision control signal DP, and Viterbi decoding data precision control signal VP are obtained, and synchronization means 4, Fourier transform means 5,
It outputs to each of the demodulation means 6 and the Viterbi decoding means 7.

The data precision control means 14 synchronizes the data precision control signal S with respect to the value of the data precision control signal PC.
P, a Fourier transform data precision control signal FP, a demodulation data precision control signal DP, and a Viterbi decoding data precision control signal VP have values as a table. For example,
The data precision control means 14 is provided with a plurality of registers, and each of the four registers corresponding to each value of the data precision control signal PC has a synchronization data precision control signal SP, a Fourier transform data precision control signal FP, and demodulation data. Precision control signal D
P and the value of the Viterbi decoding data precision control signal VP are stored.

The data holding amount control means 15 generates a data holding amount control signal DA based on the data precision control signal PC and outputs it to the Viterbi decoding means 7. The data holding amount control means 15 has a table of the values of the data holding amount control signal DA with respect to the values of the data precision control signal PC. For example, the data holding amount control means 15 includes a plurality of registers, and stores the value of the data holding amount control signal DA in each register corresponding to each value of the data precision control signal PC.

Since the transmission path distortion amount detecting means 13, the data accuracy controlling means 14, and the data holding amount controlling means 15 have tables, if the tables are changed, the bit width of the received data processing and the received data holding are held. Different controls can be applied to the quantity. Transmission path distortion amount detection means 13, data accuracy control means 14, and data holding amount control means 15
May store the table in a memory or the like instead of the register, or may perform the predetermined calculation on the value of the input signal without using the table to obtain the signal to be output.

The synchronizing means 4 receives the bit width of the received data processing, that is, in accordance with the synchronizing data precision control signal SP.
It controls the bit width when the above-described arithmetic processing is performed on the input received data. Similarly, the Fourier transform means 5, the demodulation means 6, and the Viterbi decoding means 7 are also input to the Fourier transform data accuracy control signal FP,
The bit width of the received data processing is changed according to the demodulation data accuracy control signal DP and the Viterbi decoding data accuracy control signal VP. Further, the Viterbi decoding means 7 controls the received data holding amount according to the data holding amount control signal DA. The received data holding amount is the number of received data used when obtaining the maximum likelihood path.

To control the bit width of the received data processing, for example, some bits of the data are fixed to "0". According to this, the bit width can be controlled at high speed. Also, the clock to the circuit for processing some bits of the data may be stopped. According to this, it is possible to further reduce the power consumption.

FIG. 2 is a block diagram showing the structure of the synchronizing means 4 of FIG. In FIG. 2, the synchronization means 4 includes a matched filter 41, a peak value difference detection means 42, an integration calculation means 43, a timing reproduction means 44, a phase correction amount calculation means 45, and a reception data phase correction means 46. I have it.

Each component of the synchronizing means 4 changes the bit width of the received data processing according to the synchronizing data accuracy control signal SP. Further, each component of the synchronizing means 4 is adapted to stop the clock in each component according to the clock control signal CC during the period when the synchronization reference symbol is not input.

The matched filter 41 receives the I received data I
R and Q received data QR are input, and in order to detect a synchronization reference symbol, a correlation signal is obtained and peak value difference detection means 42, integration calculation means 43, timing reproduction means 4 are obtained.
4 and the phase correction amount calculation means 45.

FIG. 3 is a block diagram of the matched filter 41 of FIG. The matched filter 41 of FIG. 3 includes a 16-bit shift register 411 and 16 multipliers 412 each of which inputs each bit of the shift register 411.
And an adder 413.

It is assumed that the sampling data number of the synchronization reference symbol is 16 data and one symbol period is one cycle. The received data input from the left side to the shift register 411 in FIG. 3 is sequentially shifted to the right, and when a signal for one cycle is input, one cycle for each bit is input from each bit of the shift register 411 as an intermediate tap of the filter. It becomes possible to take out signals simultaneously. Each bit of the shift register 411 is output to the corresponding 16 multipliers 412. 16
A coefficient is set in each of the multipliers 412, and each multiplier 412 outputs the product of the coefficient and the input bit to the adder 413.

For example, if the pattern of the synchronization reference symbol to be detected from the received data is "1011 0101 0110 0101", 16 multipliers 412 are set to the values of the bits of this pattern in order from the right. Adder 413
Outputs the correlation value between the pattern to be detected and the 16-bit data stored in the shift register 411 as a correlation signal by adding the outputs of the multipliers 412.
In this way, the correlation value between the received signal and the pattern to be detected can be obtained in real time. When the correlation signal is observed, a sharp peak of the correlation value always appears, and the synchronization reference symbol can be detected. Using the timing at which this peak appears, the timing is reproduced and the received data is phase-corrected.

FIG. 4 is an explanatory diagram showing the waveform of the correlation signal output from the matched filter 41 of FIG. In the correlation signal, one sharp peak of the correlation value always appears in each period corresponding to one symbol. FIG. 4A is a diagram showing a case where there is no channel distortion and an ideal synchronization reference symbol is received. In this case, a clear peak waveform can be obtained. FIG. 4B is a diagram showing a case where a synchronization reference symbol with transmission path distortion is received. In this case, the peak of the waveform caused by the distortion of the transmission line is formed at a place other than the peak value.

As shown in FIG. 4, the maximum value of the peak other than the peak value of the predetermined threshold and the correlation function (that is, 2)
(The next largest local maximum) (difference from transmission line distortion)
It can be seen that the smaller the value, the larger the amount of transmission line distortion, and the larger this difference, the smaller the amount of transmission line distortion. The peak value difference detecting means 42 detects the transmission path distortion margin as shown in FIG. 4 from the correlation signal and outputs it to the transmission path distortion amount detecting means 13 as the first synchronous transmission path distortion amount detecting signal D1.

FIG. 5 is a block diagram showing the structure of an integrating circuit included in the integral calculating means 43 shown in FIG. The integrating circuit of FIG. 5 includes a flip-flop 431 and an adder 432 for each one.
I have six. This integrating circuit can output the total of 16 samples up to a certain point of time of the correlation signal as an integrated value. A clock (not shown) is input to each flip-flop 431 every time one sampling is performed,
The value moves to the next flip-flop 431 on the right side. Therefore, the integrating circuit of FIG. 5 can output the integrated value of the correlation signal in the period of 16 samples while moving the period of integration.

FIG. 6 is an explanatory diagram showing the relationship between the correlation signal and the output of the integrating circuit of FIG. FIG. 6A is a diagram showing a case where there is no channel distortion and an ideal synchronization reference symbol is received. In this case, since the correlation signal has a large value only at one sampling point, the integrating circuit of FIG.
A constant value is output for a period corresponding to 16 samples. Figure 6
(B) is a diagram showing a case where a synchronization reference symbol added with transmission path distortion is received. In this case, the period in which the integrating circuit in FIG. 5 outputs a relatively large value is longer than the period corresponding to 16 samples.

As shown in FIG. 6, it can be seen that the longer the period in which the integrating circuit of FIG. 5 outputs a relatively large value, the larger the amount of transmission line distortion, and the shorter the period, the smaller the amount of transmission line distortion. . Therefore, the integral calculating means 43 obtains the length of the period during which the output of the integrating circuit of FIG. 5 exceeds a predetermined threshold value, and supplies it to the transmission path distortion amount detecting means 13 as the second synchronous transmission path distortion amount detecting signal D2. Output.

In FIG. 2, timing reproduction means 44
Outputs the reproduction timing signal TS synchronized with the peak value of the correlation signal to the timing of the synchronization reference symbol to the reception control means 11. The phase correction amount calculation means 45
A phase correction control signal indicating a phase error amount is obtained from the peak value of the correlation signal and is output to the reception data phase correction means 46.
The reception data phase correction means 46 corrects the phases of the I reception data IR and the Q reception data QR based on the phase correction control signal, and outputs the I reception data IS and the Q reception data QS after the phase correction to the Fourier transform means 5. To do.

FIG. 7 is a block diagram showing the structure of the demodulation means 6 of FIG. In FIG. 7, the demodulation unit 6 includes a phase correction unit 61, a signal point coordinate determination unit 62, and a signal point coordinate difference detection unit 63. Phase correction means 61
Is I received data IF and Q received data Q on the frequency axis.
Phase correction is performed on F, and the obtained corrected I reception data and Q reception data are output to the signal point coordinate determination means 62.

FIG. 8 is a signal point constellation diagram (constellation di
It is explanatory drawing which shows the signal point arrangement | positioning of 16QAM system on agram, and an error vector. In FIG. 8, the symbol ● indicates the coordinates of the ideal signal point, and the symbol ○ indicates the corrected I.
An example of coordinates of signal points of received data and Q received data is shown. A boundary is set between the ideal signal points (symbols ●) in FIG. 8, and the signal point coordinate determination means 62 determines the corrected I reception data and Q reception data among the ideal signal points. Which is closest to the signal point (symbol ◯) of, and its coordinates are demodulated to I received data ID and Q received data QD
To the Viterbi decoding means 7.

The signal point coordinate difference detecting means 63 has the coordinates indicated by the corrected I received data and Q received data outputted by the phase correcting means 61 and the signal point coordinate judging means 62 on the complex plane as shown in FIG. The magnitude of the difference (error vector) from the coordinates indicated by the demodulated I received data ID and Q received data QD to be output is output to the transmission path distortion amount detection means 13 as a demodulated transmission path distortion amount detection signal DD.

The Viterbi decoding means 7 accumulates the demodulated I reception data ID and Q reception data QD for a predetermined time, estimates the code sequence most likely to be transmitted using the Viterbi algorithm, and decodes it. Get the bitstream. As a result, the transmission line distortion is added to the reception signal on the transmission line, and the error generated due to the deterioration of the reception signal can be corrected.

The Viterbi algorithm is known as an algorithm for efficiently estimating a code sequence. The Viterbi algorithm calculates the likelihood of a path (representing a state transition) to each state (a scale indicating the degree of similarity to a transmission sequence) at a certain time, and determines the most probable path (maximum likelihood) to reach that state. This is an algorithm for estimating the transmission code sequence by considering only (path) from the next time. Since the likelihood is not calculated for all paths, the amount of calculation can be reduced significantly.

FIG. 9 is an explanatory diagram of the Viterbi algorithm. After converting the received data to 2-bit parallel data,
An example of performing the decoding process using the Viterbi algorithm will be described. The 2-bit code is (0,0), (0,
1), (1, 0), and (1, 1) correspond to the four states, the state transits between these four states when the transmission data is observed for a predetermined period. Considering the influence of the delayed wave up to one symbol time (when the propagation path memory length L of the Viterbi algorithm is "1"), description will be made with reference to FIG.

The path metric (probability of reaching this state) of the state (0,0) at time i is obtained. First,
The branch metric of the path from the state (0,0) at time (i-1) to the state (0,0) at time i is added to the path metric of state (0,0) at time (i-1). , And this value is A1. Next, the time (i-
The branch metric of the path from the state (0,1) at time (i-1) to the state (0,0) at time i is added to the path metric of state (0,1) in 1), and this value is A2.

Next, at the time (i-1), the state (1,
The branch metric of the path from the state (1,0) at time (i-1) to the state (0,0) at time i is added to the path metric of (0), and this value is set to A3.
Next, the branch metric of the path from the state (1,1) at time (i-1) to the state (0,0) at time i is added to the path metric of state (1,1) at time (i-1). Is added and this value is set to A4.

A1, A2, A3 and A4 obtained above
And the smallest one is selected as the path metric of the state (0, 0) at time i. A1, A2, A
Only the path corresponding to the selected one of 3 and A4 is left, and after time (i + 1), only that path may be considered. This remaining path is referred to as a "survival path", and this is stored in the storage means as survivor path information. Such a process is performed for other states (0,
The same is done for 1), (1, 0), and (1, 1).

Assuming that the received data holding amount is equal to the symbol length affected by the delayed wave (this is L), the received data sequence is traced back from time i by a time corresponding to the received data holding amount L. Is used to determine the maximum likelihood path at time i (of the surviving paths at time i, the path with the smallest path metric at time i). The maximum likelihood path is determined by the value of the branch metric (the degree of approximation between the received data and the path). Finally, the error-corrected received data can be obtained from the maximum likelihood path.

The Viterbi decoding means 7 traces back time,
Path with the smallest branch metric value (maximum likelihood path)
And the branch metric with the branch metric value next smaller than the maximum likelihood path (survival path) is calculated, and when the difference exceeds a predetermined threshold value, the traced time is transmitted. It shall be detected as the amount of road strain. It is determined that the smaller the traced time is, the smaller the amount of transmission path distortion is. The Viterbi decoding means 7 outputs the traced time as a Viterbi decoding channel distortion amount detection signal VD.

FIG. 10 is a flow chart showing the operation of the radio communication apparatus of FIG. In FIG. 10, step S
In 11, the clock is supplied to the frequency conversion means 1, the A / D conversion means 2, the quadrature detection means 3, and the synchronization means 4.
The clock control means 12 outputs a clock control signal CC for instructing the Fourier transform means 5, the demodulation means 6, and the Viterbi decoding means 7 to stop the clock.

In step S12, the transmission path distortion amount detecting means 13 processes the received data with the highest accuracy.
Set the bit width of received data processing. That is, the transmission path distortion amount detecting means 13 maximizes the bit width of the received data processing in the synchronizing means 4, the Fourier transforming means 5, the demodulating means 6, and the Viterbi decoding means 7, and the received data holding amount in the Viterbi decoding means 7. A data accuracy control signal PC instructing to do so is output.

In step S13, the reception control means 11
Determines whether or not the received data is detected, that is, whether or not the received data has reached the synchronizing means 4, based on the reproduction timing signal TS output by the synchronizing means 4. If detected, the process proceeds to step S14, and if not detected, this step is executed again.

In step S14, the synchronizing means 4 obtains the first and second synchronous transmission line distortion amount detection signals D1 and D2 as the transmission line distortion amount.

In step S15, a routine for changing the processing accuracy is executed. Here, the transmission line distortion amount detection means 1
3 obtains and outputs a data precision control signal PC for instructing to change the bit width of the received data processing in the synchronizing means 4, based on the first and second synchronous transmission path distortion amount detection signals D1 and D2. .

In step S21, the reception control means 11
On the basis of the reproduction timing signal TS, determines whether or not the received data has arrived at the Fourier transform means 5, and notifies the clock control means 12 of it. If it has arrived, the process proceeds to step S22, and if it has not arrived, this step is executed again.

In step S22, the clock control means 1
2 is a period in which the synchronization reference symbol is not input, so the peak value difference detection means 42 in the synchronization means 4
The clocks of the integration calculation means 43 and the phase correction amount calculation means 45 are instructed to stop, and the Fourier transform means 5 outputs a clock control signal CC instructing to supply the clocks.

In step S23, the reception control means 11
Determines whether the received data has arrived at the demodulation means 6 based on the reproduction timing signal TS, and notifies the clock control means 12 of it. If it has reached step S24
Go to and repeat this step if not reached.

In step S24, the clock control means 1
2 outputs a clock control signal CC instructing the demodulation means 6 to supply a clock.

In step S25, the demodulation means 6 obtains the amount of transmission line distortion, that is, the demodulation transmission line distortion amount detection signal DD.

In step S26, a routine for changing the processing accuracy is executed. Here, the transmission line distortion amount detection means 1
3 is based on the first and second synchronous transmission line distortion amount detection signals D1 and D2 and the demodulation transmission line distortion amount detection signal DD,
A data accuracy control signal PC instructing to change the bit width of the received data processing in the demodulation means 6 is obtained and output.

In step S31, the reception control means 11
Determines whether the received data has arrived at the Viterbi decoding means 7 based on the reproduction timing signal TS, and notifies the clock control means 12 of it. If it has arrived, the process proceeds to step S32. If it has not arrived, this step is executed again.

In step S32, the clock control means 1
2 outputs a clock control signal CC instructing the Viterbi decoding means 7 to supply a clock.

In step S33, the Viterbi decoding means 7 obtains the amount of transmission line distortion, that is, the Viterbi decoding transmission line distortion amount detection signal VD.

In step S34, a routine for changing the processing accuracy is executed. Here, the transmission line distortion amount detection means 1
3 is a Viterbi decoding means 7 based on the first and second synchronous transmission path distortion amount detection signals D1 and D2, the demodulation transmission path distortion amount detection signal DD, and the Viterbi decoding transmission path distortion amount detection signal VD.
To change the bit width of received data processing in
At the same time, the data precision control signal PC for instructing to change the amount of received data in the Viterbi decoding means 7 is obtained and output.

In step S41, the reception control means 11
Determines whether or not the packet has ended, and notifies the clock control means 12. If the packet has ended, the process proceeds to step S42, and if the packet has not ended, this step is executed again.

In step S42, the clock control means 1
2 supplies a clock to the entire synchronizing means 4, and outputs a clock control signal CC instructing to stop the clocks of the Fourier transform means 5, the demodulation means 6 and the Viterbi decoding means 7. Then, the process returns to step S12.

FIG. 11 is a flowchart of a routine for changing the processing accuracy. In FIG. 11, step S5
In 1, the transmission path distortion amount detection means 13 refers to the table and sets the value of the data accuracy control signal PC for the combination of the transmission path distortion amounts obtained by the synchronization means 4, the demodulation means 6, and the Viterbi decoding means 7. Ask.

In step S52, the processing accuracy, that is, the bit width of the received data processing, and the Viterbi decoding means 7
It is determined whether or not the received data holding amount in is changed. If it is changed, the process proceeds to step S53, and if it is not changed, this routine is finished.

In step S53, the processing accuracy is changed. That is, the synchronization unit 4, the demodulation unit 6, and the Viterbi decoding unit 7 change the bit width of the received data processing according to the data precision control signal PC, and the Viterbi decoding unit 7 receives according to the data precision control signal PC. Change the data retention amount. Then, this routine ends.

As described above, the radio communication apparatus of FIG. 1 can control the bit width of the received data processing and the received data holding amount in the Viterbi decoding means 7 according to the amount of transmission path distortion. Further, since the synchronizing means 4 and the demodulating means 6 control the bit width at the time of processing the received data as soon as the amount of transmission path distortion is obtained, the bit width of the received data processing is changed at high speed to an appropriate value. be able to. Further, clock control can be performed so that a portion where the received data processing is not performed is stopped and only a necessary portion is operated.
Therefore, it is possible to reduce the power consumption even during the reception operation.

(Second Embodiment) FIG. 12 is a characteristic diagram showing the relationship between transmission path distortion and error rate for each modulation method. Figure 1
2, there is a difference in the allowable range of transmission path distortion due to the difference in the modulation method. For example, BPSK, QPSK,
Comparing the 16QAM and 64QAM modulation systems, BP
The allowable range for transmission line distortion is wide in the order of SK, QPSK, 16QAM, and 64QAM. In the first embodiment, the wireless communication device that controls the bit width and the like of received data processing according to the amount of transmission path distortion has been described, but in the second embodiment, the bit width and the like of received data processing is controlled by the modulation method. A wireless communication device that does this will be described.

FIG. 13 is a block diagram of a radio communication apparatus according to the second embodiment of the present invention. The wireless communication apparatus of FIG. 13 is the same as the wireless communication apparatus of FIG. 1, except that the transmission path distortion amount detecting means 13 is replaced by the modulation method detecting means 16, and the Viterbi decoding means 7 and the clock control means 12 are replaced by the Viterbi decoding means 27.
And clock control means 32, respectively. The other components are the same as those described with reference to FIG. 1, so the same reference numerals are given and the description thereof is omitted.

The Viterbi decoding means 27 detects the modulation method of the subcarrier from the header of the received data and outputs it as the modulation method information signal MT to the modulation method detecting means 16. The modulation method detection means 16 receives the modulation method information signal MT as an input, generates a data accuracy control signal PC, and outputs it to the data accuracy control means 14 and the data holding amount control means 15. Further, the modulation method detection means 16 notifies the clock control means 32 of the modulation method.

The operation sequence of the modulation method detecting means 16 will be described. The modulation method detecting means 16 sets the bit width and the like of the received data processing so that the received data can be processed with the highest accuracy at the start of the receiving operation. That is, the modulation method detecting means 16 includes the synchronizing means 4, the Fourier transforming means 5, the demodulating means 6, and the bit width of the received data processing in the Viterbi decoding means 27, and the Viterbi decoding means 2.
A data precision control signal PC for instructing to maximize the received data holding amount in 7 is output.

When the received data reaches the Viterbi decoding means 27 after receiving the received data, the modulation method detecting means 16 determines the bit width of the received data processing according to the modulation method information signal MT output from the Viterbi decoding means 27. The data accuracy control signal PC is output so as to sequentially change the received data holding amount in the Viterbi decoding means. As a result, it is possible to control the bit width and the like of the received data processing according to the transmission path distortion that each modulation method can tolerate, and reduce the power consumption during the receiving operation.

FIG. 14 is a timing chart showing the demodulated data holding timing in the Viterbi decoding means 27 of FIG. For example, comparing BPSK and 16QAM, BPSK has a smaller amount of data in one symbol. When the same clock is used, the write period WR to the memory for holding the received data included in the Viterbi decoding means 27 for holding the past received data is shorter in the case of BPSK.

Writing to the reception data holding memory
If the subcarrier modulation method is BPSK, the write clock to the reception data holding memory when the subcarrier modulation method is BPSK is 16Q when the modulation method is 16Q.
The frequency may be lower than the write clock to the reception data holding memory in the case of AM. Therefore, the clock control means 32 determines the Viterbi decoding means 2 according to the modulation method.
A clock control signal CC for instructing to change the clock frequency of 7 is output to change the operating frequency of the Viterbi decoding means 27. When the modulation method is BPSK, if the operating frequency of the Viterbi decoding means 27 is smaller than that when the modulation method is 16QAM, the power consumption during the receiving operation can be reduced.

As described above, the radio communication apparatus of FIG. 13 can control the bit width of the received data processing and the received data holding amount in the Viterbi decoding means 27 according to the modulation method. Also, depending on the subcarrier modulation method,
Clock control can be performed to change the clock frequency. Therefore, it is possible to reduce the power consumption even during the reception operation.

[0101]

As described above, according to the wireless communication device of the present invention, the bit width when processing data is controlled in accordance with the amount of channel distortion and the modulation method of subcarriers, and the Viterbi decoding means. The received data holding amount in is changed. Therefore, it is possible to reduce the power consumption without lowering the reception performance even during the reception operation.

[Brief description of drawings]

FIG. 1 is a block diagram of a wireless communication device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a synchronization means of FIG.

FIG. 3 is a block diagram of the matched filter of FIG.

FIG. 4 is an explanatory diagram showing a waveform of a correlation signal output from the matched filter of FIG.

5 is a block diagram showing a configuration of an integrating circuit included in the integral calculating means of FIG.

6 is an explanatory diagram showing a relationship between a correlation signal and an output of the integrating circuit of FIG.

FIG. 7 is a block diagram showing a configuration of demodulation means in FIG.

FIG. 8 is an explanatory diagram showing a 16QAM scheme signal point arrangement and an error vector on the signal point arrangement diagram.

FIG. 9 is an explanatory diagram of a Viterbi algorithm.

10 is a flowchart showing an operation of the wireless communication device of FIG.

FIG. 11 is a flowchart of a routine for changing processing accuracy.

FIG. 12 is a characteristic diagram showing the relationship between transmission path distortion and error rate for each modulation scheme.

FIG. 13 is a block diagram of a wireless communication device according to a second embodiment of the present invention.

14 is a timing chart showing the demodulated data holding timing in the Viterbi decoding means in FIG.

FIG. 15 is a block diagram of a conventional OFDM signal receiving apparatus.

[Explanation of symbols]

1 Frequency conversion means 2 A / D converter 3 Quadrature detection means 4 synchronization means 5 Fourier transform means 6 Demodulation means 7,27 Viterbi decoding means 11 Reception control means 12, 32 Clock control means 13 Transmission line distortion amount detection means 14 Data accuracy control means 15 Data retention amount control means 16 Modulation method detecting means 41 Matched Filter 42 peak value difference detection means 43 Integral calculation means

   ─────────────────────────────────────────────────── ─── Continued front page    F-term (reference) 5J065 AC02 AD10 AF04 AG05 AH05                       AH18 AH23                 5K004 AA01 AA05 AA08 BB05 BD01                       FD05 FG00 FH03 JD05 JG00                       JH02                 5K014 AA01 BA11 EA07 HA10                 5K022 DD01 DD33 DD42

Claims (14)

[Claims] 1. A wireless communication apparatus for receiving an orthogonal frequency division multiplex signal for transmitting information by a plurality of subcarriers, wherein the wireless communication apparatus obtains a decoded bitstream from received data after quadrature detection. A wireless communication device that changes processing accuracy according to the amount of transmission line distortion. 2. A radio communication apparatus for receiving an orthogonal frequency division multiplex signal for transmitting information by a plurality of subcarriers, wherein the received data after quadrature detection is subjected to a phase correction, and the obtained reception after the phase correction is performed. A synchronization unit that outputs data and obtains and outputs the amount of transmission path distortion based on the received data after the quadrature detection, and Fourier-transforms the received data after the phase correction, and obtains the received signal on the frequency axis. Fourier transforming means for outputting data, demodulating the received data on the frequency axis, outputting the obtained demodulated received data, and based on the received data on the frequency axis and the demodulated received data And a demodulation unit for obtaining and outputting the amount of transmission path distortion, and decoding the demodulated received data using a Viterbi algorithm, and outputting the obtained decoded bit stream. Of these, the Viterbi decoding means for obtaining and outputting the amount of channel distortion based on the demodulated received data, and the amount of channel distortion output by the synchronizing means, the demodulating means, and the Viterbi decoding means. Based on at least one of the above, a transmission path distortion amount detecting means for generating and outputting a data accuracy control signal, and a synchronizing means for changing the bit width of received data processing according to the data accuracy control signal, A data precision control unit that controls the Fourier transform unit, the demodulation unit and the Viterbi decoding unit, and a data holding amount that controls the Viterbi decoding unit so as to change the received data holding amount according to the data precision control signal. A wireless communication device including a control unit. 3. The wireless communication device according to claim 2, wherein the synchronization means obtains a correlation value between the received data after the quadrature detection and a pattern of a predetermined synchronization reference symbol as a correlation function, and a matched filter. A peak value difference detecting means for obtaining and outputting the amount of the transmission path distortion from the difference between the second largest maximum value of the correlation function and a predetermined value in a period corresponding to one symbol period. Wireless communication device. 4. The wireless communication apparatus according to claim 3, wherein the synchronization means stops the clock of the peak value difference detection means during a period when no synchronization reference symbol is input. apparatus. 5. The wireless communication device according to claim 2, wherein the synchronization unit obtains a correlation value between the received data after the quadrature detection and a predetermined synchronization reference symbol pattern as a correlation function. , The integral value of the correlation function in a period corresponding to one symbol period is sequentially obtained while moving the integration period, and the transmission line distortion is changed from the movement range of the integration period such that the integral value becomes a predetermined value or more. A wireless communication device, comprising: an integral calculation means for obtaining and outputting a quantity. 6. The wireless communication device according to claim 5, wherein the synchronization unit stops the clock of the integration calculation unit during a period in which no synchronization reference symbol is input. . 7. The wireless communication device according to claim 2, wherein the demodulation unit determines a distance between an actual signal point and an ideal signal point on a signal point arrangement diagram representing the phase and amplitude of each subcarrier. A wireless communication device, which outputs the amount of distortion of the transmission path. 8. The wireless communication device according to claim 2, wherein the Viterbi decoding unit sets a difference between a branch metric of the maximum likelihood path and a branch metric other than the maximum likelihood path to a predetermined threshold value or more. A radio communication device, wherein the length of a reception data holding period as described above is obtained and output as the amount of the transmission path distortion. 9. The wireless communication device according to claim 2, wherein when the reception data after the quadrature detection is input, the synchronization unit obtains an amount of transmission path distortion based on the data and responds to the amount. When the received data output from the Fourier transform unit is input, the demodulation unit obtains the amount of transmission path distortion based on the data. The bit width of the received data processing in the demodulation means is changed according to this and the amount of transmission path distortion obtained by the synchronization means, and the Viterbi decoding means is the reception data output by the demodulation means. Is input, the amount of transmission line distortion is obtained based on the data, and in accordance with this and the amount of transmission line distortion obtained by the synchronization means and the demodulation means, in the Viterbi decoding means, A wireless communication device, wherein a bit width of received data processing and an amount of received data held are changed. 10. The wireless communication device according to claim 2, wherein the transmission path distortion amount detection means includes a plurality of registers, and the synchronization means, the demodulation means, and the Viterbi decoding among the plurality of registers. A radio communication device, wherein the value of the data accuracy control signal is stored in each of the ones corresponding to the combinations of the amounts of transmission line distortions obtained by the means. 11. A radio communication apparatus for receiving an orthogonal frequency division multiplex signal for transmitting information by a plurality of subcarriers, wherein the received data after quadrature detection is subjected to phase correction, and the obtained reception after phase correction is performed. Synchronizing means for outputting data, Fourier transform means for Fourier transforming the phase-corrected received data, and outputting the obtained received data on the frequency axis, and demodulating the received data on the frequency axis to obtain Demodulation means for outputting the received data after demodulation, the received data after demodulation is decoded using a Viterbi algorithm, and the obtained decoded bit stream is output and the modulation method of the subcarrier is detected. And a Viterbi decoding unit that outputs the data, and the synchronization unit and the Fourier unit that change the bit width of the received data processing according to the modulation method of the subcarrier. Data accuracy control means for controlling the conversion means, the demodulation means and the Viterbi decoding means, and a data holding amount control for controlling the Viterbi decoding means so as to change the received data holding amount according to the modulation method of the subcarrier. And a wireless communication device. 12. The wireless communication device according to claim 11, wherein the Viterbi decoding unit changes an operating frequency according to a modulation scheme of the subcarrier. 13. The wireless communication device according to claim 2, wherein the bit width of the received data processing is changed by fixing the value of a predetermined bit of the received data to zero. apparatus. 14. The wireless communication device according to claim 2, wherein the bit width of received data processing is changed by stopping a clock to a circuit for processing a part of bits of data. A characteristic wireless communication device.