KR100258973B1 - Bimos transistor logic circuit - Google Patents

Abstract

PURPOSE: A BIMOS transistor logic circuit is provided which eliminates noise margin and maximizes a swing width to improve the gate driving performance and the response speed of output signal. CONSTITUTION: A BIMOS transistor logic circuit includes the first MOS transistor(31) whose gate is connected to a signal input port and whose one port is connected to the ground, the second MOS transistor(32) whose gate is connected to an output port and whose one port is connected to the ground, and the first bipolar transistor(35) whose base is connected to the other port of the first MOS transistor and which is connected between the power supply and the output port. The circuit further has the second bipolar transistor(36) whose base is connected to the other port of the second MOS transistor and which is connected between the output port and the ground, a switch(37) for selectively driving the first and second bipolar transistors in response to an input signal, and a resistor connected between the base of the first bipolar transistor and the output port.

Description

Bimos transistor logic circuit

1 is a conventional bimos inverter logic circuit diagram.

2 is a logic circuit diagram of a NAND gate using a conventional inverter.

3 is an inverter logic circuit diagram of a bi-MOS transistor logic circuit of the present invention.

4 is a logic circuit diagram of a NAND gate according to the bi-MOS transistor logic circuit of the present invention.

5 is a logic circuit diagram of a NOR gate according to the bi-MOS transistor logic circuit of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to NAND gate integrated circuits, and more particularly, to a BiMOS transistor logic circuit that improves response speed and widens the level of output potential to prevent malfunction.

In response to the demand for high-density integrated circuit devices (LSIs) driven by high capacities and low power supplies, recently, a BIMOS logic circuit that reduces the number of components and improves operation speed is disclosed in the US Patent Publication No. 4,804,869 entitled "BIMOS LOGICAL CIRCUIT." Was introduced.

FIG. 1 illustrates the conventional bimos inverter logic circuit, and the other of the first and second MOS transistors 11 and 12 and the first MOS transistor 11, each of which comprises an MOS transistor having one terminal grounded. A first bipolar transistor 15 having a terminal and a base terminal connected to each other and having an NPN type, and a second bipolar transistor 16 having a NPN type connected to the other terminal and a base terminal of the second MOS transistor 12 and having a NPN type. And the first and second bipolar transistors 15 and 16 are connected in series to both of the nodes N between the power supply V _CC and the ground, and the gate terminal of the first MOS transistor 11 and the The base terminal of the second bipolar transistor 16 is connected at the node Q, and the gate terminal of the second MOS transistor 12 and the base terminal of the second bipolar transistor 16 are connected at the node P. It is structured.

In addition, a third MOS transistor 13 connected to a power supply V _CC and one terminal thereof, the other terminal connected to the base terminal of the first bipolar transistor 15, and the gate terminal connected to the signal input terminal I. One terminal is connected to the node N, the other terminal is composed of a fourth MOS transistor 14 connected to the base terminal of the second bipolar transistor 16 and the gate terminal is connected to the signal input terminal I. do.

In the operation of the inverter circuit according to the above configuration, when "low" is applied to the signal input terminal I, the third MOS transistor 13 is "on" and the power source (3) is supplied to the base of the first bipolar transistor 15. Current flows from V _CC ), thereby turning on the first bipolar transistor 15. As a result, "high" is formed in the node P and the node N, and "high" is output to the output V _OUT terminal. At the same time, "high" is applied to the gate of the second MOS transistor 12, "on", thereby the base of the second bipolar transistor 16 is grounded "off" and the fourth MOS transistor 14 is also " Off ". Eventually, the first MOS transistor 11 is "off" as the node N is separated from the ground and "low" is applied to the node Q.

At this time, when the signal input to the signal input terminal I is changed from "low" to "high", as the third MOS transistor 13 is "off" and the fourth MOS transistor 14 is "on" The node Q starts to be charged by the output voltage. The first MOS transistor 11 is "on" from the moment when the level of the voltage at which the voltage rises exceeds the forward voltage V _BE between the base and the emitter of the second bipolar transistor 16. As a result, the node P is connected to ground so that the first bipolar transistor 15 and the second MOS transistor 12 are “off” and the output voltage V _OUT is applied by the second bipolar transistor 16. The level of is reversed to "low".

2 is a detailed circuit diagram of a NAND gate using an inverter according to the conventional method, wherein the signal input terminal I is composed of two terminals Ia and Ib for two signal inputs and according to the configuration, the third Morse The transistor 13 is replaced by the fifth and sixth MOS transistors 131 and 132 connected in parallel to each other, and the fourth MOS transistor 14 is the seventh and eighth MOS transistors 141 and 142 connected in series with each other. Are replaced by).

When the "low" is input to the two signal input terminals Ia and Ib, both the fifth and sixth MOS transistors 131 and 132 are "on" and both the seventh and eighth MOS transistors 141 and 142 are both. "Off". As a result, when the first bipolar transistor 15 is "on", "high" is formed and output to the output V _OUT terminal, and at the same time, as the second MOS transistor 12 is "on", the node ( The second bipolar transistor 16 is "off" because Q) is connected to ground. At this time, the first MOS transistor 11 is in an "off" state, and the output V _OUT remains "high" even when the signals input to the two signal input terminals I _a and I _b are inverted to "high." do. When the input signals of the two signal input terminals I _a and I _b are inverted to "high", the fifth and sixth MOS transistors 131 and 132 are "off" and the seventh and eighth MOS transistors 141. As the power supply of the output terminal is charged to the node Q as the 142 is turned on, the second bipolar transistor 16 is turned on, and the output level is gradually switched to low. .

In the NAND gate circuit of the conventional inverter according to the above method, the number of devices is reduced and the operation speed is increased, compared to the previous NAND gate circuit, but the swing width of the output voltage is V _DD -V _BEON to V _BE (the second Formed by the forward bias voltage of the bipolar transistor 16, there is a problem that the full swing is not performed from OV to V _DD .

In order to solve the above problems, the bimorph transistor logic circuit of the present invention has an object to provide a NAND gate capable of full swing without a noise margin of the output stage.

In order to achieve the above object, the bi-MOS transistor logic circuit of the present invention comprises: a first MOS transistor having a gate connected to a signal input terminal and one terminal connected to ground; A second MOS transistor having a gate connected to the output terminal and one terminal connected to the ground; A first bipolar transistor having a base connected to the other electron of the first MOS transistor and connected between a power supply voltage and an output terminal; A second bipolar transistor having a base connected to the other terminal of the second MOS transistor and connected between an output terminal and a ground voltage; Switching means for selectively driving the first bipolar transistor and the second bipolar transistor in response to an input signal; And a resistance means connected to a base terminal and an output terminal of the first bipolar transistor, wherein two signal input terminals replace the signal input terminals for two signal inputs; Fifth and sixth morph transistors, the gates of which are respectively connected to the two signal input terminals and are connected to each other in series by replacing the first MOS transistors; A seventh and eighth morph transistors disposed in parallel with the third MOS transistors and connected in parallel with each other; Two ninth and tenth morph transistors, which are opposed to the fourth MOS transistor and connected in series with each other, to form a NAND gate, wherein two signal input terminals replace the signal input terminals for two signal inputs; An eleventh and twelfth morph transistors connected to the two signal input terminals, respectively, and connected in parallel with each other by replacing the first MOS transistor; Two thirteenth and fourteenth MOS transistors that are opposed to the third MOS transistors and are connected to each other in series; The NOR gate may be configured to include two fifteenth and sixteenth MOS transistors that are opposed to the fourth MOS transistors and are connected in parallel with each other.

Hereinafter, with reference to the accompanying drawings will be described in more detail an embodiment of the bi-MOS transistor logic circuit of the present invention.

3 is an inverter circuit according to the bi-MOS transistor logic circuit of the present invention.

4 is a NAND gate circuit according to the bi-MOS transistor logic circuit of the present invention.

5 is a logic circuit diagram of a NOR gate according to the bi-MOS transistor logic circuit of the present invention.

In the inverter circuit of FIG. 3, the gate is connected to the signal input terminal I, the first MOS transistor 31 having one terminal connected to the power supply Vcc, the other terminal connected to the ground, and the gate connected to the output terminal. A second MOS transistor 32 having one terminal connected to ground, one terminal of the first MOS transistor 31 and a base connected thereto, a collector connected to a power source V _CC , and an emitter connected to a power source V _CC . A first bipolar transistor 35 connected to an output terminal V _OUT positioned between grounds, the other terminal of the second MOS transistor 32, and a base are connected, and a collector is connected to the output terminal V _OUT . The second bipolar transistor 36 to which the emitter is connected to ground, the base of the power supply Vcc and the first bipolar transistor 31, and the other terminal of the output terminal V _OUT and the second bipolar transistor 36. Signal input by selectively connecting Is connected to the chair (I) switching means (37) for forming an output signal corresponding to the signal input to, and the base terminal and the output terminal (V _OUT) of said first bipolar transistor (35) of the first bipolar transistor charging the power supply (V _CC) that is blocked by the forward bias voltage supply (V _CC) and its supplied by the drive (35) in the parasitic capacitances formed between the output terminal (V _OUT) and ground, and the charging And a resistor R ₁ for forming a ground and a path at the time of discharging the power supply and discharging a voltage below the forward bias voltage of the second bipolar transistor 36 to an OV level, and the switching means 37 includes a gate. Is connected to the signal input terminal I, one terminal is connected to the power supply V _CC , and the other terminal is connected to the base of the first bipolar transistor 31. Input The fourth terminal transistor 34 is connected to the terminal I, one terminal is connected to the output terminal V _OUT , and the other terminal is connected to the base terminal of the second bipolar transistor 36.

In addition, the first MOS transistor 31 is composed of a PMOS transistor, and the second, third, and fourth MOS transistors 32, 33, and 34 are composed of NMOS.

In operation of the inverter circuit according to the above configuration, when "low" is applied to the signal input terminal I, the third MOS transistor 33 is "on" and a power source V is applied to the base of the first bipolar transistor 35. _A current flows from _CC ), thereby turning on the first bipolar transistor 35. At this time, if the parasitic capacitor formed between the output terminal (V _OUT ) and the ground is C ₁ , when the power supplied to the first bipolar transistor 35 is formed above the threshold voltage (V _BEON ) is turned on and the capacitor The power V _CC starts to be charged in the C ₁ , and the voltage formed at the output terminal V _OUT is V _DD -V _{BEON by} the resistor R ₁ and the first bipolar transistor 35. by being filled with a formed path V _DD -V _BEON than V _DD to charge the path formed by the resistor (R _1). At this moment, as “high” is applied to the node N, the second MOS transistor 32 is “high” applied to the gate and is “turned on”, and the base of the second bipolar transistor 36 is connected to ground. Connected and " off ". Eventually the node N is disconnected from ground.

In addition, when the input signal is inverted from "low" to "high", the first and fourth MOS transistors 31 and 34 constituted by the NMOS are "turned on" and the base of the second bipolar transistor 36 is output. A path by the first MOS transistor 31, a path by the resistor R ₁ , a fourth MOS transistor 34, and a second MOS transistor 32 as connected to (V _OUT ) and turned “on”. As a path connected to the ground is formed by the second bipolar transistor 36, the power of the base of the first bipolar transistor 35 is discharged through the paths. As a result, the voltage difference between the drain and the source of the second MOS transistor 32 in which the first bipolar transistor 35 is “turned off” and is saturated and “cut off” according to the voltage of the output terminal V _OUT is obtained. When the second bipolar transistor 36 is formed larger than the forward bias voltage V _BEON , the second bipolar transistor 36 is "on". Accordingly, the power supply of the output terminal V _OUT is connected to the path by the second bipolar transistor 36, the path by the fourth and second MOS transistors 34, the resistor R ₁ , and the first MOS transistor. Discharged by a path connected to ground by " 31 ". At this time, when the discharged voltage is lower than the forward bias voltage V _{BEON of} the second bipolar transistor 36, the second bipolar transistor 36 is “off” and subsequent voltage discharge is performed by the resistor R ₁ and the _first voltage. One MOS transistor 31 discharges to the ground level by a path connected to ground, and the level of the output voltage V _OUT is inverted to " low ".

4 is a detailed circuit diagram of a NAND gate using an inverter by a logic circuit of the present invention, wherein the signal input terminal I is composed of two terminals I ₁ and I ₂ for two signal inputs. The first and second MOS transistors 31 are replaced by fifth and sixth MOS transistors 311 and 312 connected in series with each other, and the third and third MOS transistors 33 and 7 are connected to each other in parallel. The fourth MOS transistor 34, which is replaced by 331 and 332, is composed of two ninth and tenth MOS transistors 341 and 342 connected in series with each other.

Its operation is that if the "low" is input to the two signal input terminals (I ₁ , I ₂ ), both the seventh and eighth MOS transistors 331, 332 are "on" and the fifth, sixth, ninth and the like. The tenth MOS transistors 311, 312, 341, 342 are “off”. As a result, the first bipolar transistor 35 is "on", and thus "high" is formed and output from the output V _OUT terminal, and at the same time, the second MOS transistor 32 is "on" and thus the first bipolar transistor 35 is "on". The second bipolar transistor 36 is " off " due to the base of the bipolar transistor 36 being connected to ground. In this case, when the signals input to the two signal input terminals I ₁ and I ₂ are inverted to “high”, the seventh and eighth MOS transistors 331 and 332 are “off” and the fifth, sixth, and fifth As the ninth and tenth MOS transistors 311, 312, 341, and 342 are "on", the second bipolar transistor 36 is "on" while the second bipolar transistor 36 is charged with the output terminal. When the output level gradually changes to " low " and the discharged voltage is lower than the forward bias voltage V _BEON of the second bipolar transistor 36, the resistor R ₁ and the first MOS transistor 31 By the path connected to the ground by the discharge to the ground level, the level of the output voltage (V _OUT ) is formed to OV. In this case, even when “low” is input to only one of the two signal input terminals I ₁ and I ₂ , the seventh and eighth MOS transistors 331 and 332 are connected in parallel, and the fifth and sixth MOS transistors are connected in parallel. Since 311 and 312 and the ninth and tenth MOS transistors 341 and 342 are connected in series, they are operated in the same manner as when "low" is input to the two terminals. That is, when "low" is input to at least one terminal, a NAND gate having "high" is formed as an output terminal.

5 is a detailed circuit diagram of a NOR gate using the inverter according to another embodiment of the present invention, wherein the signal input terminal I includes two terminals I ₁ and I ₂ for inputting two signals. As a result, the first MOS transistor 31 of the inverter is replaced by the eleventh and twelfth MOS transistors 313 and 314 connected in parallel to each other, and the third MOS transistor 33 is connected in series with each other. The fourteenth MOS transistors 333 and 334 are replaced by the fourteenth MOS transistors 333 and 334, and the fourth and second MOS transistors 343 and 344 are connected to each other in parallel.

Its operation is that when the "low" is input to the two signal input terminals (I ₁ , I ₂ ), both the thirteenth and fourteenth MOS transistors (333, 334) are "on" and the eleventh, twelfth, fifteen and Sixteenth MOS transistors 313, 314, 343, and 344 are “off”. As a result, the first bipolar transistor 35 is "on", and thus "high" is formed and output from the output V _OUT terminal, and at the same time, the second MOS transistor 32 is "on" and thus the first bipolar transistor 35 is "on". The second bipolar transistor 36 is " off " due to the base of the bipolar transistor 36 being connected to ground. At this time, when the signals input to the two signal input terminals I ₁ and I ₂ are both “high”, the thirteenth and fourteenth MOS transistors 333 and 334 are “off” and the eleventh, twelfth and As the fifteenth and sixteenth MOS transistors 313, 314, 343, and 344 are "on", the second bipolar transistor 36 is "on" while the second bipolar transistor 36 is charged with the output terminal. When the output level gradually changes to " low " and the discharged voltage is lower than the forward bias voltage V _BEON of the second bipolar transistor 36, the resistor R ₁ and the first MOS transistor 31 By the path connected to the ground by the discharge to the ground level, the level of the output voltage (V _OUT ) is formed to OV.

In this case, even when “high” is input to only one of the two signal input terminals I ₁ and I ₂ , the thirteenth and fourteenth MOS transistors 333 and 334 are connected in series and the eleventh and twelfth MOS transistors. Since 313 and 314 and the fifteenth and sixteenth MOS transistors 343 and 344 are connected in parallel, they are operated in the same manner as when "high" is input to the two terminals. That is, when "high" is input to at least one terminal, the NOR gate having "low" is formed as an output terminal.

In addition, although the inverter, the NAND gate, and the NOR having one input and two signals as inputs are described as the embodiments of the present invention, it is apparent that the bimos transistor logic circuit of the present invention can be configured with a gate having a plurality of inputs. .

Accordingly, the bi-MOS transistor logic circuit of the present invention includes two morph transistors for driving two bipolar transistors, and switching means for selectively driving them in response to an input signal, and swings a voltage formed at an output terminal. By providing a resistor to maximize the swing width of the output voltage without noise margin, the driving ability of the gate is improved and the response speed of the output signal is improved.

Claims (8)

A first MOS transistor having a gate connected to the signal input terminal and one terminal connected to the ground; A second MOS transistor having a gate connected to the output terminal and one terminal connected to the ground; A first bipolar transistor having a base connected to the other terminal of the first MOS transistor and connected between a power supply voltage and an output terminal; A second bipolar transistor having a base connected to the other terminal of the second MOS transistor and connected between an output terminal and a ground voltage; Switching means for selectively driving the first bipolar transistor and the second bipolar transistor in response to an input signal; And resistance means connected to the base terminal and the output terminal of the first bipolar transistor. The bi-MOS transistor logic circuit of claim 1, wherein the first and second MOS transistors each include a PMOS transistor and an NMOS transistor. 2. The biMOS transistor logic circuit of claim 1, wherein the first and second bipolar transistors are of an NPN type. The switching circuit of claim 1, wherein the switching unit comprises: a third MOS transistor for driving the first bipolar transistor in response to an input signal; And a fourth MOS transistor configured to apply an output voltage to the gate of the third bipolar transistor in response to an input signal. The logic circuit of claim 4, wherein the third and fourth MOS transistors are configured of NMOS transistors. 6. A first MOS transistor whose gate is connected to the signal input terminal and one terminal is connected to the ground, a second MOS transistor whose gate is connected to the output terminal and one terminal is connected to ground, and the base is connected to the other terminal of the first MOS transistor A first bipolar transistor connected between a power supply voltage and an output terminal, a second bipolar transistor connected with a base connected to the other terminal of the second MOS transistor, and connected between an output terminal and a ground voltage, and the first bipolar transistor in response to an input signal. A bi-MOS transistor logic circuit comprising a transistor and switching means for selectively driving the second bipolar transistor, and resistance means connected to a base terminal and an output terminal of the first bipolar transistor, wherein the bi-MOS transistor logic circuit includes: Two signal input terminals to replace the signal input terminals; Fifth and sixth morph transistors, the gates of which are respectively connected to the two signal input terminals and are connected to each other in series by replacing the first MOS transistors; A seventh and eighth morph transistors disposed in parallel with the third MOS transistors and connected in parallel with each other; And a ninth and tenth MOS transistors disposed in series with each other and opposing the fourth MOS transistors to form a NAND gate. A first MOS transistor whose gate is connected to the signal input terminal and one terminal is connected to the ground, a second MOS transistor whose gate is connected to the output terminal and one terminal is connected to ground, and the base is connected to the other terminal of the first MOS transistor A first bipolar transistor connected between a power supply voltage and an output terminal, a second bipolar transistor connected with a base connected to the other terminal of the second MOS transistor, and connected between an output terminal and a ground voltage, and the first bipolar transistor in response to an input signal. A bi-MOS transistor logic circuit comprising a transistor and switching means for selectively driving the second bipolar transistor, and resistance means connected to a base terminal and an output terminal of the first bipolar transistor, wherein the bi-MOS transistor logic circuit includes: Two signal input terminals to replace the signal input terminals; An eleventh and twelfth morph transistors connected to the two signal input terminals, respectively, and connected in parallel to each other by replacing the first MOS transistor; Two thirteenth and fourteenth MOS transistors that are opposed to the third MOS transistors and are connected to each other in series; And a fifteenth and sixteenth MOS transistors disposed in parallel with each other and connected to the fourth MOS transistors to form a NOR gate. The predetermined morph transistor according to any one of claims 1 to 6, wherein the bi-MOS transistor logic circuit is connected to the first and third morph transistors in parallel with each other by a predetermined signal input. And a predetermined MOS transistor connected in series and parallel with the fourth MOS transistor, so that a gate having a plurality of inputs can be configured.