KR100258213B1 - Time Division Enbit Counter Circuit in Synchronous Transmission Equipment - Google Patents

Time Division Enbit Counter Circuit in Synchronous Transmission Equipment Download PDF

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KR100258213B1
KR100258213B1 KR1019970076019A KR19970076019A KR100258213B1 KR 100258213 B1 KR100258213 B1 KR 100258213B1 KR 1019970076019 A KR1019970076019 A KR 1019970076019A KR 19970076019 A KR19970076019 A KR 19970076019A KR 100258213 B1 KR100258213 B1 KR 100258213B1
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memory
signal
circuit
synchronous transmission
latch circuit
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KR1019970076019A
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Korean (ko)
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KR19990056043A (en
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박재영
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윤종용
삼성전자주식회사
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0623—Synchronous multiplexing systems, e.g. synchronous digital hierarchy/synchronous optical network (SDH/SONET), synchronisation with a pointer process
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/54—Ring counters, i.e. feedback shift register counters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Computer Hardware Design (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE: A time sharing N-bit counter circuit in an SDH(Synchronous Digital Hierarchy) is provided to design a plurality of counters with a time-sharing method using a RAM, thereby improving an usage efficiency of an FPGA. CONSTITUTION: In a time sharing N-bit counter circuit in a synchronous digital hierarchy, an N-decimal counter(100) receives a frame start signal(FRS) and a clock signal(CLK) to generate a time slot address. A memory(110) stores an N number of hexadecimal-operated values. A latch circuit(112) maintains the whole data of the memory upon a writing time of the memory. A +1 operation circuit(113) carries out a +1 operation for the output of the latch circuit by a carrier signal and clears the output of the latch circuit to zero by a clear signal.

Description

동기식 전송장치에 있어서 시분할 엔비트 카운터회로Time Division Enbit Counter Circuit in Synchronous Transmission Equipment

본 발명은 동기식 전송장치에서 시분할 카운터에 관한 것으로, 특히 동기식 전송장치의 계위신호단위(TU12;Tributary Unit 12)의 PPS의 횟수를 카운팅하는 동기식 전송장치에 있어서 시분할 n비트 카운터회로에 관한 것이다.The present invention relates to a time division counter in a synchronous transmission apparatus, and more particularly, to a time division n-bit counter circuit in a synchronous transmission apparatus counting the number of PPSs of a tributary unit 12 (TU12) of a synchronous transmission apparatus.

종래 동기식 전송장치(SDH;Synchronous Digital Hierarchy)에서 TU12 단위의 PPS의 횟수를 카운트하는 카운터를 구현함에 있어 구성회로의 복잡화로 FPGA의 사용효율을 떨어 뜨리는 문제점이 있다.In implementing a counter that counts the number of PPSs in TU12 units in a conventional synchronous transmission device (SDH), there is a problem in that the efficiency of the FPGA is reduced due to the complexity of the configuration circuit.

따라서 본 발명의 목적은 동기식 전송장치의 TU12 단위의 PPS의 횟수를 카운팅하는 카운터를 구현함에 있어, 메모리(RAM)를 사용하여 시분할 방식으로 다수의 카운터를 설계함으로써, FPGA의 사용효율을 향상시키는 회로를 제공함에 있다.Accordingly, an object of the present invention is to implement a counter for counting the number of PPS of TU12 unit of a synchronous transmission device, by designing a plurality of counters in a time division manner using a memory (RAM), thereby improving the efficiency of the FPGA In providing.

상기 목적을 수행하기위한 본 발명은 동기식 전송장치의 PPS카운터에 있어서, 프레임시작신호(FRS)와 클럭신호(CLK)를 받아 타임슬롯 어드레스를 발생시키는 N진 카운터와,N개의 16진 연산된 값을 저장하는 메모리와,상기 메모리의 라이트시간동안 상기 메모리의 전 데이터를 유지하기 위한 래치회로와,상기래치회로의 출력을 케리어(CAR)신호에 의하여 ＋1연산을 수행하고 클리어(CLR)신호에 의하여 제로로 클리어하는 ＋1연산회로로 구성됨을 특징으로 한다.According to an aspect of the present invention, there is provided a PPS counter of a synchronous transmission apparatus, comprising: an N-degree counter for receiving a frame start signal (FRS) and a clock signal (CLK) to generate a timeslot address, and N hexadecimal calculated values. And a latch circuit for holding all the data of the memory during the write time of the memory, and a +1 operation on the output of the latch circuit by a carrier signal and a clear (CLR) signal. It consists of a +1 operation circuit which clears to zero.

도 1는 본 발명의 실시예에 따른 동기식 전송장치의 계위신호단위(TU12;Tributary Unit 12)의 PPS의 횟수 카운팅 회로도1 is a circuit diagram counting the number of PPSs of a tributary unit 12 (TU12) of a synchronous transmission apparatus according to an exemplary embodiment of the present invention.

도 2는 도 1의 실시예의 동작타이밍도2 is an operation timing diagram of the embodiment of FIG.

이하 본 발명의 바람직한 실시예의 상세한 설명이 첨부된 도면들을 참조하여 설명될 것이다.하기에서 각 도면의 구성요소들에 참조부호를 부가함에 있어, 동일한 구성요소들에 대해서는 비록 다른 도면상에 표시되더라도 가능한한 동일한 부호를 가지도록 하고 있음에 유의해야 한다. 또한 본 발명을 설명함에 있어, 관련된 공지 기능 또는 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명은 생략할 것이다. 그리고 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의내려진 용어들로서 이는 사용자 또는 칩설계자의 의도 또는 관례 등에 따라 달라질 수 있으며, 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A detailed description of a preferred embodiment of the present invention will now be described with reference to the accompanying drawings. In the following, reference numerals are given to components of each drawing, even though the same components are shown in different drawings. Note that they have the same sign. In describing the present invention, when it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. Terms to be described later are defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or a chip designer, and the definitions should be made based on the contents throughout the present specification.

도 1은 본 발명의 실시예에 따른 동기식 전송장치의 계위신호단위(TU12;Tributary Unit 12)의 PPS의 횟수를 카운터회로도로서1 is a counter circuit diagram illustrating the number of PPSs of a tributary unit 12 (TU12) of a synchronous transmission apparatus according to an exemplary embodiment of the present invention.

프레임시작신호(FRS;Frame Ready Start)와 클럭신호(CLK)를 받아 타임슬롯 어드레스를 발생시키는 63진 카운터(100)와, 63개의 16진 연산된 값을 저장하는 64×4의 메모리(RAM)(110)와, 상기 메모리(RAM)의 라이트시간동안 상기 메모리(110)의 전 데이터를 유지하기 위한 래치회로(112)와,상기래치회로(112)의 출력을 케리어(CAR;CARRIER)신호에 의하여 ＋1연산을 수행하고 클리어(CLR;CLEAR)신호에 의하여 제로로 클리어하는 ＋1연산회로(113)로 구성된다.A 63-degree counter 100 that receives a frame start signal (FRS) and a clock signal (CLK) to generate a timeslot address, and a 64 × 4 memory (RAM) that stores 63 hexadecimal calculated values. And a latch circuit 112 for holding all data of the memory 110 during a write time of the memory RAM, and an output of the latch circuit 112 to a carrier signal. +1 operation circuit 113 which performs +1 operation and clears to zero by a clear (CLR) CLEAR signal.

도 2는 본 발명의 실시예의 도 1의 동작파형도로서2 is an operating waveform diagram of FIG. 1 according to an embodiment of the present invention;

(2a)는 카운터(100),메모리(110),래치회로(112)의 클럭으로 인가되고,(2a) is applied to the clock of the counter 100, the memory 110, the latch circuit 112,

(2b)는 프레임시작신호(FRS)로서 상기 카운터(100)로 입력되며,2b is input to the counter 100 as a frame start signal FRS,

(2c)는 케리어(CAR)신호로서 1+연산회로(113)에 입력되고,(2c) is input to the 1+ arithmetic circuit 113 as a carrier (CAR) signal,

(2d)는 클리어(CLR)신호로서 1+연산회로(113)에 입력되며,2d is input to the 1+ operation circuit 113 as a clear (CLR) signal,

(2e)는 카운터(100)의 발생 어드레스신호에 대한 파형이며,(2e) is a waveform of the generated address signal of the counter 100,

(2f)는 메모리(110)의 출력 데이터 파형이고,2f is an output data waveform of the memory 110,

(2g)는 래치회로(112)의 출력 데이터 파형이며,(2g) is an output data waveform of the latch circuit 112,

(2h)는 ＋1연산회로(113)의 출력 데이터 파형이다.(2h) is an output data waveform of the +1 operation circuit 113.

따라서 본 발명의 구체적 일 실시예를 도 1 및 도 2를 참조하여 상세히 설명하면,Therefore, a specific embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

도 1의 예와 같이 63진 카운터(100)는 (2a)와 같이 프레임시작(FRS)가 "로우"가 될시 (2b)와 같이 클럭신호(CLK)의 상승에지에 동기되어 초기값으로 클리어되며, 상기 프레임시작(FRS)가 "하이"가 될시 (2b)의 클럭신호의 상승에지마다 ＋1씩 카운팅 되며, 타임슬롯 데이터인 (2e)와 같이 어드레스신호를 발생시킨다. 상기 1클럭 주기마다 (2e)와 같은 어드레스가 메모리(RAM)(110)의 어드레스에 입력이 되고, (2a)의 클럭신호(CLK)가 "하이"인 반주기 동안 메모리(110)는 리드 상태가 되며, 래치회로(112)는 통과 모드가 되어 전 타임슬롯시간에 저장된 데이터가 메모리(110)에서 출력되어 래치회로(112)를 통과한 후 ＋1연산회로(113)에 입력된다. 이때 (2c)와 같은 케리어신호가 "하이"이고,(2d)와 같이 클리어신호(CLR)가 "로우"가 되면 (2g)와 같이 래치회로(112)의 래치출력신호에 ＋1을 합하여 (2h)와 같이 출력하며, (2c)의 케리어신호(CAR)와 (2d)와 같은 클리어신호(CLR)가 모두 "로우"이면 (2g)와 같은 래치출력를 (2h)와 같이 어드레스 출력신호로 출력한다. 만약 카운터(100)의 값이 0Fh이면 0Fh를 계속유지한다. (2c)와같이 케리어신호(CAR)에 무관하게 클리어(CLR)가 "하이"이면 (2g)와 같이 래치출력에 무관하게 (2h)와 같이 어드레스 출력(ADDER OUT)신호를 제로(ZERO)로 출력한다.(2a)와 같이 클럭신호(CLK)가 "로우"인 반주기 동안 래치회로(112)는 래치모드가 되어 전 데이터를 유지하므로서 ＋연산회로(113)의 입출력 신호에는 변화가 없으며, 메모리(110)는 라이트상태가 되어 ＋1연산회로(113)의 동작에 의한 (2h)와 같은 출력신호가 메모리(RAM)(110)에 저장된다. 다음 주기의 클럭의 상승에지에서는 상기와 같은 동작이 63번 반복되어 63개의 시 분할된 16진 카운터가 동작하게 된다.As shown in the example of FIG. 1, the 63-definition counter 100 is cleared to its initial value in synchronization with the rising edge of the clock signal CLK as shown in (2b) when the frame start FRS becomes "low" as shown in (2a). When the frame start FRS becomes " high ", the signal is counted by +1 for each rising edge of the clock signal of (2b), and an address signal is generated as shown in the time slot data (2e). An address such as 2e is input to the address of the memory 110 every one clock period, and the memory 110 is in a read state during a half period in which the clock signal CLK of (2a) is "high". The latch circuit 112 enters the pass mode, and data stored in the entire time slot time is output from the memory 110, passes through the latch circuit 112, and is input to the +1 operation circuit 113. At this time, when the carrier signal as shown in (2c) is "high" and the clear signal CLR as "low" as in (2d), +1 is added to the latch output signal of the latch circuit 112 as shown in (2g) (2h). If the carrier signal CAR of 2c and the clear signal CLR of 2d are both "low", the latch output like 2g is output as an address output signal like 2h. . If the value of the counter 100 is 0Fh, 0Fh is kept. If the clear (CLR) is "high" regardless of the carrier signal (CAR) as shown in (2c), the address output (ADDER OUT) signal is zeroed as shown in (2h) regardless of the latch output as shown in (2g). As shown in (2a), the latch circuit 112 enters the latch mode and holds all data during the half cycle in which the clock signal CLK is "low", and there is no change in the input / output signal of the + operation circuit 113, and the memory Reference numeral 110 denotes a write state, and an output signal such as (2h) by the operation of the +1 operation circuit 113 is stored in the memory (RAM) 110. On the rising edge of the clock of the next period, the above operation is repeated 63 times, and the 63 time division hexadecimal counters are operated.

상술한 바와같이 종래는 SDH장비의 TU12 단위의 PPS의 횟수를 카운팅하는 카운터를 구현함에 있어, 플립프롭을 사용하였을 경우 매우 많은 갯수가 필요하며, 소용량의 FPGA로 구현이 매우 어려우나,본 발명은 메모리(RAM)를 사용할 수 있는 FPGA에서 단 몇 개의 프로그램 로직만을 사용하여 구현 가능하므로써 FPGA를 효율적으로 활용할 수 있는 이점이 있다.As described above, in implementing a counter for counting the number of PPS of TU12 units of the SDH device, a very large number is required when using flip-flops, and it is very difficult to implement a small-capacity FPGA. In FPGAs that can use (RAM), it can be implemented using only a few program logics, which has the advantage of making efficient use of FPGAs.

Claims (1)

동기식 전송장치의 PPS카운터에 있어서,In the PPS counter of the synchronous transmission device, 프레임시작신호(FRS)와 클럭신호(CLK)를 받아 타임슬롯 어드레스를 발생시키는 N진 카운터(100)와,N개의 16진 연산된 값을 저장하는 메모리(110)와, 상기 메모리(110)의 라이트시간동안 상기 메모리(110)의 전 데이터를 유지하기 위한 래치회로(112)와, 상기래치회로(112)의 출력을 케리어(CAR)신호에 의하여 ＋1연산을 수행하고 클리어(CLR)신호에 의하여 제로로 클리어하는 ＋1연산회로(113)로 구성됨을 특징으로 하는 동기식 전송장치에 있어서 시분할 n비트 카운터회로.An N-decimal counter 100 that receives a frame start signal FRS and a clock signal CLK to generate a timeslot address, a memory 110 that stores N hexadecimal calculated values, and a memory 110 of the memory 110. The latch circuit 112 for holding all the data of the memory 110 and the output of the latch circuit 112 are performed by a carrier signal and a clear signal by the clear signal. A time division n-bit counter circuit in a synchronous transmission device comprising a +1 operation circuit (113) for clearing to zero.
KR1019970076019A 1997-12-29 1997-12-29 Time Division Enbit Counter Circuit in Synchronous Transmission Equipment KR100258213B1 (en)

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