KR100257676B1 - Pci interface card - Google Patents

Abstract

PURPOSE: A PCI interface card of a computer is provided to process a PCI interface, and to simultaneously enable a data bus which a logic unit uses to interface 8-bit or 16-bit by considering a timing for enabling the logic unit to process a transaction. CONSTITUTION: A PCI matching unit is equipped with an address buffer(41), an address latch(42), a data latch(44) and a multiplexer(43). The multiplexer(43) multiplexes and outputs an address and data applied from a PCI bus. The address latch(42) outputs the address applied from the multiplexer(43) till a frame signal is applied from the PCI bus. The address buffer(41) stores and outputs the address applied from the address latch(42). The data latch(44) latches data applied from a logic unit(10), converts and outputs the data.

Description

Your computer's PCI interface card

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer, and more particularly, to a PCI interface card of a computer capable of performing logic to be implemented in a PCI (Peripheral Component Interconnection) type interface card without additional logic.

1, the PCI interface card of the conventional computer includes a logic unit 10, a PCI interface unit 30, and a PLD (Programmable Logic Device) unit 20, The PCI interface unit 30 has a unique number of the corresponding PCI interface card and receives a transaction assigned to itself from the PCI bus inside the computer, And outputs the authorized transaction to the logic unit 10. [0050] When the PLD unit 20 outputs a transaction from the PCI interface unit 30 to the logic unit 10, the PLD unit 20 receives a control signal from the PCI interface unit 30 to match the timing of the signal and the interface of the bus, And outputs a corresponding control signal to the logic unit side.

The operation of the PCI interface card of the conventional computer configured as described above will be described below.

When a transaction assigned to the PCI interface card through the PCI bus occurs, the PCI interface unit 30 checks the unique number included in the transaction and confirms whether the corresponding transaction is a transaction corresponding to the transaction, It outputs its own unique number to the PCI bus side and informs it to process transactions authorized to it. In the case of a write operation from the PCI bus to the PCI interface card, the PCI interface unit 30 receives the address and data from the PCI bus and transmits data to the logic unit 10 to instruct the execution of the transaction , The PLD unit 20 receives a control signal from the PCI interface unit 30 because the timing of the signal and the structure of the data bus and the address bus are different between the PCI interface unit 30 and the logic unit 10, And a control signal for matching the address bus to the logic unit 10 side. The logic unit 10 processes a transaction received from the PCI interface unit 30 according to a control signal applied from the PLD unit 20 and notifies the PCI interface unit 30 of the result of the transaction, The PCI bus 30 outputs the result of processing to the PCI bus side, thereby terminating the PCI transaction.

As described above, the PCI interface card of the conventional computer has a problem that the timing or the bus interface between the interface unit and the logic unit to be implemented does not match, and thus additional logic for interfacing the timing or the bus with the PLD unit is required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to provide a data processing apparatus and a data processing method capable of processing a PCI transaction in consideration of a timing at which a logic unit can process a transaction, Bit of the PCI interface card.

According to an aspect of the present invention, there is provided a PCI interface card of a computer having a logic unit for processing and outputting an applied transaction, the method comprising: registering the logic unit with a PCI bus, A PCI matching unit for checking whether the transaction is a transaction assigned to itself and receiving a transaction assigned thereto and outputting it to the logic unit; And a PCI interface unit that outputs a control signal corresponding to the function of the logic unit and includes a counter unit for matching timing between the logic unit and the PCI bus.

The PCI matching unit includes: a multiplexer for multiplexing and outputting data and addresses applied from a PCI bus; An address latch for maintaining an address applied from the multiplexer until a frame signal is applied from the PCI bus; An address buffer for storing an address applied from the address latch and outputting the address to the logic unit; And a data latch for latching data applied from the logic unit corresponding to an address applied from the address buffer and outputting the latched data according to a standard of a PCI bus to be output.

The counter unit performs a logic operation on a predetermined level of frame signal applied from the PCI bus, a predetermined level of data transfer preparation signal applied from the PCI bus, and a predetermined level of a preparation signal applied from the logic unit, A first logic gate for outputting a signal; A counter for starting counting according to a control signal applied from the first logic gate and outputting a count value; And a second logic gate receiving a count value as an input from the counter and outputting a control signal of a predetermined level when a predetermined count value is applied thereto.

1 is a block diagram of a PCI interface card of a conventional computer.

2 is a block diagram of a PCI interface card according to the present invention;

3 is a detailed block diagram of the PCI matching unit shown in FIG.

4 is a detailed block diagram of the counter unit shown in FIG.

Description of the Related Art [0002]

10: logic section 20: PLD section

30, 60: PCI interface unit 40: PCI matching unit

41: address buffer 42: address latch

43: multiplexer 44: data latch

50: counter part 51: first logic gate

52: 3-bit counter 53: second logic gate

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a PCI interface card according to the present invention. As shown in FIG. 2, the PCI interface unit 60 includes a logic unit 10 and a PCI interface unit 60. The logic unit 10 performs a transaction applied from the PCI interface unit 60. The PCI interface unit 60 has its own unique number and performs a transaction corresponding to itself in a transaction applied from the PCI bus Outputs it to the logic unit 10, and provides an interface by matching the timing of data transmission with the logic unit 10. The PCI interface unit 60 includes a PCI matching unit 40 and a counter unit 50. The PCI matching unit 40 includes an address buffer 41, An address latch 42, a data latch 44, and a multiplexer 43, as shown in FIG. The multiplexer 43 multiplexes the address and data supplied from the PCI bus and outputs the multiplexed data. The address latch 42 holds the address applied from the multiplexer 43 until the frame signal is applied from the PCI bus. The address buffer 41 stores and outputs the address applied from the address latch 42. The data latch 44 latches the data applied from the logic unit 10 corresponding to the address and outputs the data Converts it to conform to the standard, and outputs it to the multiplexer 43 side.

On the other hand, the counter unit 50 includes a first logic gate 51, a second logic gate 53, and a 3-bit counter 52.

The first logic gate 51 outputs a high level signal when a low level frame signal and a data transfer preparation signal are received from the PCI bus and a low level preparation signal is received from the logic unit 10, . The 3-bit counter 52 receives a high-level signal from the first logic gate 51 and starts counting and outputs the counted value as 3-bit binary data. The second logic gate 53 outputs a high level signal when the binary data output from the 3-bit counter 52 is 101.

On the other hand, in the present embodiment, the address bus and the data bus of the logic unit 10 are separated, and the address bus is composed of m bits and the data bus is composed of 16 bits.

The present invention configured as described above operates as follows.

Generally, a PCI interface card uses a 32-bit address / data bus. Accordingly, various types of transactions flow on the 32-bit PCI bus. Since each PCI interface card has a unique number assigned thereto, the PCI interface unit 60 receives only transactions assigned to the PCI bus, do. The multiplexer 43 separates the address and the data in the transaction to be applied and outputs the separated m-bit address to the logic unit 10 via the address latch and the address buffer. The logic unit 10 outputs data corresponding to the address of m bits applied from the address buffer 41 through the data bus. Since the logic unit 10 is composed of a 16-bit data bus, the first 16 The bit data is latched by the data latch 44. When the second 16-bit data is output, the 16-bit data is output together with the first 16-bit data, thereby outputting the 32-bit data.

Meanwhile, when a transaction assigned to the PCI interface card according to the present invention is applied to the PCI bus, the corresponding PCI interface card receives a low-level frame signal and a low-level data transfer preparation signal from the PCI bus. If the logic unit 10 of the PCI interface card is not ready to process a transaction, a low-level ready signal is output, and a low-level frame signal, a low-level data transfer ready signal, and a low- And is applied to the first logic gate 51. Accordingly, the first logic gate 51 outputs a high level control signal to operate the counter 52. The counter 52 starts counting in accordance with the control signal applied from the first logic gate 51 and outputs the count value as binary data to the second logic gate 53. When the count value becomes 5, That is, when 101 is output, it indicates that the preparation signal output timing of the logic unit 10 is late. Therefore, the second logic gate 53 outputs a high-level control signal to control the PCI Releases the bus, and terminates the transaction.

In this case, the count value of the counter 52 can be arbitrarily adjusted, and the timing can be adjusted with the PCI bus by suitably adjusting it according to the type and function of the logic unit 10 of the PCI interface card.

As described above, according to the present invention, a PCI transaction can be processed in consideration of a timing at which a logical part of a PCI interface card becomes ready to process a transaction, and at the same time, a specification of a data bus and an address bus, Regardless of whether it is different from the standard.

Claims (3)

And a logic unit (10) for processing and outputting an applied transaction, wherein the logic unit (10) and the PCI bus are matched with each other so that a transaction received from the PCI bus A PCI matching unit 40 for receiving a transaction that is assigned to itself and outputting it to the logic unit 10; And a PCI interface unit 60 that outputs a control signal corresponding to the function of the logic unit 10 and includes a counter unit 50 for matching the timing of the PCI bus with the logic unit 10 The PCI interface card of the computer. The system of claim 1, wherein the PCI matching unit (40) comprises: a multiplexer (43) for multiplexing and outputting data and addresses applied from the PCI bus; An address latch (42) for holding an address applied from the multiplexer (43) until a frame signal is applied from the PCI bus; An address buffer 41 for storing an address applied from the address latch 42 and outputting the address to the logic unit 10; And a data latch 44 latching data applied from the logic unit 10 corresponding to an address applied from the address buffer 41 and outputting the latched data according to a standard of the PCI bus to be output. The computer's PCI interface card. The logic unit (10) according to claim 1, wherein the counter unit (50) comprises: a frame signal of a predetermined level applied from the PCI bus; a data transfer preparation signal of a predetermined level applied from the PCI bus; A first logic gate 51 for logically operating the ready signal and outputting a corresponding control signal; A 3-bit counter (52) for starting counting according to a control signal applied from the first logic gate (51) and outputting a count value; And a second logic gate (53) receiving a count value from the 3-bit counter (52) as an input and outputting a control signal of a predetermined level to the PCI bus when a predetermined count value is applied thereto PCI interface card.