KR100257068B1 - Semiconductor device and method for fabricating the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a method for manufacturing the same are to reduce a short channel effect and a thyristor capacitance in an SOI(silicon on insulator) device, thereby improving an operating characteristic. CONSTITUTION: A buried oxide film(31a) is formed in a semiconductor substrate(30a), and a gate gap nitride film(35) is close to the buried oxide film. A gate electrode(34) and a gate oxide film(33) are laminated on the gate gap nitride film. A sidewall spacer(37) is formed on sidewalls of the gate electrode and gate gap nitride film. A p-typed semiconductor layer(32) functioning as a channel region is formed on the gate oxide film. An epitaxial layer(40) is formed on a sidewall of the p-typed semiconductor layer in such a way that it is close to the p-typed semiconductor layer in a region in which a device operate and it is not close to the p-typed semiconductor layer in a region in which the device does not operate.

Description

Semiconductor device and method for manufacturing the same {Semiconductor device and method for fabricating the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device suitable for improving the operating characteristics of an SOI device and a manufacturing method thereof.

Referring to the accompanying drawings, a conventional semiconductor device and a manufacturing method thereof will be described.

1 is a cross-sectional view showing a conventional semiconductor device, Figures 2a to 2c is a process cross-sectional view showing a manufacturing method of a conventional semiconductor device.

In the conventional semiconductor device, as shown in FIG. 1, in an SOI substrate in which a buried oxide film 2 and a P-type semiconductor layer 3 are formed in the semiconductor substrate 1, trench etching is performed on the P-type semiconductor layer 3. The field oxide film 5 is formed so as to be isolated from the active region. A gate oxide film 6a and a gate electrode 7a are formed in the trench by digging a trench in one region of the P-type semiconductor layer 3. The source / drain regions 9b / 9c formed of n-type impurity ions in the surface of the P-type semiconductor layer 3 on the side of the gate electrode 7a are partially overlapped with the edges of the gate electrode 7a. . Further, a body contact impurity region 9a is formed in the surface of the P-type semiconductor layer 3 on which the gate electrode 7a is not formed so as to be in contact with the P-type semiconductor layer 3.

In the conventional method for manufacturing a semiconductor device having such a configuration, as shown in FIG. 2A, the P-type semiconductor layer 3 of the semiconductor substrate 1 in which the buried oxide film 2 and the P-type semiconductor layer 3 are formed is formed. Anisotropic etching is performed by a photo process to form a plurality of trenches 4.

As shown in FIG. 2B, an oxide film is deposited to fill a trench in the semiconductor substrate 1, and then planarized by an etch back or chemical mechanical polishing to form a field oxide film 5. A trench for forming a gate electrode is formed on the active region of the P-type semiconductor layer 3. After that, a thin oxide film 6 for forming a gate oxide film is formed on the entire surface, and a polysilicon layer 7 for forming a gate electrode is deposited on the oxide film 6. Thereafter, after the photoresist film 8 is applied to the entire surface, the photoresist film is selectively patterned so that the photoresist film remains only on the trenches formed in the P-type semiconductor layer 3 in order to form the gate electrode in an exposure and development process.

As shown in FIG. 2C, the polysilicon layer 7 and the oxide film 6 are anisotropically etched using the patterned photosensitive film 8 as a mask to form a gate electrode 7a and a gate oxide film 6a. Then, n-type impurity ions are implanted using the gate electrode 7a as a mask to form source / drain regions 9b / 9c in the P-type semiconductor layer 3 on both sides of the gate electrode 7a. In this case, the source / drain regions 9b and 9c are formed to partially overlap the edges of the gate electrode 7a.

The conventional semiconductor device and its manufacturing method as described above has the following problems.

First, since the material for forming the gate electrode is first deposited and then patterned, the layout needs to be defined larger than that of the etched pattern. Therefore, the layout is increased. Accordingly, the area where the gate electrode and the source / drain region overlap each other increases, so that parasitic capacitance is increased. This increases the operating speed of the device.

Second, since the gate oxide film is formed after the trench is formed, the operation reliability of the gate oxide film is degraded by etching damage.

Third, the thickness of the channel is adjusted by trench etching, but when the thickness of the channel is thin, it is difficult to control the etching. For this reason, the overall uniformity of the device is reduced.

Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor device suitable for improving operation characteristics by reducing short channel effects and parasitic capacitance in an SOI device, and a method of manufacturing the same.

1 is a cross-sectional view showing a conventional semiconductor device

2A through 2C are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

3 is a plan view showing a semiconductor device of the present invention

4A is a cross-sectional view taken along the line II of FIG.

4B is a cross-sectional view taken along the line II-II of FIG. 3.

5A to 5K are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

Explanation of symbols for the main parts of the drawings

30, 30a: semiconductor substrate 31, 31a: buried oxide film

32: P-type semiconductor layer 33: gate oxide film

34: gate electrode 35: gate cap nitride film

36: cap oxide film 37: side wall spacer

38: interlayer oxide film 39: semiconductor layer

40: epitaxial layer 41: planar protective film

A semiconductor device according to the present invention for achieving the above object is a first buried insulating film formed on a semiconductor substrate, a gate cap nitride film in contact with the first buried insulating film, a gate electrode and a gate insulating film formed by stacking the gate cap nitride film and a semiconductor A layer, a sidewall spacer formed on side surfaces of the gate electrode and the gate cap nitride film, an epi layer formed in contact with both sides of the semiconductor layer, a second buried insulating film formed on both sides of the epi layer and between the epi layer and thinner than the epi layer, And a planar protective film formed between the first buried insulating film and the second buried insulating film, and a source / drain region formed in the surface of the epi layer.

The method of manufacturing a semiconductor device of the present invention configured as described above is a step of forming a gate oxide film, a gate electrode, a gate cap insulating film, and a cap insulating film in a first semiconductor substrate including the first buried insulating film and the first semiconductor layer. Forming a sidewall spacer on side surfaces of the gate oxide film, the gate electrode, the gate cap insulating film, and the cap insulating film; and forming an interlayer oxide film and a second semiconductor layer on the exposed first semiconductor layers on both sides of the sidewall spacer. And removing the cap insulating layer using the second semiconductor layer and the gate electrode as a mask, and anisotropically etching the sidewall spacers so that the first semiconductor layers on both sides of the sidewall spacers are exposed. A transistor is formed on the first semiconductor substrate on both sides of the sidewall spacer using an electrode as a mask. Forming a tooth, forming an epi layer in the trench of the first semiconductor substrate so as to be in contact with the first semiconductor layer formed below the gate electrode, and forming a planar protective film up to the height of the gate cap insulating film of the semiconductor substrate. Bonding the second buried insulating film, the gate cap insulating film, and the planar protective film of the second semiconductor substrate having the second buried insulating film; and exposing the first buried insulating film to the surface of the first buried insulating film. And polishing the substrate, and forming a source / drain region in the surface of the exposed epitaxial layer.

Referring to the drawings, a semiconductor device and a method for manufacturing the same will be described below.

FIG. 3 is a plan view showing a semiconductor device of the present invention, FIG. 4A is a cross-sectional view showing the II-I cross section of FIG. 3, FIG. 4B is a cross-sectional view showing the II-II cross section of FIG. 3, and FIGS. It is a process sectional drawing which shows the manufacturing method of a device.

In the semiconductor device of the present invention, as shown in FIGS. 3, 4A, and 4B, an embedded oxide film 31a is formed in the semiconductor substrate 30a, and the gate cap nitride film 35 is in contact with the embedded oxide film 31a. A gate electrode 34 and a gate oxide film 33 are stacked on the gate cap nitride film 35. A sidewall spacer 37 is formed on side surfaces of the gate electrode 34 and the gate cap nitride layer 35, and a P-type semiconductor layer 32 used as a channel region is formed on the gate oxide layer 32. have. The epi layer 40 is formed on the side surface of the P-type semiconductor layer 32 so as to contact the P-type semiconductor layer 32 in the region where the device operates, and the epi layer 40 is in the region where the device does not operate. It is formed so as not to contact this P-type semiconductor layer 32.

In addition, another buried oxide film 31 is formed flat between the epi layer 30 and both sides thereof.

A planar passivation layer 41 is formed between the gate cap nitride layer 35, the gate electrode 34, the sidewall spacer 37, the gate oxide layer 33, the buried oxide layer 31a, and another buried oxide layer 31. It is. The source / drain regions 43 are formed in the epi layer 40 not in contact with the P-type semiconductor layer 32.

The method of manufacturing the semiconductor device of the present invention configured as described above is shown on the P-type semiconductor layer 32 of the semiconductor substrate 30 having the buried oxide film 31 and the P-type semiconductor layer 32 as shown in FIG. 5A. In the thermal oxidation process, the gate oxide film 33 is formed to have a thickness of about 30 to 100 kPa. At this time, the thickness of the buried oxide film 31 is about 1000 to 4000 GPa and the P-type semiconductor layer 32 is about 500 to 2000 GPa. And depositing a doped polysilicon layer on the oxide layer to have a thickness of 1000 to 3000Å, depositing a nitride layer and an oxide layer on the polysilicon layer in turn, and then using the gate forming mask to form the oxide layer, nitride layer, and polysilicon layer. Anisotropic etching is performed by stacking the gate electrode 34, the gate cap nitride film 35, and the first oxide film 36. In this case, the gate cap nitride layer 35 may be formed of a good etching selector for the P-type semiconductor layer 32 and the first oxide layer 36.

As shown in FIG. 5B, the second oxide film is deposited on the semiconductor substrate 30 at about 2000 to 3000 microns, and then the second oxide film is anisotropically etched to form the gate electrode 34, the gate cap nitride film 35, and the first oxide film 36. A side wall spacer 37 is formed on the side. At this time, the gate oxide layer 33 is also etched.

A thin interlayer oxide film 38 is formed on the P-type semiconductor layer 39 exposed by the thermal oxidation process as shown in FIG. 5C, and the gate cap nitride film 35 and the cap oxide film 36 are formed on the semiconductor substrate 30. And a semiconductor layer 39 having good etching selectivity is deposited. After that, the planarization process is performed by etch back or chemical mechanical polishing (CMP).

As shown in FIG. 5D, the cap oxide layer 36, the sidewall spacers 37, and the gate oxide layer 33 are selectively removed to form a small amount of sidewall spacers 37 on the sides of the gate cap nitride layer 35 and the gate electrode 34. ) Is formed.

As shown in FIG. 5E, the semiconductor layer 39 and the P-type semiconductor layer 32 exposed using the gate electrode 34 and the sidewall spacers 37 as an mask are anisotropically etched to bury the interlayer oxide film 38 and buried therein. The oxide film 31 is exposed.

As shown in FIG. 5F, the exposed portions of the interlayer oxide film 38 and the buried oxide film 31 composed of oxide films are anisotropically etched to expose the semiconductor substrate 30 and the P-type semiconductor layer 32.

As shown in FIG. 5G, the P-type semiconductor layer 32 is etched to completely expose the buried oxide film 31, and the semiconductor substrate 30 is anisotropically etched to form holes having a predetermined depth in the semiconductor substrate 30. Form.

As shown in FIG. 5H, the same height is filled to fill the hole formed in the semiconductor substrate 30 exposed by selective epitaxy growth and to contact the P-type semiconductor layer 32 formed under the gate electrode 34. The P-type epi layer 40 is formed to have. At this time, epitaxy growth is grown using a chemical solution of SiH ₂ Cl ₂ (DCS), HCl, H ₂ . The epitaxial layer 40 in the region to be separated from the P-type semiconductor layer 32 is etched to isolate the devices.

As shown in FIG. 5I, a low pressure chemical vapor deposition (LPCVD) or a silicon on glass (SOG) is deposited on the semiconductor substrate 30, and then a gate cap nitride layer is formed by etch back or chemical mechanical polishing (CMP). The planarization protective film 41 is formed by planarizing so as to remain to 35.

As shown in Fig. 5J, the semiconductor device fabricated as described above is bonded to an SOI substrate, which is a semiconductor substrate 30a provided with a buried oxide film 31a. The conditions at the time of joining advance at the temperature of 800-950 degreeC, or advance at normal temperature.

As shown in FIG. 5K, after polishing the semiconductor substrate 30 so that the buried oxide film 31 remains, an n-type high concentration impurity ion is exposed on the epitaxial layer 40. Ions are implanted to have a concentration of 2.0 x e ^{15 to} 5.0 x e ¹⁵ / cm 2 with energy of 30 to 60 KeV to form source / drain regions 43.

The semiconductor device of the present invention and the manufacturing method thereof as described above have the following effects.

First, parasitic capacitance is small because the gate electrode and the source / drain region overlap each other.

Second, in the SOI substrate having a thin channel structure, the thickness of the source / drain regions is thick, thereby preventing an increase in resistance of the source / drain regions.

Third, since the source / drain regions are formed of an Elfp bait structure, the short channel effect can be improved, and the generation of electron pairs is reduced by reducing the drain field at the corner of the drain region, thereby reducing the floating body effect. do.

Fourth, since the gate oxide film is formed on the surface free of etching damage, the reliability of the device is improved.

Fifth, since the channel and the gate electrode are aligned in one photo process, the process is simplified.

Claims (8)

A first investment insulating film formed on a semiconductor substrate, A gate cap nitride film in contact with the first investment insulating film, A gate electrode, a gate insulating film, and a semiconductor layer formed by stacking the gate cap nitride film; Sidewall spacers formed on side surfaces of the gate electrode and the gate cap nitride film, An epitaxial layer formed in contact with both sides of the semiconductor layer, A second buried insulating film formed on both sides of the epitaxial layer and between the epitaxial layer and having a thickness thinner than the epitaxial layer A flat protective film formed between the first investment insulating film and the second investment insulating film, And a source / drain region formed in the surface of the epi layer. The semiconductor device according to claim 1, wherein the source / drain regions are insulated from other active regions by the second investment insulating layer. The semiconductor device according to claim 1, wherein the gate electrode and the source / drain regions are formed in a row without overlapping. In a first semiconductor substrate comprising the first buried insulating film and the first semiconductor layer, Forming a gate oxide film, a gate electrode, and a gate cap insulating film and a cap insulating film to be stacked; Forming sidewall spacers on side surfaces of the gate oxide film, the gate electrode, the gate cap insulating film, and the cap insulating film; Forming an interlayer oxide film and a second semiconductor layer on the exposed first semiconductor layers on both sides of the sidewall spacers; Removing the cap insulating layer using the second semiconductor layer and the gate electrode as a mask and anisotropically etching the sidewall spacers to expose the first semiconductor layers on both sides of the sidewall spacers; Forming trenches in the first semiconductor substrate on both sides of the sidewall spacer using the gate electrode as a mask; Forming an epitaxial layer in the trench of the first semiconductor substrate so as to be in contact with the first semiconductor layer formed below the gate electrode; Forming a planar protective film up to a height of the gate cap insulating film of the semiconductor substrate; Bonding a second investment insulating film of the second semiconductor substrate having a second investment insulating film, the gate cap insulating film, and the planar protective film; Polishing the first semiconductor substrate until the surface of the first investment insulating film is exposed; Forming a source / drain region in the surface of the exposed epitaxial layer. The method of manufacturing a semiconductor device according to claim 4, wherein the first and second buried insulating films are formed of an oxide film. The method of claim 4, wherein the gate cap insulating film is formed of a nitride film. The method of claim 4, wherein the cap insulating film is formed of an oxide film. The method of claim 4, wherein the sidewall spacer is formed of an oxide film.

Images