KR100255551B1 - A method and an apparatus for enabling a processor to access an external component through a private bus or a shared bus - Google Patents

Abstract

Methods and apparatus are disclosed that enable processor 156 to access external components 158a-n via dedicated bus 146 or shared bus 148. One embodiment of the invention is an external memory access device that includes an external memory access unit 144. This external memory access unit 144 is connected to the processor 156 via an external memory access unit bus 142. The external memory access unit 144 is also connected to the external memories 158a-n via the dedicated bus 146. The external memory access unit 144 is also connected to the external memory 158a-n via a shared bus 148, which is one of the external components, ie 150, 152 or 154. Is connected to the external memories 158a-n.

Description

A METHOD AND AN APPARATUS FOR ENABLING A PROCESSOR TO ACCESS AN EXTERNAL COMPONENT THROUGH A PRIVATE BUS OR A SHARED BUS}

Recently, as the number of processors (eg, digital signal processors using RISC type structures) increases, the instruction execution speed of the processor is increased by simplifying or eliminating the microcode of the processor. For example, one way to increase the instruction execution speed of the processor by this simplification / removal is to decode instruction and reduce execution time. Indeed, many processors currently using RISC type architectures can decode and execute one instruction word in only one clock cycle.

In order to take advantage of this reduced instruction decoding and execution time, and to further increase the processor's instruction execution speed, there is a need for a method of reducing the data access time (ie, the time required to provide a processor required data word to the processor). Do. In addition, the method of reducing data access time has long been used in digital signal processing applications which require a digital signal processor to receive the maximum amount of multimedia data in real time.

Figure 1 shows one conventional data access method. As shown in this figure, this conventional method reduces data access time by disposing an internal data memory bank 100 within the processor 102. The arithmetic logic unit (i.e., ALU) 104 can then access the data word in several clock cycles by supplying the address of the particular memory cell (which stores the data word) to the internal data memory bank. The internal data memory bank also decodes these addresses and provides the ALU with the required data words (at the supplied addresses) by driving the appropriate bit lines and sense amplifiers. However, since the space of the processor die is limited, and because the memory cell array occupies a relatively large die space, only a limited amount of data can be stored therein, and thus the ALU under this conventional data access method. The amount of data that can be accessed is limited. Thus, this conventional data access method does not sufficiently reduce the data access time, since this method allows the ALU to access only a limited amount of data. In addition, this conventional internal data access method does not provide the shortest data access time, because sometimes the ALU 104 must terminate its data access to allow other components to access the data memory. to be.

As such, since the conventional internal data storage method does not sufficiently reduce the data access time, various conventional external data access methods have been developed. 2 shows an example of a conventional external data access method. As shown in this figure, this conventional method stores data in a surplus memory of the program memory. However, this conventional data access method also does not sufficiently reduce the data access time, since one instruction bus 110 is used to exchange instructions and data with the processor 112. In particular, this conventional method requires three full clock cycles to access the data word, where (1) during the first clock cycle, the processor 112 receives the instruction word and (2) the second clock. During the cycle, the processor 112 decodes the instruction, and (3) during the third clock cycle, the processor 112 generates a data address and reads the data. In addition, this conventional method also does not sufficiently reduce data access time, which requires that the processor 112 often terminate its data access to allow other components of the computer to use the command bus to access the data memory. Because. For example, sometimes the processor must terminate its data access to allow external system memory to store additional information in the data memory.

3 shows a second conventional method of accessing external data. This conventional method uses a separate instruction bus 120 and data bus 122 to connect the processor 124 to separate instruction memory 126 and data memory 128, respectively. However, for various reasons, this conventional external data access method also does not provide the shortest data access time. First, this conventional external data access method does not provide the shortest data access time, which means (1) making a separate data request for each individual data word on the data memory cell array 128 side, and ( 2) This is because the processor requests the processor to wait until the data memory cell array supplies the requested data. Secondly, access time is adversely affected because in order to communicate with the data memory 128, the processor 124 must drive a large capacitive data bus due to the number of components connected to it. .

Third, the conventional external memory access method of FIG. 3 does not sufficiently reduce the access time, which is sometimes the processor itself to allow other components of the computer to use the data bus to access the data memory. This is because the data access must be terminated. For example, the processor must sometimes terminate its data access to allow external system memory to access the data memory. This conventional data access method reduces the data access time by reducing the number of times that an external system memory must terminate its data access in order to allow additional data to be stored in the data memory bank 128. Increase the size of the array. However, this conventional solution is not seen as an optimal solution, because the size of the data memory cell increases the cost of the computer system. Also, this conventional solution cannot be used when the size of the data memory cell array cannot be increased due to design constraints and space limitations.

TECHNICAL FIELD The present invention relates to the field of computer systems, and more particularly, to a method and apparatus for enabling a processor to access external components via a dedicated bus or a shared bus.

1 illustrates one conventional data access method that reduces data access time by storing data therein.

Figure 2 illustrates one conventional external data access method for storing data in redundant memory of a program memory.

3 illustrates another conventional external data access method for storing data in an external data memory.

4 illustrates a computer system structure including one embodiment of an external memory access device of the present invention.

FIG. 5 illustrates one embodiment of an external memory access unit bus, an external memory access unit, a dedicated bus, and a shared bus used in the external memory access device of FIG.

FIG. 6 illustrates one embodiment of a dedicated and shared bus interface used in the external memory access unit of FIG. 5; FIG.

7 illustrates one embodiment of a timing diagram for a block read access operation of the shared and dedicated bus interface of FIG.

8 illustrates one embodiment of a timing diagram for a block write access operation of the shared and dedicated bus interface of FIG.

9 illustrates one embodiment of a state machine block used in the external memory access unit of FIG.

10 illustrates one embodiment of a state diagram for a dedicated bus state machine of the state machine block of FIG.

11 is a timing diagram for operation of one embodiment of a state machine output generator of the state machine block of FIG. 9 during a block read access over a dedicated bus.

12 is a timing diagram for operation of one embodiment of a state machine output generator of the state machine block of FIG. 9 during a block write access via a dedicated bus.

FIG. 13 is a timing diagram for operation of one embodiment of a state machine output generator of the state machine block of FIG. 9 during a read after write access via a dedicated bus. FIG.

14 illustrates one embodiment of a state diagram for the shared bus state machine of the state machine block of FIG.

FIG. 15 is a timing diagram for operation of one embodiment of a state machine output generator unit of the state machine block of FIG. 9 during a block read access over a shared bus. FIG.

FIG. 16 is a timing diagram for operation of one embodiment of a state machine output generator unit of the state machine block of FIG. 9 during a block write access via the shared bus. FIG.

FIG. 17 is a timing diagram of the operation of one embodiment of a state machine output generator unit of the state machine block of FIG. 9 during a read after a write access via the shared bus.

18 is a timing diagram of the operation of one embodiment of the state machine output generator unit of the state machine block of FIG. 9 during a write access through the shared bus when the shared bus grant signal is removed and the processor is not locking its shared bus.

Detailed description of the invention

In the following, numerous details are set forth in order to provide a thorough understanding of the present invention. However, of course, these specific details are not required by those skilled in the art in practicing the present invention. For example, for purposes of explanation, the following description includes methods and apparatus for accessing external data memory, but the present invention is directed to a processor skilled in the art to access any external memory (eg, instruction memory) or any other component. Of course it can be used by. In other instances, well-known electrical structures and circuits are shown in block diagram form in order not to obscure the present invention by unnecessary details.

Summary of the Invention

The present invention provides a method and apparatus that allows a processor to access external components via a dedicated bus or shared bus. One embodiment of the present invention is an external memory access device including an external memory access unit. This external memory access unit is connected to the processor via an external memory access unit bus. The external memory access unit is also connected to an external memory via a dedicated bus. The external memory access unit is also connected to an external memory via a shared bus, which also connects external components to the external memory.

The objects and advantages of the present invention will become more readily apparent to those skilled in the art after reviewing the following detailed description and the accompanying drawings.

1. External memory access device

The present invention provides a method and apparatus that allows a processor to access external components via a dedicated bus or shared bus. 4 shows a computer system structure including one embodiment of an external component access device of the present invention. In the embodiment of the present invention described in FIG. 4, the external component access device is an external memory access device that allows the processor 156 to access the N data memory banks 158. However, the external component access device of the present invention allows the processor to access any number of other external memory banks (eg, N instruction memory banks) or any number of other external components.

As shown in FIG. 4, the external memory access device 140 includes an external memory access unit bus 142, an external memory access unit (EMAU) 144, a dedicated bus 146, a shared bus 148, and a shared bus. Bus arbiter 15, direct memory access unit 152, data memory bank controller 154, and N data memory banks 158. Processor 156 uses external memory access device 140 to minimize its data access time. In particular, processor 156 is a conventional processor with limited internal data storage capacity and limited addressing capability for accessing data. In one embodiment of the present invention, the processor 156 is a digital signal processor (DSP) having a RISC type structure, whereby the DSP can decode and execute an instruction word in only one clock cycle. Thus, to take advantage of this reduced instruction decode and execution time, and to further increase the instruction execution speed of the DSP, the DSP 156 uses an external memory access device 140 to minimize its data access time. . Also, program instructions are stored externally in program RAM 160 and data words are stored externally in data memory bank 158. The processor 156 uses the program bus 162 to access the program RAM 160 and the external memory access device 140 to access the N data memory banks 158.

The processor 156 also uses the EMAU bus 142, the EMAU 144, and the shared bus 148 to access a number of external components connected to the shared bus 148. Some examples of these external components connected to the shared bus include an external processor, external system memory, or an external serial port, where the port is shared with other external components not connected to the shared bus. Send and receive information from external components connected to the bus. In addition, in the embodiment of the present invention shown in FIG. 4, the processor 156 may share a shared bus arbiter 150, a data memory controller, via an EMAU bus 142, an EMAU 144, and a shared bus 148. 154, and a direct memory access unit (DMA) 152. Shared bus arbiter 150 determines whether another bus master is accessing the shared bus, and if so, the particular bus master being accessed has a higher priority than the bus master requesting access to the shared bus. Assigning control of the shared bus between multiple bus masters (e.g., EMAU 144 and DMA 152) by determining if there is.

Many well known bus arbiters may be used as the shared bus arbiter 150. For example, one embodiment of shared bus arbiter 150 is a system arbitration logic unit used in a computer system architecture using a PCI bus. Some of these bus arbiters are connected to their respective bus masters through separate request lines and separate grant lines. Another bus arbiter is connected to all bus masters through a common request line and a common grant line by time multiplexing the access times of each bus master to their respective lines. Another arbitrator may also use a common request line and a common grant line for access to all bus masters, but which bus master is making a request on the request line and which bus master has shared bus access on that grant line. A decoder is used for the arbiter and bus master (rather than using time multiplexing techniques) to determine if it is approved.

Regardless of how shared bus arbiter 150 is connected to the bus master via the request line and the grant line, in one embodiment of the present invention, the arbiter operates in the following manner. In order to gain access to the shared bus, the bus master must bring the signal on its request line to a first logical state (eg, a "1" logic level). If arbiter 150 wishes to grant access to the shared bus and to the request bus master, the arbiter sends a signal on the grant line to the second logical state of the bus master (eg, "1"). Should be made. If the arbiter later wishes to terminate a particular access to the shared bus, the arbiter must bring the signal on the grant line side of the accessing bus master into a third logical state (eg, "0"), thus The accessing bus master may terminate access to the shared bus and bring the signal on its request line to a fourth logical state (eg, “0”) in the next clock cycle.

Thus, prior to initiating communication over the shared bus, processor 156 initiates communication with shared bus arbiter 150 to obtain permission to drive the shared bus. In particular, to gain access to the shared bus, processor 156 requires the EMAU to initiate external access over the shared bus. At this time, the EMAU 144 puts the signal on the request line side into a first logical state, and the arbitrator sets the signal on the grant line side (indicating that the arbitrator has granted access to the shared bus, i. Wait until the second logical state. The access of the EMAU to the shared bus may be terminated by the arbiter if the arbiter brings the signal on the grant line side of the EMAU to a third logical state, whereby the EMAU may terminate access to the shared bus. And the signal on the demand line side can be brought to the fourth logic state in the next clock cycle. However, as described below, the processor refuses to bring the signal on the request line side to the fourth logic state in response to the arbiter bringing the signal on the grant line side to a third logic state, thereby providing the shared bus with the shared bus. The EMAU can be programmed to refuse to terminate access to it (ie, the EMAU can be programmed to lock the shared bus).

Processor 156 also communicates with data memory bank controller 154 via EMAU bus 142, EMAU 144, and shared bus 148. Through the activation of a certain number of control lines (not shown in FIG. 4) connecting the data memory bank controller 154 to the N data banks 158, the data memory bank controller is configured to route the data memory bank to a specific bus. (Ie, allow the data memory bank to receive information from the shared bus or dedicated bus). The bus master accesses data memory bank controller 154 through the shared bus to request controller 154 to assign a particular data memory bank to a particular bus. When the data memory bank controller determines that a particular bus master has access to a particular data bank, the controller transmits a control signal through a control line connected to the data bank. The data bank then decodes the control signal to determine if they should be accessed and if information should be received from the shared bus or dedicated bus. After informing the request data bank that it is to be accessed via the shared bus or the dedicated bus, the data bank memory controller sends a grant signal to the bus master side on the shared bus side. Upon receipt of a grant signal for accessing a particular data bank, the requesting bus master initiates data access to the request data bank via the shared bus or dedicated bus.

In the case of the embodiment of the present invention shown in FIG. 4, EMAU 144 is the only bus master that can access a data memory bank via the dedicated bus or shared bus. In other words, the only bus master that can access a particular data memory bank through the dedicated bus is EMAU 144. This embodiment of the invention reduces the data access time of the processor 156 by preventing the processor from interrupting data access caused by other components accessing a particular data bank. It just makes the data bank accessible. In particular, since the processor 156 does not terminate data access to allow other components of the computer system to access the data bank, the data access time of the processor is minimized. Rather, the processor 156 may access a particular data bank through the dedicated bus, such that other components may access another data bank through the shared bus. In addition, this embodiment of the present invention only allows the EMAU to access the data bank through the dedicated bus in order to reduce the data access time of the processor 156 by not overloading the dedicated bus.

In the case of the embodiment of the present invention shown in FIG. 4, the processor 156 also communicates with the direct memory access unit (DMA) 152 to direct the EMAU bus 142, the EMAU 144, and the shared bus 148. use. The direct memory access unit 152 connects a number of external components (eg, external system memory not shown in FIG. 4) to the data bank side via a dedicated bus 148. In addition, these external components can access a particular data bank through the shared bus connection when EMAU 144 is not accessing via dedicated bus 146. The processor 156 also communicates with the DMA 152 to program the DMA so that external components can access the data bank that the processor wishes to access. For example, when the processor finishes accessing a data bank, it may wish to review the contents of that data bank by external components. Thus, the processor directly accesses the memory access unit (via an external memory access unit and a shared bus) and programs the unit to provide the contents of the data bank to the external component.

As previously mentioned, to minimize the data access time, processor 156 accesses N data memory banks 158 to EMAU bus 142, EMAU 144, and dedicated bus 146 or Use shared bus 148. In other words, the external memory access device of the present invention allows the processor to have a short data access time. For example, when processor 156 accesses data memory bank 158 via dedicated bus 146, the external memory access device 140 may initiate a write operation at the X + Y clock cycle, and When a read operation is initiated, the X + Y + Z clock cycle allows access to the X location of the data memory, where (1) X represents the number of locations accessed in the data memory, and (2) Y is the (3) Z represents the number of clock cycles required to prefetch data during the read operation. In the case of the embodiment of the present invention shown in FIG. 4, the programming clock cycle Y is two and the prefetch clock cycle Z is two. In addition, if the processor 156 uses a shared bus to access a particular data memory bank, then the external memory access device 140 may perform an X + Y + W clock cycle when the processor starts a write operation, and a read operation may be performed. When started, at X + Y + Z + W clock cycles, access the Y position of the data memory, where W represents the number of clock cycles the EMAU waits until an arbitrator grants access to the shared bus. .

As also described below, the processor 156 first programs the EMAU during the initial programming phase when it wishes to initiate external access via a dedicated or shared bus. For example, during the initial programming phase, the processor 156 informs EMAU of the start address of an external component that the EMAU wishes to access via the shared bus or dedicated bus. During the initial programming phase, processor 156 also informs the EMAU whether it needs to initiate a block external access operation or a single external access operation. If processor 156 requires an out-of-block access operation, the processor also informs the EMAU of the block size, step size, and specific block mode access method (ie, incremental or decremented access method). give. In addition, the processor 156 must determine whether the EMAU should deny access release in response to the removal of the grant signal of the arbitrator after initiating access through the shared bus (ie, the EMAU must lock the shared bus). The EMAU. If the external access required by the processor 156 to initiate the EMAU 144 is an external data access, then the programmed information also tells the EMAU whether to access the data bank via a dedicated bus or shared bus. After the EMAU is programmed, the processor provides an external read or write command (e.g., a read command or a write command directed to one of the external data registers of EMAU 144) by way of the processor and the external through the EMAU. Initiate communication between components.

2. External memory access unit bus

For one embodiment of the present invention, FIG. 5 shows a more detailed view of the EMAU bus 142, EMAU 144, dedicated bus 146, and shared bus 148 of FIG. 1. As shown in this figure, the EMAU bus includes an external data bus line 180, an external input / output access bus line 182, an EMAU register bus line 184, a read / write bus line 186, and a stop. Processor bus line 188 is included.

In the case of the embodiment of the present invention shown in FIG. 5, the external data bus line 180 is a 16 bit line used to transfer a 16 bit data word between the processor 156 and the EMAU 144. In addition, the external input / output access bus line 182 is a 1-bit line, where the processor 156 uses this line to supply an external input / output access signal to the external memory access unit side. This external input / output access signal also informs the external memory access unit whether the processor wishes to initiate an external input / output access, whereby the external memory access unit sends any other signal that the processor transmits on the EMAU bus. Can be reviewed.

EMAU register bus 184 is a 2-bit line bus, where the processor uses this bus to communicate with a specific register of the EMAU. In other words, processor 156 uses EMAU register bus 184 to command communication with a particular EMAU register. The EMAU bus also includes a read / write bus line 186 that the processor uses to inform the EMAU that the external access includes a read operation (ie an input operation) or a write operation (ie an output operation). do.

Finally, the EMAU bus includes a stop processor bus line 188, which is used by the EMAU to stop the operation of the processor 156. For example, in the case of an embodiment of a processor 156 that does not have a standby machine, the EMAU sends a stop processor clock signal to the clock gate circuitry side of the processor to stop the operation of the processor. use. On the other hand, in the case of an embodiment of the processor 156 that does not have a standby machine, the EMAU 144 sends a standby signal to the standby machine side to enable the standby machine to idle the processor. The EMAU includes two clock cycles when (1) the clock module 202 sends a stop request signal to the EMAU to power down the processor and the EMAU, or (2) during the initial prefetch phase of a read operation. The processor sends a stop processor clock signal or wait signal to the processor when it is necessary to stop the processor.

For the purpose of illustration, FIG. 5 illustrates a specific number of bit lines of the EMAU bus 142. However, in another embodiment of the present invention, the EMAU bus has a different width. For example, for illustrative purposes, Figure 5 shows a 16-bit line external data bus that carries a 16-bit data word, but in the case of another embodiment of the invention the external data bus 180 may have a different width and different bits. A data word with a size can be transferred. Thus, one embodiment of the EMAU 144 receives an 8-bit data word and uses a sign extension technique to transfer this 16-bit data word to the processor 156 side.

3. Dedicated bus and shared bus

For one embodiment of the present invention, Figure 5 also shows a more detailed view of the dedicated and shared buses of the present invention. As shown in this figure, each of these buses includes a read bus line 206 and a write bus line 208. These read bus lines and write bus lines are provided in a dedicated bus and a shared bus to inform external components that the processor is accessing via the EMAU that the processor wants to perform a read or write operation. Used. In addition, the dedicated bus and shared bus have a 16-bit line address bus 210, which uses this address bus 210 to transmit the address of an externally accessed component. Finally, these two buses have a 16 bit line bidirectional data bus 212, which is used to carry data signals between the processor 156 and the externally accessed component. Although a specific width of the dedicated bus and the shared bus is shown in FIG. 5 for explanation, of course, in other embodiments of the present invention, these buses may have different widths.

4. External memory access unit

Figure 5 also shows one embodiment of the external memory access unit of the present invention. As shown in this figure, the external memory access unit includes an EMAU clock generator 192, a shared and dedicated bus interface 190, and a state machine block 194. The EMAU clock generator receives clock signals from the system clock module 202, augments these clock signals, and sends these enhanced signals to the state machine block 194 side and to the shared and dedicated bus interface 190 side. to provide.

As shown in FIG. 5, state machine block 194 grants the shared bus acknowledgment from arbiter 150 to determine when processor 156 can access the shared bus via an external memory access unit. Receive signal and shared bus request signal. Also, as previously mentioned, state machine block 194 receives a stop request signal (on the stop request line 200 side) from the system clock module 202 so that the processor and the EMAU can be powered down. . In addition, as described below, the state machine block 194 may include an external I / O access bus 182, an EMAU register bus 184, and a read / write bus 186 to determine when external access may be initiated. ), The EMAU control bus 204, and the signal on the shared bus grant line side. Upon determining that external access can be initiated, state machine block 194 can initiate external data access in response to an external read or write command from the processor (via EMAU control bus 204). The enable signal is transmitted to the shared and dedicated bus interface 190. In other words, the state machine block 194 can generate an enable signal that controls the operation of the shared and dedicated bus interface 190 (and thus control the operation of the EMAU 144), the processor 156. Monitors the signals sent to the shared and dedicated bus interface 190 side.

Shared and dedicated bus interface 190 includes a number of registers programmed by processor 156 during the initial programming phase. Processor 156 controls the programming of the registers of shared and dedicated bus interface 190 via control signals sent along external I / O access 182, EMAU register 184, and read / write bus 186. do. In addition, via external data bus 180, processor 156 sends programming signals to specific registers of shared and dedicated bus interface 190. The shared and dedicated bus interface 190 also uses an external data bus 180 to communicate information with the processor 156 and with external components (eg, external data memory banks 158). Finally, shared and dedicated bus interface 190 uses EMAU control bus 204 to send and receive control signals to and from state machine block 194.

5. Shared and dedicated bus interface

FIG. 6 shows a more detailed view of one embodiment of the shared and dedicated bus interface 190 of the EMAU 144 of FIG. 5. As shown in this figure, shared and dedicated bus interface 190 includes bus interface control unit 220, external access control register (EACR) 222, external read address unit (ERAU) 224, external write address. Unit (EWAU) 230, external data read register (EDRR) 226, and external data write register (EDWR) 228. The control unit 220 is connected to the processor 156 via an external data bus 180, an external I / O access bus 182, an EMAU register bus 184, and a read / write bus 186. The control unit 220 is a decoder that controls communication between the processor 156 and external registers of the shared and dedicated bus interface 190. For example, the control unit 220 may be configured such that any signal on the EMAU bus 142 side is shared and dedicated bus interface until the processor directs the initiation of external access via the external I / O access bus line 182. It does not reach the register of 190). When an external access signal is detected on the external I / O access bus 182, the control unit 220 determines the register with which the processor wishes to communicate by examining the signal on the EMAU register bus 184 side. As mentioned previously, in one embodiment of the present invention, the EMAU register bus has two bit lines. Thus, for this embodiment of the present invention, Table 1 describes the decoding logic used by the control unit 220 to determine the external register (of the bus interface 190) with which the processor 156 communicates.

Bit value of the second bit line of the EMAU register bus Bit value of the first bit line of the EMAU register bus External register of the bus interface being accessed 0 0 External access control register (222) 0 One External read address unit (224) One 0 External record address unit 230 One One External Data Register (226a / 228)

Once the control unit 220 has determined which external register of the shared and dedicated bus interface it wishes to communicate with, it enables the required external register and displays the rest of the external register of the bus interface 190. Enable it. At this time, the control unit 220 sends a signal on the external data bus 180 and a read / write bus 186 side to the requested register side to initiate communication between the requested register and the processor.

In addition, as shown in FIG. 6, the control unit 220 receives a clock signal on the clock bus 198 side. The control unit 220 uses the clock signal for its operation and sends it to the external register side of the shared and dedicated bus interface (via the bus interface control bus 232). As shown in FIG. 6, the control unit 220 also receives a signal from the state machine block 194 along the EMAU control bus 204. As shown in this figure, the control line that state machine block 194 uses to communicate with the shared and dedicated bus interface 190 allows the processor 156 to initiate communication with an external address unit 224 or 230. And a counter enable line which the control unit uses to transmit a counter enable signal to the external address unit 224 side.

The control lines that state machine block 194 uses to communicate with shared and dedicated bus interfaces 190 also include shared and dedicated bus read and write enable lines. The signals on these lines are sent by the control unit along the bus interface control bus 232 and the enable bus 234 to the external memory interface unit 238. Based on these shared and dedicated bus read and write enable signals, external memory interface unit 238 is responsible for whether the shared bus or dedicated bus is required for external access, and if so, external access may perform a read or write operation. Determine if it is included.

Thus, if an external memory interface unit determines that the dedicated bus is required for external readout, the external memory interface unit 238 puts all the bus lines on the shared bus into a tri-state, and write bus lines of the dedicated bus. Deactivate and activate the address bus, data bus, and read bus lines of the dedicated bus. On the other hand, if the processor requires the dedicated bus for external writing, external memory interface unit 238 puts all the bus lines on the shared bus into three states, deactivates the read bus lines of the dedicated bus, and dedicates them. Activates the address bus, data bus, and write bus lines of the bus. However, if processor 156 requested an external read along the shared bus, external memory interface unit 238 deactivates all the bus lines on the dedicated bus, deactivates the write bus lines of the shared bus, and Activate the shared bus's address bus, data bus, and read bus lines. Finally, if the processor requires an external read along the shared bus, external memory interface unit 238 deactivates all bus lines on the dedicated bus, deactivates write bus lines on the shared bus, and shares Activates the bus address bus, address bus, and write bus lines.

a. External access control register

As mentioned previously, to initiate external data access, processor 156 initially programs EMAU 144 during the initial programming phase. In the case of the embodiment of the shared and dedicated bus interface 190 shown in FIG. 6, the programming operation is as follows. During the first cycle of the two cycle initial programming phase, the processor 156 programs the external access control register 222. Processor 156 initiates the programming of external access register 222 by first instructing an external input or output access on the external I / O access line 182 side. Processor 156 also sends a "0" on the EMAU register bus to inform control unit 220 that it wants to communicate with external access control register 222. At this time, the processor 156 provides the EACR 222 by providing a write signal to the read / write bus 186 side and transmitting the first control word to the shared and dedicated bus interface 190 side through the external data bus 180. Program the first control word. Table 2 describes an example of the first control word.

First control word Number of bits Bit function One Loop size bits 2 Loop size bits 3 Loop size bits 4 Loop size bits 5 Loop size bits 6 Loop size bits 7 Loop size bits 8 Loop size bits 9 Increment Bits 10 Decrement Bits 11 Step size bits 12 Lock shared bus bit 13 reservation 14 reservation 15 reservation 16 reservation

The ninth and tenth bits of the first control word indicate whether the processor is planning to initiate a single access operation or a block access operation. If a block access operation is needed, these ninth and tenth bits also indicate whether the processor desires incremental or decremented block mode operation. Table 3 describes one method by which the ninth and tenth bits are used to indicate the mode of access operation.

Bit value of Decrement (10th) bit Bit value of increment (ninth) bit Type of access action 0 0 Single access behavior 0 One Automatic Increment Block Access Behavior One 0 Automatic Decrement Block Access Behavior One One Single access behavior

At this time, the EACR 222 informs the address counter unit 244 or 247 (of the ERAU 224 or the EWAU 230) of the type of access operation requested by the processor 156. If the processor 156 requires some kind of block mode access operation (i.e., auto increment or automatic decrement block mode access operation), the first 8 bits of the first control word (i.e. loop size bits) ) Determines the size of the accessed block (ie loop size). These first 8 bits allow the processor to select any block size from 1 to 256. The external access control register 222 provides the block size to the address counter unit 244 or 247 side.

Processor 156 also uses the eleventh bit of the first control word to program the access mode. In particular, when processor 156 requests block mode access, the eleventh bit informs the EMAU that the step size of the increment or decrement is one or two. This ability of the present invention to allow the processor to program step size 2 is advantageous for DSP applications, where the processor is a real number when real and imaginary data elements are stored in the data memory as adjacent data words. This allows you to access only data or imaginary data. The external access control register 222 also informs the address counter 224 or 247 of this step size.

The twelfth bit of the first control word determines whether an EMAU will lock the shared bus. In particular, if this shared bus lock bit is set (ie has a value of "1"), then the 16th bit of the second control word (hereinafter referred to as EMAU) should initiate data transfer over the shared bus. As mentioned in the following, if processor 156 is instructing this word by ERAU 224 or EWAU 230), then the EMAU will share the request after the request has been approved by arbiter 150. The bus is locked. Thus, if the EMAU accesses the shared bus after the processor 156 requests the data transfer to lock the shared bus, the EMAU will not make the shared bus request signal low even after the arbitrator has removed the shared bus grant signal. (If the shared bus request signal goes low, the arbiter grants access to the shared bus to another bus master). After locking the shared bus, the EMAU does not automatically unlock the shared bus after the processor terminates access through the shared bus. In particular, in order for the EMAU to unlock the shared bus, the processor 156 must reprogram the external access control register (i.e., the processor 156 must clear the twelfth bit (a value of " 0 "). Other control words) must be recorded in the EACR 222). This ability of the processor to remain locked to the shared bus is useful during read correction write operations. Finally, if this shared bus lock bit is not set (ie does not have a value of "0"), the shared bus is not locked, and the EMAU indicates that the arbitrator will lower the signal on the grant line side. After the state, the access to the shared bus is abandoned.

In addition, the processor 156 indicates that it wishes to communicate with the external access control unit 222 by (1) providing an active signal on the external I / O access line 182 (2). External access by sending a " 0 " signal on the EMAU register bus 184 to instruct the 220 side, and (3) providing a read operation signal on the read / write bus line 186. The first control word stored in the control register 222 may be read. In response to this signal, the EACR 222 provides a programmed first control word on the bus interface control bus 232, where the word provides the information to the control unit 220 and the external data bus 180. Through the processor 156 to pass through.

b. External address unit

In the last clock cycle of the initial programming phase of two clock cycles, the processor 156 programs one of the external address units. During this clock cycle, the processor 156 maintains an active signal on the external input / output access line 182 and indicates that it wants to communicate with one of the external address units 224 or 230. Transmits a "1" or "10" signal on the EMAU register bus. In the case where the external read operation is to be initiated, the processor 156 programs the external read address unit 224 and in the case where the external write operation is to be initiated, the external write address unit 230 is programmed. In order not to obscure the description of the present invention by unnecessary description, the programming of the external read address unit is described below. However, the description below can of course also be applied to the programming of the external write address unit.

After selecting the ERAU 224, the processor 156 sends a 16-bit second control word to the external address unit via the external data bus 180 and writes a write operation signal on the read / write bus line 186. By providing an external read address unit 224 to record the signal. The sixteenth bit of the second control word is used to indicate that the EMAU should initiate a read operation over a shared bus or dedicated bus. This sixteenth bit is stored in the second address register 246 of the ERAU 224. The ERAU supplies the sixteenth bit to the state machine 224 side, which generates an enable signal that later selects a bus to use when the EMAU should initiate external access. In the case of the embodiment of the present invention illustrated in FIG. 6, if the value of the sixteenth bit is "1", the EMAU can access an external component through a shared bus, and the value of the sixteenth bit is " 0 ", the EMAU can initiate external data access via the dedicated bus.

Bits 1 through 15 of the second control word are used by the processor to indicate the address of an external component that is connected to a shared bus or a dedicated bus. During an external data access, bits 1 to 15 of the second control word are either (1) the address of the requested data word when the EMAU performs a single access operation, or (2) when the EMAU performs a block access operation. Indicates the initial address of the requested block of data words. The ninth to fifteenth bits of the second control word are stored in the second address register 246 of the external read address unit 224. The seven bits, together with the original lower 8 bits, define an external register location (e.g., a memory location in one of the N data banks 158).

The lower 8 bits of the second control word are supplied to the address counter unit 244 of the ERAU 224. In addition, when the state machine block 190 supplies the active counter enable signal to the address counter unit 244, the address counter unit may control these lower eight bits and the control signal supplied by the EACR 222 (i.e., step size). , Loop size, and decrement / increment mode signal) to generate up to 256 external partial addresses. In other words, if processor 156 requires block mode access, address counter unit 244 counts up by one or two starting from the initial eight bits received (ie, bits 1 through 8 of the second control word). Or count down to generate up to 256 external partial addresses.

As shown in FIG. 6, the address counter unit 244 also receives a counter enable signal (from the state machine block 194 via the bus interface control unit 220 and the bus interface control bus 232), Correspondingly, the counter is activated or deactivated. The operation of the external read address unit 224 during the first two clock cycles in which the counter unit 224 receives the active counter enable signal will now be described. During the high phase of the first clock cycle, the second address register 246 stores bits 9 through 16 of the second control word, and the first address register 245 stores bits 1 through 8 of the second control word. . During the low phase of the first clock cycle, the first address register 245 supplies the first eight bits of the second control word to the second address register 246, where this register 246 is the lower one. Combine the eight bits with bits 9-16 to produce a complete first external address. Store this complete first external address. Also during this row phase, the counter 244 generates a first 8-bit partial address. During the high phase of the second clock cycle, the counter 244 supplies the first partial address to the first address register 245, and the second address register 246 supplies the first external address to the address output bus 236. Send along). During the low phase of the second clock cycle, the address counter 244 generates a second 8-bit partial address, and the second address register 246 receives the first partial address from the first address register 245. Combine the first partial address with bits 9 to 16 of the second control word to generate a complete second external address, and store this complete second external address.

In addition, the processor 156 (1) provides an active signal on the external I / O access line 182 to (2) instruct the control unit 220 that it wants to communicate with the ERAU 244. The current address stored in the address register of the ERAU 224 by transmitting a " 1 " signal on the EMAU register bus 184, and (3) providing a read operation on the read / write bus line 186. Or note that the second control word can be read. In response to these signals, the ERAU 224 provides the contents of the second address register 246 on the control bus 232, which registers the information with the control unit 220 and the external data bus 180. The processor 156 transmits the data to the processor 156.

c. External data register

After the initial two clock cycle programming phase, processor 156 initiates an external input (ie, read) or output (ie, write) operation. Processor 156 uses an external data read register (ie, EDRR) 226 during a read operation, and an external data write register (ie, EDWR) 228 during a write operation. By using this register data access method, the data access time of the processor 156 is reduced.

In particular, as mentioned above, in the case where the processor 156 accesses the data memory bank 158 via the dedicated bus 146, the external memory access device 140 may execute an X + Y clock when a write operation is performed. In the cycle, and in the X + Y + Z clock cycle when a read operation is performed, allows the processor to access the X position of the data memory, where (1) X is the accessed position of the data memory. (2) Y represents the number of clock cycles required to program the EMAU, and (3) Z represents the number of clock cycles required to prefetch data during a read operation. As mentioned above, for one embodiment of the present invention, the programming clock cycle Y is two and the prefetch clock cycle Z is two. On the other hand, when the processor 156 uses the shared bus 148 to access a particular data memory bank, the external memory access device 140 performs the read operation in the X + Y + W clock cycle and when the write operation is performed. At the X + Y + Z + W clock cycle, allowing the processor to access the X position of the data memory, where W is the EMAU until the arbitrator grants access to the shared bus. Indicates the number of clock cycles that are waited for.

Operation of the shared bus and dedicated bus interface 190 during the read operation will now be described with reference to FIG. 7, which shows a block read access mode executed along the dedicated bus. The following description is similarly applicable to block read access executed along a shared bus, except that during the shared bus read operation, there is a delay of W clock cycles until the arbitrator accepts the EMAU's shared bus request. Do.

The state machine block 194 may include an external I / O bus 182, an EMAU register bus 184, and to determine when the processor 156 requires an external read operation from the second external data read register 226a. Read / write bus 186 is included. When the request is detected (represented by an external I / O access signal, a read signal, and an EMAU register signal that selects an external data register 226a or 228), to suspend or idle the processor for two clock cycles. The state machine block 194 activates a processor stop signal supplied to the processor 156, whereby the EMAU 144 may prefetch two data words and store the data words in an external data register.

In particular, during the first clock cycle when state machine block 194 detects that processor 156 requires an external read from second EDRR 226a, state machine block 194 causes processor to execute external data register 226a or 228. Activate the counter enable signal as long as is accessed. Also, during the low phase in this first clock cycle, state machine block 194 provides (1) a processor stop signal on stop processor line 188, and maintains this signal for two clock cycles (i.e., Holding the signal until state machine block 194 detects an external read and then goes to a low phase of a third clock cycle), (2) activates a dedicated bus read enable signal bus and sends this signal to the processor. Stops communication with the EDRR 226a until it is 1/2 clock cycle.

The second clock cycle is a first prefetch cycle, during which the ERAU 224 transmits a first external address to the external memory interface unit 238 along the address output bus 236. The interface unit 238 transmits the first external address along the address bus 210p, which is a dedicated bus. In addition, during the second clock cycle, the shared bus and dedicated bus interface 190 activate a dedicated bus readout signal (on the read line 206p of the dedicated bus), and the active signal is processed by the processor with the EDRR 226a. After the communication ends, it is maintained until one clock cycle. Finally, during the second clock cycle, the first EDRR 226b begins storing data retrieved from the particular first data location.

The third clock cycle is a second prefetch cycle during which (1) the ERAU 224 transmits a second external address along the address output bus 236 and the address bus 210p, and (2) the second clock cycle. The first external data read register 226b ends the storing of the first data word retrieved from the first address location and begins storing the second data retrieved from the second data location, and (3) the second EDRR 226a is stored in the first data word. Store the first data word stored in the 1EDRR 226b, (4) the state machine block 194 deactivates the stop processor signal (ie, pulls down to ground), and (5) the processor 156 Start receiving data stored in the second external data read register 226a.

As shown in FIG. 7, the EMAU operation during the fourth, fifth and sixth clock cycles is the same. During this three clock cycle, (1) the state machine block 194 supplies an active read enable signal and a counter enable signal to the shared bus and dedicated bus interface 190 side, and (2) the ERAU 224 is disabled. Sends third, fourth and fifth external addresses along address bus 236 and address bus 210p, and (3) the first EDRR 226b terminates storing the second data word from the second address location. And store the retrieved third and fourth data words from the third and fourth data locations, and store the retrieved fifth data words from the fifth data location, and (4) the second EDRR 226a may be stored. Store the second, third and fourth data words stored in the 1EDRR 224b, and (5) the processor 156 searches for the first, second and third data words stored in the second EDRR 226a. End and start to retrieve the fourth data word stored in the second EDRR 226a.

During the seventh clock cycle, (1) the state machine block 194 deactivates the dedicated bus read enable signal and the counter enable signal, and (2) the ERAU 224 is the address output bus 236 and the address bus ( 6 external addresses along 210p), (3) the first EDRR 226b terminates storing the fifth data word from the fifth address location, and stops storing the sixth data word retrieved from the sixth data location. (4) the second EDRR 226a stores the fifth data word stored in the first EDRR 224b, and (5) the processor 156 stores the fourth data word stored in the second EDRR 226a. Terminate search. Thus, by the end of the eighth clock cycle (after the state machine block 194 detects that the processor 156 is accessing the external data register 226a), the EMAU 144 processes the fourth data word by the processor. 156 and prefetch two additional data words (ie, data words 5 and 6) and store them in external data read register 226.

During the signal access read operation, the shared bus and dedicated bus interface 190 operations may include: (1) during the signal access read operation, the dedicated address bus transmits only three addresses (during the second, third and fourth clock cycles), (2) the first EDRR 226b latches only three data words (during the second, third, fourth and fifth clock cycles), and (3) the second EDRR 226a (the third and fourth clocks). During the cycle), only two data words are latched, and (4) the processor 156 reads only one data word along the external data bus 180 (during the third and fourth clock cycles). Is very similar to the block read operation described above. In addition, during the signal access read operation, the counter 244 generates the same partial address three times, so that the dedicated bus address bus 210p transmits the same address three times, and the external data read register 226a outputs the same data word. Store three times, and external data read register 226b stores the same data word twice.

On the other hand, if the processor 156 supplies a write signal on the read / write bus line 186, and supplies an external I / O access signal and an EMAU register signal that selects the external data register 226a or 228, the bus interface. 190 allows processor 156 to initiate an output (ie, write) operation via external data write register 223. In particular, as mentioned earlier, when the sixteenth bit of the second control word directs external access via a dedicated bus, external memory access device 14 causes processor 156 to perform an external write operation in an X + Y clock cycle. Where (1) X represents the number of locations accessed in the data memory, and (2) Y represents the number of clock cycles required to program the EMAU. In addition, when the sixteenth bit of the second control word indicates an external write operation for a specific data memory bank through a dedicated bus, the external memory access device 140 causes the processor to perform the operation in an X + Y + W clock cycle. Where W represents the number of clock cycles the EMAU waits until an arbitrator grants access to the shared bus.

The operation of the shared bus and dedicated bus interface 190 during the write operation will now be described with reference to FIG. 8, which shows a block write access operation performed along the dedicated bus. The description below is equally applicable to block write access executed along the shared bus, except that in the case of shared bus writes there is a delay of W clock cycles until the arbitrator accepts the EMAU's shared bus request. have.

State machine block 194 reads external I / O bus 182, EMAU register bus 184, and reads to determine when processor 156 requires an external write operation from external data write register 228. / Record bus 186 is included. Upon detection of the request (represented by an external I / O access signal, a write signal, or an EMAU register signal that selects an external data register 226a or 228), the state machine block 194 causes the processor to send an external data write register. As long as 228 is accessed, the counter enable signal is activated. In addition, during the low phase of the first clock cycle in which the state machine block 194 detects an external write, the state machine block 194 activates a dedicated bus write enable signal, and the processor transmits the active signal to the EDWR ( After the communication with 228 is finished, it is maintained until 1/2 clock cycle is reached. During the second clock cycle when processor 156 accesses EDWR 228, (1) EWAU 230 sends a first external address along address output bus 236 and dedicated bus address bus 210p, (2) The external memory interface unit 238 activates the dedicated bus write bus 208p and keeps this active signal until one clock cycle after the processor terminates communication with the EDWR 228, ( 3) The EDWR 228 transfers the first data word along the dedicated bus data bus 212p to the addressed data bank side. As shown in FIG. 8, the operation of the shared bus and dedicated bus interface 190 during the third clock cycle is the same as the operation during the second clock cycle.

During the fourth clock cycle, (1) the state machine block 194 deactivates the dedicated bus write enable signal and the counter enable signal, and (2) the EWAU 230 sends an address output bus 236 and an address bus ( Transmit a third external address along 210p, (3) external memory interface unit 238 maintains an active dedicated bus write signal, and (4) EDWR 228 along dedicated bus data bus 212p; Send a third data word to the addressed data location. Thus, as illustrated in FIG. 8, the external memory access device 140 of the present invention allows the processor 156 to partially complete a write operation in an X + Y clock cycle, where X is the data. Represents the number of locations accessed in memory (ie, three data locations accessed in FIG. 8), and Y represents the number of clock cycles required to program the EMAU (ie, as shown in FIG. 8, EDRR and EWAU). Two clock cycles required for programming).

6. State machine block

9 illustrates one embodiment of a state machine block 194. The function of this block is to (1) monitor the signal that the processor sends to the shared bus and dedicated bus interface side via the external I / O access bus 182, EMAU register bus 184, and read / write bus 186. (2) monitor the acknowledgment signal supplied by the shared bus arbiter 150, and (3) generate a shared bus and dedicated bus enable signal, a counter enable signal, and a stop processor signal, the signals being Controls the operation of the shared bus and dedicated bus interface during external input / output operations. In addition, as mentioned previously, the state machine block 194 is also connected to the clock module 202 to allow the state machine to generate a stop processor signal and an EMAU clock signal by receiving a stop request signal.

As shown in FIG. 8, the state machine block 194 includes a state machine control unit 250, a shared bus state machine 252, a dedicated bus state machine 254, a state machine control bus 256, and a state machine. An output generating unit 258 is included. The control unit 250 sends clock signals on the clock bus 198 to the state machines 252 and 254 and the output generating unit 258. The control unit 250 is a decoder, which is a signal on the EMAU bus 142 until the processor 156 directs external input / output access (on the external I / O access bus 182). Prevents reaching 252,254 and output generator unit 258 side. Once processor 156 initiates an external input / output access, state machine control unit 250 causes ERAU 224 or EWAU 230 to supply the 16th bit of the second control word to the state machine side. waiting. As mentioned above, the sixteenth bit informs the state machine block 194 whether the processor 156 wishes to initiate external access via a dedicated bus or shared bus. At this time, the control unit 250 waits for the processor 156 to instruct a read or write operation toward the external data register 226a or 228 (on the EMAU register bus 184). Upon receipt of this instruction, control unit 250 (1) enables one of the state machines 252 or 254 and disables the other machine based on the value of the sixteenth bit of the second control word. And (2) enable the state machine output generator unit 258.

After the control unit 250 enables a particular state machine, the control unit 250 may be configured to include an external I / O access bus 182, an EMAU register bus 184, a read / write bus 186, a stop request line ( 200, and a signal appearing on the block mode line of the EMAU control bus 204 is sent to the state machine side. In addition, when the control unit 250 enables the shared bus state machine 252, the control unit 250 not only sends the aforementioned signal to the state machine side, but also shares (shown on the control bus 204). A bus lock signal and a shared bus grant signal are sent to the state machine side.

These inputs of the state machine cause various state transitions of the state machine. In the case of the embodiment of the state machine block 194 shown in FIG. 9, the state machines 252 and 254 transition from state to state at the rising edge of the clock. In other words, each state machine examines its input signal to determine if there is a need for a state transition at the rising edge of the clock cycle. In addition, when the state machine is enabled, the state machine generates three digit control codes (b2, b1, b0) related to its current particular state, and sends this three bit state code to the state machine output generator 258 side. Supply. The state machine output generator 258 also controls signals appearing on the read / write bus 186, the EMAU register bus 184, the EMAU control bus 204, the stop request bus 200, and the clock bus 198. Receive via bus 256. These signals, along with the three bit state codes, then drive state machine output generator 258 to generate a bus enable signal, a counter enable signal, a stop clock signal, and a shared bus request signal.

a. Dedicated Bus State Machine

If processor 156 indicates (via the 16th bit of the second control word) that it wishes to initiate external access via dedicated bus 146 and indicates that it wishes to access external data register 226a or 228, State machine control unit 250 enables dedicated bus state machine 254 and disables shared bus state machine 252.

The operation of the dedicated bus state machine 254 will now be described with reference to FIGS. 10-13. 10 shows a state diagram of one embodiment of the dedicated bus state machine 254 of FIG. FIG. 11 shows a timing diagram for the operation of one embodiment of the state machine output generator 258 of the state machine block 194 of FIG. 9 during a block read access via a dedicated bus. 12 shows a timing diagram for the operation of one embodiment of state machine output generator 258 of state machine block 194 over a dedicated bus. FIG. 13 shows a timing diagram for the operation of one embodiment of the state machine output generator 258 of the state machine block 194 of FIG. 9 during a read after write access via the dedicated bus.

As shown in FIG. 10, the operation of the dedicated bus state machine 254 is defined by the values of three signals, which are (1) a dedicated bus access enable signal and (2) an invalid signal. Reading of the data of the 2EDRR 226a (ie, EDRR2), and (3) a stop request signal. The dedicated bus access enable signal is a dedicated bus state machine enable signal generated by state machine control unit 250. In particular, state machine control unit 250 allows processor 156 to perform external read or write operations via external data registers 226a or 228 and via dedicated bus 146 (external input / output access bus 182, Generate an active dedicated bus enable signal when instructed via the EMAU register bus 184, the read / write bus 186, and the sixteenth bit of the second control word.

In addition, the input notification logic circuit of the dedicated bus state machine 254 generates an active read of data in the second EDRR 226a, which is an invalid signal when the processor initiates a single access read operation. The input notification logic circuit detects that the block mode signal is inactive and initiates a single access read operation when the processor requires an external read of the EDRR 226a. In addition, the input notification logic circuitry of the dedicated bus state machine 254 may cause the data of the second EDRR 226a to be invalid when the processor instructs the EMAU to start an initial prefetch read of a block read operation. Generates an active read. If the input notification logic circuit detects a request from the processor 156 to read the EDRR 226a after the processor writes a second control word to the ERAU 224, the input notification logic circuit causes the processor to read the block. Detects that the EMAU has been instructed to start an initial read of the operation.

On the other hand, if processor 156 requests a write operation (i.e., is initiating communication with external data write register 228), then the input notification logic circuit is not valid (i.e., this signal is " 0 " Has an value) and maintains an inactive read of the data of the second EDRR 226. If the processor 156 resumes block read access after interrupting an initial block read access during an intermediate access, the input notification logic circuitry will also maintain an inactive read of the data of the second EDRR 226a, which is an invalid signal. .

As also shown in FIG. 10, the dedicated bus state machine 254 remains in idle state A (ie, cycles) as long as the stop request signal and the dedicated bus access enable signal are in an inactive state. However, after processor 156 initiates external access to access the current external data register 226a or 228 (i.e., generates an active P bus access enable signal), the dedicated bus state machine 254 enters a state. (C) or transition to state (F).

For example, a transition from state A to state C of the dedicated bus state machine 254 (which occurs when the processor 156 requires an initial read of a single access read or block read operation from the second EDDR 226a). This will now be described with reference to FIGS. 10, 11 and 13. As shown in these figures, if the processor 156 requests an initial block read from the second EDDR 226a and the dedicated bus state machine 254 is in the idle state A, the output generator 258 will not be able to process the processor. As long as 156 is accessing external data registers 226a or 228, the counter enable signal is active. Also, during the low phase of this initial clock cycle, the output generator 258 provides a stop processor signal on the stop processor clock line 188 and maintains this signal for two clock cycles, (2) enabling a dedicated bus. The read signal is activated and held until the processor 156 is 1/2 clock cycle after the processor 156 terminates communication with the second EDRR 226a.

On the rising edge of the next clock cycle, the dedicated bus state machine 254 detects whether the reading of the data of the dedicated bus access enable signal and the EDRR2 invalid signal is active, and thus from the state A to the first prefetch state (C). Transitions to). During the clock cycle in which the dedicated bus state machine 254 is maintaining the first prefetch state C, the output generator 258 causes the bus interface 190 to store the first data word in the first EDRR 226b. Maintain a dedicated bus read enable signal to begin. In the next clock cycle, the dedicated bus state machine 254 deactivates the stop processor signal to cause the output generator 258 to allow the processor 156 to begin receiving data stored in the second EDRR 226a. A transition is made to the second prefetch state E during the clock cycle.

In the next clock cycle, the dedicated bus state machine 254 transitions to the access state (F). In this state, the processor is running, and state machine 254 is responsible for determining whether the processor is currently requesting another external read / write operation via external data register 226a or 228. 182 monitors signals on EMAU register bus 184 and read / write bus 186. If the current processor instruction is not an external access instruction via an external data register 226a or 228 (ie, the dedicated bus access enable signal is not active), then the dedicated bus state machine transitions to an idle state (A). For example, if the current processor instruction is program ERAU 224 or EWAU 230, then the dedicated bus state machine transitions from state F to state A, which means that the processor is no longer EDRR 226a or EDWR ( 228), the dedicated bus access enable signal is deactivated.

On the other hand, if the current instruction is another access instruction (ie, another read access instruction) to the second external data register 226a, the dedicated bus state machine 254 maintains state F and performs read access. 10 and 13, if the current command is an access (i.e., a write access) to the external data write register 228, then the dedicated bus state machine 254 maintains state F. And a write operation is performed based on the address of the EWAU 230. Finally, if the read of the data of the dedicated bus access enable signal and the EDRR2 invalid signal is active (e.g., before the processor 156 prefetches any data word but after programming the ERAU 224, the read operation is interrupted in advance). After requesting an external read, state machine 254 transitions from state (F) to state (C).

Direct transition of dedicated bus state machine 254 from state A to state F in one clock cycle (processor 156 requires an external write to EDWR 228 and state machine 254 enters state A ), Or what happens when the processor 156 resumes block read access after interrupting a previous block read access, will now be described with reference to FIGS. 10, 12, and 13. As shown in these figures, state machine 254 is in an idle state in state A where processor 156 has requested an external write to EDWR 228, and output generator 258 indicates that the processor has external data. As long as the registers 226a or 228 are accessed, the counter enable signal is active. In addition, during the low phase of this initial clock cycle, the output generator 258 activates the enable write signal, and this signal becomes 1/2 clock cycle after the processor terminates communication with the EDWR 228. Keep up.

In the next clock cycle, the dedicated bus state machine 254 determines whether the dedicated bus access enable signal is active (ie, has a value of "1") and whether the reading of the data of the EDRR2 invalid signal is inactive ( That is, it has a value of "0"), and accordingly a transition to the active state F is performed. In this state, state machine 254 is configured to determine whether the processor is currently requesting another external read or write operation via external data register 226a or 228, to the external input / output access bus 182, EMAU register bus. 184, and signals on input / output bus 186. If the current processor instruction is not an external access instruction via an external data register 226a or 228 (ie, the dedicated bus access enable signal is not active), then the dedicated bus state machine transitions to an idle state (A). On the other hand, if the current command is another access command to the external data write register 228 (i.e. another write operation), the dedicated bus state machine 254 maintains state F and the enable signal (i.e. And a counter enable signal and a dedicated bus write enable signal), thereby allowing the bus interface 190 to perform a write operation.

10 and 13, if the current command is another access command for the second external data read register 226a (i.e., read access), then the dedicated bus state machine 254 may As long as the processor accesses external data registers 226a or 228, it will still maintain an active counter enable signal. However, during the low phase of the clock cycle of the current instruction, the output generator 258 deactivates the dedicated bus enable write signal, activates the enable read signal of the dedicated bus, and the processor communicates with the second EDRR 226a. This signal is held until after 1/2 clock cycles. At this time, the EMAU initiates a read operation based on the address of the ERAU 224 in the next clock cycle. In this way, the external access device of the present invention can transition from a write operation to a read operation in only one clock cycle unless the processor loads a new address into the ERAU 224.

In the above description regarding the state transition of the state machine 254, it is assumed that the stop request signal is inactive (ie, has a value of "0"). If the stop request signal is active and the state machine 254 is in the idle state A or the access state F, the state machine 254 transitions to the stop state H at the rising edge of the next clock cycle. . State transition 254 holds state H until the clock module removes the stop request signal prior to transition to state G or C in the next clock cycle. If the stop request signal is inactive and the processor 156 requests an internal access read from the second EDRR 226a (i.e., reading of the data of the P bus access enable signal and the EDRR2 invalid signal is active and the stop request is active). If the signal is inactive), state machine 254 transitions to state (C).

On the other hand, if processor 156 does not require an initial external read from second EDRR 226a, state machine 254 transitions from state H to state G during the next clock cycle. From state G (which is the state of the starting processor after an overall stop state), state machine 254 transitions to idle state A or access state F. In particular, state machine 254 transitions from state G to state F when the dedicated bus enable signal is active and reading of data in EDRR 226a is inactive. State machine 254, on the other hand, transitions from state G to state A if the dedicated bus enable signal is inactive.

The operation of the dedicated bus state machine 254 after the processor interrupts external access is now described. The processor must interrupt the external block read operation, but if it later resumes this operation, the processor must first store the address of the data contained in the second external data read register 226a. During an interrupt, if the processor is using an external data read register for another read operation, the processor reads the stored address of the original data of the EDRR 226a before resuming the original block read operation. You need to reprogram it. On the other hand, during an interrupt, the processor can resume the original block read operation by simply accessing the EDRR 226a again without further programming of the ERAU 224.

On the other hand, if the processor must interrupt the external block write operation in the intermediate access in order to resume the external block write operation later, the processor must first store the address stored in the EWAU 230. After the interrupt, the processor should reload the stored original value of EWAU back to the address unit side if it performs another external write operation during the interrupt. On the other hand, if the processor does not perform another write operation during the interrupt, after this interrupt, the processor may simply resume its block write access by accessing the EDWR 228.

Finally, note that the dedicated bus state machine 254 is designed in such a way that the processor 156 can repeatedly perform the same single access read operation without the delay caused by two prefetch cycles. In particular, whenever processor 156 requires a single access read operation by deactivating a block mode signal, the processor must wait for three clock cycles before receiving the requested data word. The delay remains unchanged even when the processor requires the same data word to be supplied to it in the next clock cycle, which means that whenever the processor requires a single read operation by deactivating a block mode signal, the processor This is because the dedicated bus state machine 254 transitions from the state A to the prefetch state C and E side. However, the processor may also access the same data word repeatedly by instructing a block read operation with one loop size (ie, perform the same single read operation repeatedly). Accordingly, the processor may access EDRR 226a to obtain a data word after one two clock cycle prefetch step and only one two clock cycle prefetch step.

b. Shared bus state machine

The processor 156 indicates (via the 16th bit of the second control word) that it wishes to initiate external access via the shared bus 148 and accesses the external data register 226a or 228 (the EMAU). On the register bus), the state machine block control unit 250 enables the shared and dedicated bus interface 190 state machine 252 and disables the dedicated bus state machine 254.

The operation of the shared bus state machine 252 is now described with reference to FIGS. 14-18. 14 shows a state diagram of one embodiment of the shared bus state machine 252 of FIG. 15 shows a timing diagram for the operation of one embodiment of the state machine output generator 258 of the state machine block 194 of FIG. 9 during a block read access over the shared bus. 16 shows a timing diagram for the operation of one embodiment of state machine output generator 258 of state machine block 194 over a shared bus. FIG. 17 shows a timing diagram for the operation of one embodiment of the state machine output generator 258 of the state machine block 194 of FIG. 9 during a read after a write access via the shared bus. 18 illustrates the operation of one embodiment of the state machine output generator 258 of the state machine block 194 of FIG. 9 during a read after write access via the shared bus when the shared bus grant signal is not locking the shared bus. The timing diagram is presented.

As shown in Figure 14, the operation of shared bus state machine 252 is defined by the values of five signals, which are (1) the shared bus access enable signal, and (2) the invalid signal. Reading of the data of the 2EDRR 226a, and (3) the stop request signal, (4) the shared bus grant signal, and (5) the lock shared bus signal. The shared bus access enable signal is a dedicated bus state machine enable signal generated by state machine control unit 250. In particular, control unit 250 allows processor 156 to perform external read or write operations via external data registers 226a or 228 and via shared bus 148 (external input / output access bus 182, EMAU registers). Generate an active access enable signal when directed via a bus 184, a read / write bus 186, and a signal of the sixteenth bit of the second control word.

In addition, the input notification logic circuit of the shared bus state machine 252 generates an active read of data in the second EDRR 226a, which is an invalid signal when the processor initiates a single access read operation. The input notification logic circuit detects that the block mode signal is inactive and initiates a single access read operation when the processor requires an external read of the EDRR 226a. In addition, the input notification logic circuit of the shared bus state machine 252 is responsible for the data of the second EDRR 226a which is an invalid signal when the processor instructs the EMAU to start an initial prefetch read of the block read operation. Generates an active read. If the input notification logic circuit detects a request from the processor 156 to read the EDRR 226a after the processor writes a second control word to the ERAU 224, the input notification logic circuit causes the processor to read the block. Detect instructing the EMAU to begin an initial read of the operation.

On the other hand, if processor 156 requests a write operation (i.e., is initiating communication with external data write register 228), then the input notification logic circuit is not valid (i.e., this signal is " 0 " Has an value) and maintains an inactive read of the data of the second EDRR 226. If the processor 156 resumes block read access after interrupting an initial block read access during an intermediate access, the input notification logic circuitry will also maintain an inactive read of the data of the second EDRR 226a, which is an invalid signal. .

As also shown in FIG. 14, shared bus state machine 252 remains in isle state A (ie, cycles) as long as the stop request signal and the dedicated bus access enable signal are in an inactive state. . However, after detecting that processor 156 has initiated an external access and is currently accessing an external data register 226a or 228 (ie, after generating an active P bus access enable signal), output generator 258. ) Stops the processor clock. In particular, if output generator 258 detects that processor 156 requested an initial external access and is currently accessing external data register 226a or 228 and shared bus state machine 252 is idle (A), Output generator 258 activates a stop processor signal on stop processor line 188 during the low phase of the initial sense clock cycle.

On the rising edge of the next clock cycle, the shared bus state machine 252 transitions to the request state B and activates the shared bus request signal (which feeds the arbiter 150 side to obtain permission for the shared bus). . At this point, the shared bus state machine remains in this state until the arbiter 150 grants access to the shared bus, that is, access to the EMAU. After the arbiter accepts the EMAU's shared bus request (that is, after the shared bus state machine 252 receives the active shared bus grant signal), the shared bus state machine 252 enters the state (for another full clock cycle). Keep b). During this last clock cycle of state B, output generator 258 activates the counter enable signal. On the rising edge of the clock cycle after this final state (B) clock cycle, state machine 252 is based on the value of the reading of the data of the invalid signal of second EDRR 226a (C) or state (D). Transitions to).

For example, now transition from state B to state C of shared state machine 252 (which occurs when processor 156 requires an initial read of a single access read or block read operation from second EDDR 226a). This will be described with reference to FIGS. 14, 15, and 17. As shown in these figures, if processor 156 requires an initial block read from second EDDR 226a, (1) output generator 258 reads shared bus during the low phase of the final state (B) clock cycle. Activate the enable signal, and (2) the shared bus state machine 252 goes from the request state B to the first prefetch state C at the rising edge of the clock cycle after the last state B clock cycle. Transition. During the clock cycle in which the high bus state machine 252 is maintaining the first prefetch state C, the output generator 258 begins to allow the bus interface 190 to store the first data word in the first EDRR 226b. The shared bus read enable signal is maintained.

On the rising edge of the next clock cycle, the shared bus state machine during the clock cycle in which the output generator 258 deactivated the stop processor signal so that the processor 156 can begin receiving data stored in the second EDRR 126a. 252 transitions to the second prefetch state (E). During the next clock cycle, shared bus state machine 252 moves to access state (F). In this state, the processor is running, and state machine 252 is configured to determine whether the processor is currently requesting another external read / write operation via external data register 226a or 228. 182, the signals of the EMAU register bus 184, and the read / write bus 186. If the current processor instruction is not an external access instruction via an external data register 226a or 228 (ie, the dedicated bus access enable signal is not active), the shared bus state machine transitions to an idle state (A). For example, if the current processor instruction is program ERAU 224 or EWAU 230, then the shared bus state machine transitions from state F to state A, which means that the processor is no longer EDRR 226a or EDWR ( 228), the shared bus access enable signal is deactivated.

On the other hand, if the current command is another access (ie, another read access) command to the second external data register 226a, the shared bus state machine 252 maintains state F and performs read access. Also, as shown in Figures 14 and 17, if the current command is an access (i.e., write access) command to the external data write register 228, then the dedicated bus state machine 254 will return state (F). It maintains and performs a write operation based on the address of the EWAU 230.

(When processor 156 requires an external write to EDWR 228 and state machine 254 is in state A or when processor 156 resumes block read access after interrupting a previous block read access. The transition of the shared bus state machine 252 from state B) to state D) is now described with reference to FIGS. 14, 16, and 17. As shown in these figures, if the processor 156 requires an external write to the EDWR 228 (while the state machine 254 is idle in state A), the shared bus state machine 252 The transition from the required state B to the start state D is made at the rising edge of the clock cycle after the final state B clock cycle. During the low phase of the clock cycle while the shared bus state machine 252 is maintaining a start state D, the output generator 258 activates (1) the shared bus write enable signal and communicates with the processor EDWR 228. The signal is kept active until 1/2 clock cycles after the termination, and (2) the processor clock is started by deactivating the stop processor signal. Also, during the clock cycle in which the shared bus state machine 252 maintains the start state D, the output generator 258 deactivates the counter enable signal.

In the next clock cycle, shared bus state machine 252 transitions to state F, output generator 258 reactivates the counter enable signal until the processor stops communicating with EDWR 228. Keep this signal active.

In this state, the state machine 252 is configured to determine whether the processor is currently requesting another external read or write operation via the external data register 226a or 228, to the external input / output access bus 182, EMAU register. Signals on bus 184 and input / output bus 186 are monitored. If the current processor instruction is not an external access instruction through an external data register 226a or 228 (ie, the dedicated bus access enable signal is not an active state instruction), the dedicated bus state machine transitions to an idle state (A). . On the other hand, if the current instruction is another access instruction to the external data write register 228 (i.e. another write operation instruction), then the shared bus state machine 252 maintains state F and the enable signal (i.e. And a counter enable signal and a shared bus write enable signal), so that the bus interface 190 can perform a write operation.

14 and 17, if the current instruction is a second external data read register 226a (i.e., a read access), shared bus state machine 252 may cause the processor to send an external data register. As long as 226a or 228 is accessed, the active counter enable signal is still maintained. However, during the low phase during the clock cycle of the current instruction, the output generator 258 deactivates the dedicated bus enable write signal, while the enable read signal of the dedicated bus is active, and the processor is enabled for the second EDRR 226a. It maintains this signal until it is 1/2 clock cycle after it has finished communicating with it. At this time, the EMAU initiates a read operation based on the address of the ERAU 224 in the next clock cycle. In this way, the external access device of the present invention can transition from a write operation to a read operation in only one clock cycle unless the processor loads a new address into the ERAU 224.

The operation of shared bus state machine 252 when the processor interrupts a block operation is similar to the operation of dedicated bus state machine 254 during such an interrupt. Further, in the above description of state transition of state machine 252, it is assumed that (1) the stop request signal is inactive, and (2) the arbiter does not remove the grant signal for the EMAU during external access. . Since these two assumptions are not always correct, a description of the operation of state machine 252 is only necessary if the stop request signal is active or if the arbiter removes the grant signal during external access. If the stop request signal is active and the state machine 252 is in an idle state (A) or an access state (F), the state machine 252 transitions to a stop state (H) on the rising edge of the next clock cycle. do. State transition 252 holds state H until the clock module removes the stop request signal prior to transition to state G or B in the next clock cycle. When the stop request signal becomes inactive and the shared bus access enable signal is active, state machine 252 transitions to state B. On the other hand, if the shared bus access enable signal is active, state machine 252 transitions from state H to state G when the stop request signal is removed. From state G, state machine 252 transitions to idle state A at the rising edge of the next clock cycle.

18 shows a timing diagram for the operation of one embodiment of an output generator 258 during the write access in which the shared grant signal was removed and the processor did not lock the shared bus. As shown in this figure, if the arbitrator removes its shared bus grant signal and the shared bus state machine is in access state F and the processor 156 is requesting external access, then the shared bus state machine 252 is Stops the processor clock, pulls down the shared bus request low, transitions to the idle state (A), and requests state (B). Once the arbitrator returns to the shared bus grant signal of the EMAU, the shared bus state machine transitions from state B to state C or D based on the aforementioned criteria.

When the shared bus 148 is locked (i.e., the 12th bit of the first control word and the 16th bit of the second control word are set), and the EMAU starts sharing bus access, the shared bus state machine 252 Rejecting the shared bus acknowledgment does not pull down the request low (ie, shared verb state machine 252 remains in state F or transitions to state C and then to state E). The shared bus state machine 252 only pulls down the request low when the processor clears the twelfth bit, thus, by bringing the state machine 252 to state F and by locking the shared bus, the processor ( 156 is a multiplexed external read operation (1) without obtaining the permission of the arbiter, or (2) an external read operation without obtaining the permission of the arbiter (this operation from state (F) to state (C) in FIG. Shown as a transition).

Accordingly, the external memory access device 140 of the present invention reduces the data access time of the processor for several reasons as follows. First, by separating the program memory and the data memory, the data access time of the processor 156 does not affect the communication between the processor 156 and the program memory 160. Secondly, since a data word is prefetched for the processor during a read operation, the processor does not need to wait for the data memory bank to supply a data word, but rather while decoding and executing the previous data word. The EMAU can be made to prefetch the next data word. Third, the access time is reduced because the EMAU must not drive a high capacitive bus to access the data memory bank. Fourth, the data access time is also minimized, which does not need to terminate the data access so that other components of the computer system can access the data bank, but rather access the data bank through the dedicated bus. As such, other components may access other data banks via the shared bus.

Finally, the external memory access device of the present invention allows the processor to access a particular data bank through a dedicated bus and DMA 152 to refresh other memory banks through the shared bus. This is advantageous because very little memory capacity is required.

Claims (18)

An external component access device for allowing a processor to access a first external component, the device comprising: (a) an external component access unit; (b) an external component access unit bus connecting the external component access unit to the processor; (c) a bidirectional dedicated bus connecting the external component access unit to the first external component; And (d) a bidirectional shared bus connecting the external component access unit to the first external component and connecting a second external component to the first external component; Wherein the processor instructs the external component access unit to access the first external component along one of the dedicated bus and the shared bus, and to the dedicated bus to access the first external component. Has only access to And wherein said second external component is denied access to said first external component when said processor is accessing said first external component. 2. The system of claim 1, wherein the external component access unit follows one of the dedicated bus and the shared bus when the processor requests the external component access unit to perform an external write operation to the first external component. Transmits data to the first external component, the external component access unit requesting the external component access unit to perform an external read from the first external component when the dedicated bus and the shared bus And receive data from the first external component according to one of the following. 2. The apparatus of claim 1, further comprising a shared bus arbiter connected to the shared bus, wherein the shared bus arbiter assigns control of the shared bus among a plurality of bus masters connected to the shared bus, wherein the external component And an access unit and said second external component are bus masters. 4. The shared bus arbiter of claim 3, wherein before the shared bus arbiter assigns control of the shared bus to a bus master that requires access to the shared bus, the shared bus arbiter determines if another bus master is accessing the shared bus. If so, the request bus master determines whether the request bus master has a higher priority state than the accessing bus master, and if the request bus master has a higher priority state than the accessing bus master, the shared bus arbiter determines that the access bus master External component access device, characterized in that to terminate the access to the shared bus. 2. The apparatus of claim 1, further comprising an external component controller coupled to the shared bus and the first external component, wherein prior to communicating with the first external component, the external component access unit and the first component are further configured. 2 The external component accesses the external component controller to request that the external component controller allocate the first external component to one of the dedicated bus and the shared bus. Device. 6. The apparatus of claim 5, further comprising a third external component connected to the dedicated bus and the shared bus, wherein the external component access unit further comprises the second external component connecting the third external component and the shared bus. And communicate with the third external component via one of the dedicated bus and the shared bus while communicating via the external bus. 7. The apparatus of claim 6, wherein the external component access unit communicates with the first external component via the dedicated bus and the second external component communicates with the third external component via the shared bus. External component access device. The apparatus of claim 1, wherein the second external component is a direct memory access unit that connects a plurality of external components to the first external component via the shared bus. 3. The external component of claim 2, wherein prior to requesting the external component access unit to initiate one of an external read operation and an external write operation, the processor programs the external component access unit. Access device. 10. The system of claim 9, wherein to program the external component access unit, the processor (i) informs the external component access unit to perform external access via one of the dedicated bus and the shared bus, ii) supplying an initial address in said first external component to said external component access unit. 11. The external component of claim 10, wherein the processor further programs the external component access unit by notifying the external component access unit that the external access is one of a single access operation and a block access operation. Access device. 5. The shared bus arbitration of claim 4, wherein prior to the external component access unit requiring the external component access unit to initiate an external read or write operation, the processor terminates the access of the external component access unit via the shared bus. And program the external component access unit to ignore an existing request. 3. The apparatus of claim 2, wherein the external component access unit initiates an external read operation by suspending operation of the processor to prefetch data from the first external component. The method of claim 9, (a) If the processor accesses the first external component via the external component access unit and the dedicated bus, the external component access device may execute X + when the external component access unit performs a write operation. Access the X position in the first external component in the Y clock cycle and in the X + Y + Z clock cycle when performing a read operation, (b) if the processor accesses the first external component via the external component access unit and the shared bus, then the external component access device performs X + Y when the external component access unit performs a write operation. Access the X position in the first external component in the + W clock cycle and in the X + Y + Z + W clock cycle when performing a read operation, (c) where Y represents the number of clock cycles required to program the external component access unit, Z represents the number of clock cycles required to prefetch data during a read operation, and W represents the external component access unit. And a number of clock cycles for which the external component access unit waits until the shared bus arbiter approves access to the shared bus. 15. The apparatus of claim 14, wherein the external component access unit is (a) a shared and dedicated bus interface coupled to the external component access unit bus, the shared bus, and the dedicated bus; And (b) a state machine block coupled to the external access unit bus and the shared and dedicated bus interface, Wherein the processor programs the external component access unit by providing programming data to the shared and dedicated bus interface along the external component access unit bus and receives the external access request from the processor. A bus interface accesses the first external component via one of the dedicated bus and the shared bus, The state machine block controls the operation of the shared and dedicated bus interface during an external access operation by supplying an enable signal to the shared and dedicated bus interface, the signal provided by the processor to the shared and dedicated bus interface and the sharing. And generate the enable signal in response to a signal supplied by the dedicated bus interface to the state machine block. The method of claim 15, (a) a shared and dedicated bus interface that connects to the processor to receive programming and external access statements from the processor instructing the shared and dedicated bus to access the first external component; And (b) a state machine block coupled to the shared and dedicated bus interface; The state machine block is connected to the processor and externally generated by an enable signal in response to a signal supplied by the processor to the shared and dedicated bus interface and a signal supplied by the shared and dedicated bus interface to the state machine block. And external device access device for controlling the operation of the shared and dedicated bus interface during an access operation. 17. The system of claim 16, wherein the shared and dedicated bus interface includes a plurality of prefetch registers for storing prefetched data, wherein the shared and dedicated bus interface requires an initial external read operation by the processor and the machine block. And prefetch data when the processor stops operating. (a) program memory; (b) a processor coupled to the program memory through a program memory bus; (c) an external component access unit coupled to the processor by an external component access unit bus; (d) a bidirectional dedicated bus connecting the external component access unit to an external memory; And (e) a bidirectional shared bus connecting the external component access unit and the external component to the external memory; Wherein the processor instructs the external component access unit to access the external memory along one of the dedicated bus and the shared bus, and the processor also uniquely accesses the dedicated bus for accessing the external memory. And wherein the external component denies access to the external memory when the processor is accessing the external memory.

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