KR100255188B1 - Preamplifier - Google Patents

Abstract

PURPOSE: An adaptive pre-amplifier having a recording current optimizing function, is provided to independently optimize recording-current only with an HDA(Head Disk Assembly) level of a hard disk driver. CONSTITUTION: A recording data generator(44) generates and outputs data having a specific pattern in order to measure a data error rate. The outputted recording data are recorded on a target sector on a disk in a magnetic type, through an encoder(64) and a pre-amplifier IC(Integrated Circuit)(20). If data recording is completed, a micro controller(28) is transformed to a data play mode, to read data from the target sector through the head. The signal played through the head is inputted to a play signal quality measurer(46) through RDX and RDY terminals of the pre-amplifier IC(20). The play signal quality measurer(46) outputs a value counting the quality of an inputted play signal to a window comparator(48). If the counted value inputted from the play signal quality measurer(46) exists within a window set as a reference value of the recording current, PWM(Pulse Width Modulation) is fixed and the recording current supplied to the head is recognized as an optimized recording-current.

Description

Adaptive Preamplifier with Write Current Optimization

The present invention relates to a preamplifier of a hard disk drive, and more particularly, to an adaptive preamplifier having a function of optimizing a recording current.

Hard disk drives, which are widely used as data storage devices for computer systems, have doubled the recording density every two to three years since the first products were developed by IBM in the late 1950s. Easily accessible around the road. Hard disk drives are largely classified as one of magnetic recording devices, but unlike other electronic devices, the related technologies are not only basic magnetic recording technologies but also a combination of electronic technologies, which can be a major research theme in each field. It is a combination of various high-tech technologies.

In general, hard disk drives can be divided into two parts. One part is a circuit subset in which most circuit components are mounted on a printed circuit board (PCB), and is generally called a printed circuit board assembly (PCBA). The other part is a set of instruments incorporating most of the mechanical components including some magnetic heads (or data transducers) and magnetic disks and some circuit components, commonly referred to as HDA (Head Disk Assembly). Hereinafter, a schematic mechanism structure of the HDA will be described with reference to FIG. 1.

1 shows a schematic mechanism structure of a general HDA, and shows an example in which two discs are mounted. Referring to FIG. 1, two disks 2 are installed in one spindle 12 as a stack and rotated by the spindle 12. The head 4 for recording, reproducing and erasing data on the disk 2 is lifted from the disk 2 as the disk 2 rotates. The head 4 is coupled via a suspension to a distal end of the support arm 8 of the rotary voice coil actuator 10. The actuator 10 moves the head 4 on the disk 2 in the radial direction, ie in the inner or outer circumferential direction. Signal transmission between the head 4 and the PCBA takes place via a head wire and a flexible printed circuit (FPC) 14. The head wire is generally installed along the suspension 6 and the arm 8 of the actuator 10 and soldered to the conductive pattern on the FPC 14. The FPC 14 and the PCBA are connected to each other by the connector 16.

On the other hand, when data is reproduced from the disc 2, the signal induced in the coil of the head 4 is extremely weak, typically about 50 mu V. When the weak signal is transmitted to the PCBA through the head wire and the FPC 14 as it is, the signal-to-noise ratio (SNR) is deteriorated due to noise, distortion, attenuation, etc. due to mutual interference between signal patterns. In other words, the amplitude of the signal is reduced. As a result, the signal induced in the head 4 is amplified as a preamplifier IC and then transferred to the PCBA. The preamplifier IC used at this time usually includes a head switching circuit. As an example of the preamplifier IC, a block diagram of SSI 32R2041RW manufactured by Silicon System Co., Ltd. is shown in FIG. 2. Since the SSI 32R2041RW is well-published in "STORAGE PRODUCTS 1994 DATA BOOK" published in 1994 by Silicon Systems, its detailed description will be omitted. Hereinafter, a configuration and operation of a hard disk drive useful for understanding the present invention will be described with reference to FIG. 3, which shows a block diagram of a general hard disk drive.

3 shows an example of a hard disk drive having two disks and four heads as in FIG. 1, which is divided into an HDA 50 and a PCBA 60. Referring to FIG. 3, the HDA 50 includes a disk 2, a head 4, an actuator 10, a preamplifier IC 20, an actuator motor 38, and a spindle motor 40. The PCBA 60 includes read / write channel circuits 22, a DDC (Disk Data Controller) 24, a buffer RAM 26, a microcontroller 28, a ROM 30, a servo driver 32, and a spindle motor. The drive section 34 and the disk signal control section 36 are provided. In the following description of the operation of the respective components, the two disks 2 installed in the stack 12 on the spindle 12 are rotated by the spindle motor 40. Each of the heads 4 is located on one of the disk surfaces corresponding to one of the disks 2 and is mounted to an actuator 10 coupled with the actuator motor 38. The preamplifier IC 20 connected to the head 4 preamplifies the analog read signal picked up by the head 4 during data reproduction and applies the preamplifier to the read / write channel circuit 22. The data is written onto the disc 2 by applying the write current according to the encoding write data applied from the write channel circuit 22 to the head 4. At this time, the preamplifier IC 20 selects head switching, that is, one of the four heads 4, by the head selection signal applied from the disk signal controller 36, and connects it to the read / write channel circuit 22. The read / write channel circuit 22 detects a data pulse from a read signal applied from the preamplifier IC 20, decodes the data pulse, applies the decoded data to the DDC 24, and decodes the write data applied from the DDC 24. Applied to the amplifier IC 20.

The DDC 24 is controlled by the microcontroller 28 and records data transmitted from the host computer on the disk 92 or transfers data reproduced from the disk 2 to the host computer. The DDC 24 also interfaces the communication between the host computer and the microcontroller 28. This DDC 24 is also referred to as an 'interface controller'. The buffer RAM 26 temporarily stores data transmitted between the host computer and the microcontroller 28 and the read / write channel circuit 22. On the other hand, the microcontroller 28 controls the data recording / reproducing operation by the DDC 24 in response to the recording / reproducing command input from the host computer and performs servo control for data recording / reproducing. The ROM 30 stores the execution program of the microcontroller 28 and various setting values.

The servo driver 32 generates a driving current for driving the actuator motor 38 by a signal for position control of the head 4 generated from the microcontroller 928 and applies it to the actuator motor 38. The actuator motor 38 is coupled to the actuator 10 and moves the head 4 on the disk 2 in correspondence with the direction and level of the drive current applied from the servo driver 32. The spindle motor driver 34 rotates the disc 2 by driving the spindle motor 40 according to a control value for rotation control of the disc 2 generated from the microcontroller 28. On the other hand, the disc signal controller 36 decodes servo information from the read data output from the read / write channel circuit 22 and applies it to the microcontroller 28 and transmits various control signals necessary for data recording / reproducing from the DDC 24. It is generated by the applied signal and the control of the microcontroller 28 and applied to the preamplifier IC 20, the read / write channel circuit 22, the DDC 24, and the like. The disk signal controller 36 typically uses an ASIC (Application Specific Integrated Circuit) designed for each hard disk drive.

In a typical hard disk drive having the above-described configuration, the quality of the signal reproduced from the disk 2 through the head 4 is the current applied to the head 4 at the time of data recording (hereinafter, it will be defined as a recording current). It can be said that it depends on setting the optimum condition. As a method employed in a conventional hard disk drive to optimize the recording current, as shown in FIG. 3, a combination of the HDA 50 and the PCBA 60 or a separate test equipment is combined with the HDA 50 to record various recording currents. The best case (ie, the lowest error rate) of the reproduced signal after application to (4) was considered to be optimized. That is, in the conventional hard disk drive, in order to optimize the recording current, the PCBA 60 or a separate test equipment must be combined with the HDA 50. However, the optimized write current only works in PCBA 60 or separate test equipment combined with HDA 50. If the PCBA 60 of the shipped hard disk drive fails and the PCBA 60 needs to be replaced, there is a manufacturing process problem that requires optimizing the recording current for the replaced PCBA 60 again. In addition, even when the HDA 50 is combined with a separate test equipment, since various types of test equipment are commercialized as described above, the system for evaluating the quality of the data reproduction signal is different, so that the work of mutually adjusting the final evaluation value is separate. There is a hassle needed.

Accordingly, an object of the present invention is to provide an adaptive preamplifier capable of independently optimizing the recording current only by the HDA level of the hard disk drive.

1 is a schematic mechanism diagram of a conventional HDA.

2 is a diagram illustrating a preamplifier IC for showing a block configuration of a preamplifier IC as one component of a hard disk drive.

3 is a block diagram of a general hard disk drive.

Figure 4 is a block diagram of an adaptive preamplifier according to an embodiment of the present invention.

Figure 5 is a detailed block diagram of an adaptive preamplifier according to an embodiment of the present invention.

Hereinafter, an operation according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

Figure 4 shows a block diagram of an adaptive preamplifier according to an embodiment of the present invention, Figure 5 shows a detailed block diagram of an adaptive preamplifier according to an embodiment of the present invention. Referring to FIG. 4, the adaptive preamplifier according to an embodiment of the present invention includes a pulse width modulation unit 42 and an SSI 32R2041RW one-chip IC 20 shown in FIG. 2 as an example of the conventional preamplifier. A recording data generator 44, a reproduction signal quality measuring section 46, and a window comparator 48 are added. Hereinafter, the configuration and operation of an adaptive preamplifier according to an embodiment of the present invention will be described with reference to FIGS. 4 and 5.

First, the pulse width modulator 42 connected to the write current control terminal WC of the preamplifier IC 20 of FIG. 4 is input from the microcontroller 28 according to the PWM fixed signal output from the window comparator 48. The pulse width of PWM "is variably output. On the other hand, between the output terminal of the pulse width modulator 42 and the write current control terminal WC of the preamplifier IC 20, external resistors R1, R2, R3 for controlling the write current are connected as shown in FIG. That is, the recording current value is determined by an external resistance element connected to the recording current control terminal WC. Therefore, the preamplifier IC 20 applies the recording current of the value corresponding to the amount of current of the recording current control terminal WC to the head 4 in accordance with the recording data when data is recorded on the disk 2. Meanwhile, the data terminal of the preamplifier IC 20 is shown in FIG. The recording data generator 44 connected to the data generator generates a recording data pattern in accordance with the NRZ data input from the read / write channel circuit 22 and the data terminal. Will output The write data generator 44 is composed of a shift register as shown in FIG. 5 to generate a pattern of write data, and extracts the output signal and the NRZ data of the data pattern generator 66. A data terminal of the preamplifier IC 20 by encoding the exclusive oragate 62 outputting the exclusive OR gating output and the output signal of the exclusive oragate 62. It consists of an encoder to output.

One input terminal of the exclusive oragate of the recording data generator 44 having the above-described configuration is a read / write channel circuit according to the switching on-off operation of the switch SW switched under the control of the microcontroller 28 in the user mode. NRZ data is input from (22). In addition, the switch SW is provided in the preamplifier IC 20 to perform the write current optimization function according to an embodiment of the present invention under the control of the microcontroller 28 F / F / Switch on and off with terminals. On the other hand, the reproduction signal quality measuring unit 46 measures the quality of the recording data signal input through the read data output terminals RDX and RDY of the preamplifier IC 20 to determine whether the amount of current recorded on the disc 2 is appropriate. The value is determined and output to the window comparator 48. In this case, the value output to the window comparator 48 may be expressed as a count value representing the quality of the signal reproduced from the disc 2. The window comparator 48 compares the count value input from the reproduction signal quality measuring unit 46 with the reference value of the recording current and outputs a PWM fixed signal for fixing the " PWM " value when the count value is within a set window range. do. Hereinafter, the operation of the adaptive preamplifier having the above-described configuration will be described with reference to FIGS. 4 and 5.

First, the mode selection of the conventional preamplifier was to select either "data recording" or "data reproduction" or to enable the preamplifier IC 20 chip function. However, in one embodiment of the present invention, the conventional preamplifier function is selected. "Factory Mode (F)" and "User Mode (U)" are added to optimize the recording current using the "Factory Mode" during the manufacturing process of the hard disk drive. The following describes the recording current optimization procedure in the "factory mode". First, in order to measure the data error rate, the recording data generator 44 generates and outputs data having a specific pattern, and the output recording data is output to the target sector on the disc 2 through the encoder 64 and the preamplifier IC 20. Is recorded in magnetic form on the image. When data recording is completed, the microcontroller 28 switches to the data reproducing mode and reads data from the target sector through the head 4. At this time, the signal reproduced through the head 4 is input to the reproduction signal quality measuring unit 46 through the RDX and RDY terminals of the preamplifier IC 20. The reproduction signal quality measuring unit 46 outputs a value obtained by counting the quality of the input reproduction signal to the window comparator 48. If the count value input from the reproduction signal quality measuring unit 46 is a value within the window range set as the reference value of the recording current, it is possible to fix "PWM" and recognize this as the optimized recording current at that point. That is, the microcontroller 28 can store the optimized recording current value in the "factory mode" and use it in the "user mode".

As described above, the present invention adds a user mode and a factory mode to the conventional preamplifier, and measures the quality of the recording current in the factory mode during the manufacturing process to optimize the recording current, thereby eliminating the need for a separate HDA test equipment.

Claims (4)

In adaptive preamplifiers for hard disk drives, Optimized recording current applied to the head when a recording current according to a predetermined data pattern capable of measuring a data error rate is applied to the head and the signal reproduced through the head has a value within a predetermined window range of the recording current. Adaptive preamplifier characterized by the setting of current. The adaptive preamplifier of claim 1, wherein the predetermined data pattern capable of measuring the data error rate is generated by a write data generator composed of shift registers. 3. The adaptive preamplifier of claim 2, wherein the recording current is a recording current converted into a digital value by a pulse width modulation method. 4. The adaptive preamplifier of claim 3, wherein the adaptive preamplifier includes a user and a factory mode terminal to optimize the recording current by the factory mode enable during the manufacturing process.