KR100250734B1 - Method of manufacturing inter insulation film of semiconductor device - Google Patents

Method of manufacturing inter insulation film of semiconductor device Download PDF

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KR100250734B1
KR100250734B1 KR1019960077152A KR19960077152A KR100250734B1 KR 100250734 B1 KR100250734 B1 KR 100250734B1 KR 1019960077152 A KR1019960077152 A KR 1019960077152A KR 19960077152 A KR19960077152 A KR 19960077152A KR 100250734 B1 KR100250734 B1 KR 100250734B1
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oxide film
film
forming
semiconductor device
layer
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KR1019960077152A
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KR19980057849A (en
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손용선
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김영환
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A device for forming an interlayer dielectric of a semiconductor device is provided to improve a flatness of a semiconductor device by using a layer laminated under an SOG(Silicon-On-Glass) layer as an etching stop layer. CONSTITUTION: A conductive layer pattern(13) is formed on a silicon substrate(11). An oxy-nitride layer(14) and a sacrificial oxide layer(15) are formed sequentially on an upper portion of the whole structure. An SOG layer(16) is formed on the upper portion of the whole structure. A hardening process is performed. The SOG layer(16) and the sacrificial oxide layer(15) are etched back by using the oxy-nitride layer(14) as an etching stop layer. An oxide layer(17) is formed on the upper portion of the whole structure.

Description

반도체 소자의 층간 절연막 형성 방법Method of forming interlayer insulating film of semiconductor device

본 발명은 반도체 소자의 층간 절연막 형성 방법에 관한 것으로, 특히 도전층간의 절연 및 평탄화를 목적으로 형성하는 반도체 소자의 층간 절연막 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming an interlayer insulating film of a semiconductor device, and more particularly, to a method for forming an interlayer insulating film of a semiconductor device formed for the purpose of insulating and planarization between conductive layers.

일반적으로 반도체 소자의 제조 공정에서 도전층은 이중 또는 다중 구조로 형성되며 도전층간에는 절연 및 평탄화를 위한 층간 절연막이 형성된다. 그러면 종래 반도체 소자의 층간 절연막 형성 방법을 도1a 내지 도1c를 통해 설명하면 다음과 같다.In general, in the manufacturing process of a semiconductor device, the conductive layer has a double or multiple structure, and an interlayer insulating film for insulation and planarization is formed between the conductive layers. A method of forming an interlayer insulating film of a conventional semiconductor device will now be described with reference to FIGS. 1A to 1C.

도1a는 절연막(2)이 형성된 실리콘 기판(1)상에 도전층 패턴(3)을 형성한 후 전체 상부면에 제1산화막(4)을 형성하고 상기 제1산화막(3)상에 SOG막(5)을 도포한 상태의 단면도이다.FIG. 1A shows that after forming the conductive layer pattern 3 on the silicon substrate 1 on which the insulating film 2 is formed, the first oxide film 4 is formed on the entire upper surface, and the SOG film is formed on the first oxide film 3. It is sectional drawing of the state which apply | coated (5).

도1b는 표면을 평탄화시키기 위하여 상기 SOG막(5)을 에치백한 상태의 단면도로서, 이때 상기 SOG막(5)이 과도 식각되는 경우 상기 도전층 패턴(3)이 노출되고 표면의 평탄도가 불량해진다. 이러한 현상은 상기 에치백 공정시 식각 정지점을 정확하게 감지하지 못함에 따라 발생되는데, 상기 SOG막(5)이 상기 도전층 패턴(3)과 접촉되는 경우 상기 SOG막(5)으로부터 방출되는 수분에 의해 후속 공정시 불량이 발생되거나 소자의 신뢰성이 저하된다.FIG. 1B is a cross-sectional view of the SOG film 5 etched back to planarize the surface. In this case, when the SOG film 5 is excessively etched, the conductive layer pattern 3 is exposed and the flatness of the surface is exposed. It becomes bad. This phenomenon occurs when the etching stop point is not accurately sensed during the etch back process. When the SOG film 5 is in contact with the conductive layer pattern 3, the moisture is emitted from the SOG film 5. As a result, defects occur in subsequent processes or the reliability of the device is degraded.

도1c는 전체 상부면에 제2산화막(6)을 형성한 상태의 단면도인데, 전체적인 표면의 평탄도가 불량한 상태가 도시된다. 그러므로 이러한 표면의 평탄도불량에 의해 후속 공정의 진행이 어려워지고 심한 경우 소자의 불량이 유발되기 때문에 상기와 같은 방법을 0.25㎛이하의 디자인 룰(Design Rule)을 갖는 고집적 소자의 제조에 적용하기 어렵게 된다.FIG. 1C is a cross-sectional view of a state in which the second oxide film 6 is formed on the entire upper surface, and a state in which the flatness of the entire surface is poor is shown. Therefore, it is difficult to apply the above method to the fabrication of highly integrated devices having design rules of 0.25 μm or less, because of poor surface flatness, which makes it difficult to proceed with subsequent processes and, in severe cases, causes device defects. do.

따라서 본 발명은 SOG막 하부에 질화산화막과 산화막이 적층된 막을 형성하므로써 상기한 단점을 해소할 수 있는 반도체 소자의 층간 절연막 형성 방법을 제공하는 데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming an interlayer insulating film of a semiconductor device which can solve the above-mentioned disadvantages by forming a film in which a nitride oxide film and an oxide film are stacked below the SOG film.

상기한 목적을 달성하기 위한 본 발명은 실리콘 기판상에 도전층 패턴을 형성한 후 전체 상부면에 질화 산화막 및 희생 산화막을 순차적으로 형성하는 단계와, 전체 상부면에 SOG막을 증착한 후 경화 공정을 실시하는 단계와, 상기 질화 산화막을 식각 정지 감지층으로 이용하여 상기 SOG막 및 희생 산화막을 에치 백하는 단계와, 전체 상부면에 산화막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a nitride layer and a sacrificial oxide film sequentially on the entire upper surface after forming a conductive layer pattern on the silicon substrate, and after the SOG film is deposited on the entire upper surface of the curing process And etching back the SOG film and the sacrificial oxide film using the nitride oxide film as an etch stop detection layer, and forming an oxide film on the entire upper surface thereof.

도1a 내지 도1c는 종래 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of forming an interlayer insulating film of a conventional semiconductor device.

도2a 내지 도2d는 본 발명에 따른 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도.2A to 2D are cross-sectional views of a device for explaining a method for forming an interlayer insulating film of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1,11 : 실리콘 기판 2,12 : 절연막1,11 silicon substrate 2,12 insulating film

3,13 : 도전층 패턴 4 : 제1산화막3,13: conductive layer pattern 4: first oxide film

5,16 : SOG막 6 : 제2산화막5,16 SOG film 6: Second oxide film

14 : 제1절연막 15 : 제2절연막14: first insulating film 15: second insulating film

17 : 제3절연막17: third insulating film

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도2a 내지 도2d는 본 발명에 따른 반도체 소자의 층간 절연막 형성 방법을 설명하기 위한 소자의 단면도로서, 도2a는 절연막(12)이 형성된 실리콘 기판(11)상에 도전층 패턴(13)을 형성한 후 전체 상부면에 제1절연막(14) 및 제2절연막(15)을 순차적으로 형성한 상태의 단면도로서, 상기 제1절연막(14)은 질화산화막(SiOxNyHz)으로 형성하며 상기 제2절연막(15)은 산화막(SiO2-xHy)으로 형성한다. 이때 상기 질화산화막(SiOxNyHz) 및 산화막(SiO2-xHy)은 플라즈마 화학기상증착(PECVD) 반응로내에서 SiH4및 N2O 가스의 반응을 이용하여 인-시투(In-Situ)로 형성한다. 또한 이때 상기 질화산화막(SiOxNyHz)은 SiH4, N2O 및 NH3가스의 반응을 이용하여 형성하며 상기 산화막(SiO2-xHy)은 SiH4및 N2O 가스의 반응을 이용하여 형성해도 된다.2A to 2D are cross-sectional views of devices for explaining the method for forming an interlayer insulating film of a semiconductor device according to the present invention. After that, the first insulating film 14 and the second insulating film 15 are sequentially formed on the entire upper surface, and the first insulating film 14 is formed of a nitride oxide film (SiO x N y H z ). The second insulating layer 15 is formed of an oxide film (SiO 2-x H y ). In this case, the nitride oxide film (SiO x N y H z ) and the oxide film (SiO 2-x H y ) are formed in-situ using a reaction of SiH 4 and N 2 O gas in a plasma chemical vapor deposition (PECVD) reactor. In-Situ). In addition, the nitride oxide film (SiO x N y H z ) is formed by the reaction of SiH 4 , N 2 O and NH 3 gas and the oxide film (SiO 2-x H y ) is formed of SiH 4 and N 2 O gas You may form using reaction.

도2b는 상기 제2절연막(15)상에 SOG막(16)을 도포한 후 450℃ 이하, 예를들어 10 내지 450℃의 온도에서 경화 공정을 실시한 형태의 단면도이다.FIG. 2B is a cross-sectional view of the hardening process performed at a temperature of 450 ° C. or lower, for example, 10 to 450 ° C. after the SOG film 16 is applied on the second insulating film 15.

도2c는 상기 제1절연막(14)이 노출되는 시점까지 상기 SOG막(16)을 불소가 함유 플라즈마를 이용하여 에치 백한 상태의 단면도로서, 상기 에치백 공정시 잔류 가스 분석기를 이용하여 식각 정지점을 검출하므로써 표면의 평탄도가 양호해진다. 이때, 상기 SOG막(16) 에치백 공정을 부가 설명하면 다음과 같다.FIG. 2C is a cross-sectional view of the SOG film 16 etched back using a fluorine-containing plasma until the first insulating film 14 is exposed, and an etch stop point using a residual gas analyzer during the etchback process. The surface flatness is improved by detecting. In this case, the SOG film 16 etch back process will be further described as follows.

상기 불소가 함유된 가스를 이용한 플라즈마 식각 공정으로 상기 SOG막(16)을 에치백하면 소정 시간 후 상기 제2절연막(15) 및 제1절연막(14)이 순차적으로 노출된다. 이때 상기 질화 산화막인 제1절연막(14)이 식각되면 반응로내에 질소 및 불화질소와 같은 질소 성분의 반응 부산물이 생성되는데, 이를 상기 잔류 가스 분석기가 감지하여 식각 공정을 정지시키게 된다. 여기서 상기 제2절연막(15)은 희생산화막으로 이용된다.When the SOG film 16 is etched back by a plasma etching process using the fluorine-containing gas, the second insulating film 15 and the first insulating film 14 are sequentially exposed after a predetermined time. In this case, when the first insulating layer 14, which is the nitride oxide film, is etched, reaction by-products of nitrogen components such as nitrogen and nitrogen fluoride are generated in the reactor, and the residual gas analyzer detects this to stop the etching process. In this case, the second insulating layer 15 is used as a sacrificial oxide layer.

도2d는 전체 상부면에 제3절연막(17)을 형성한 상태의 단면도로서, 상기 제3절연막(17)은 산화막(SiO2-xHy)으로 형성된다.FIG. 2D is a cross-sectional view of the third insulating film 17 formed on the entire upper surface, and the third insulating film 17 is formed of an oxide film (SiO 2-x H y ).

상술한 바와 같이 본 발명에 의하면 SOG막 하부에 질화산화막과 산화막이 적층된 막을 형성하고, 이를 SOG막 에치백시 식각 정지점으로 이용하므로써 공정의 안정화를 이루며 용이하게 표면의 평탄도를 향상시킬 수 있다. 그러므로 소자의 신뢰성 및 수율이 향상될 수 있으며, 따라서 본 발명은 0.25㎛이하의 디자인 룰을 갖는 고집적 소자의 제조에 적용될 수 있다.As described above, according to the present invention, by forming a nitride oxide film and an oxide film laminated under the SOG film, and using this as an etch stop point during etch back of the SOG film, the surface flatness can be easily stabilized and the surface flatness can be easily improved. have. Therefore, the reliability and yield of the device can be improved, and thus the present invention can be applied to the manufacture of highly integrated devices having design rules of 0.25 탆 or less.

Claims (6)

(정정)실리콘 기판상에 도전층 패턴을 형성한 후 전체 상부면에 질화 산화막 및 희생 산화막을 순차적으로 형성하는 단계와, 전체 상부면에 SOG막을 증착한 후 경화 공정을 실시하는 단계와, 상기 질화 산화막을 식각 정지 감지층으로 이용하여 상기 SOG막 및 희생 산화막을 에치 백하는 단계와, 전체 상부면에 산화막을 형성하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.Forming a conductive layer pattern on the silicon substrate and sequentially forming a nitride oxide film and a sacrificial oxide film on the entire upper surface; depositing a SOG film on the entire upper surface and performing a curing process; And etching back the SOG film and the sacrificial oxide film using an oxide film as an etch stop sensing layer, and forming an oxide film on the entire upper surface. (정정)제1항에 있어서, 상기 질화 산화막 및 희생 산화막은 인-시투로 형성되는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.(Correction) The method for forming an interlayer insulating film of a semiconductor device according to claim 1, wherein the nitride oxide film and the sacrificial oxide film are formed in-situ. (정정)제1항에 있어서, 상기 에치 백 공정은 불소가 함유된 플라즈마를 이용하여 실시하는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.(Correction) The method for forming an interlayer insulating film of a semiconductor device according to claim 1, wherein said etch back process is performed using a plasma containing fluorine. (정정)제1항에 있어서, 상기 질화 산화막 및 희생 산화막은 SiH4및 N2O 가스의 반응을 이용한 플라즈마 화학기상증착 방법으로 형성된 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.(Correction) The method for forming an interlayer insulating film of a semiconductor device according to claim 1, wherein the nitride oxide film and the sacrificial oxide film are formed by a plasma chemical vapor deposition method using a reaction of SiH 4 and N 2 O gases. (정정)제1항에 있어서, 상기 질화산화막은 SiH4, N2O 및 NH3가스의 반응에 의해 형성된 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.(Correction) The method for forming an interlayer insulating film of a semiconductor device according to claim 1, wherein said nitride oxide film is formed by reaction of SiH 4 , N 2 O, and NH 3 gas. 제1항에 있어서, 상기 경화 공정은 10 내지 450℃의 온도에서 실시되는 것을 특징으로 하는 반도체 소자의 층간 절연막 형성 방법.The method of claim 1, wherein the curing step is performed at a temperature of 10 to 450 ° C. 7.
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