KR100249522B1 - Clock generating circuit - Google Patents

Abstract

Compared to the conventional clock generation circuit in which shaking occurs even in the minute change of the input clock, the present invention reproduces a clock having a small jitter, thereby preventing data corruption during signal transmission between units and devices, and implementing system operation with improved performance. To a stable clock generation circuit.

The stable clock generation circuit according to the present invention,

A phase comparator for receiving an input clock f _r and a comparison clock f _i and comparing phases of two signals; A low pass filter for low pass filtering the output of the phase comparator; A voltage controlled oscillator for varying a fundamental frequency and outputting the output of the low pass filter; A divider A for generating a final clock by inputting the output f _o of the voltage controlled oscillator; And a divider B for dividing the output f _o of the voltage controlled oscillator to generate a comparison clock f _i input to the phase comparator, and a divider C for determining the number of divisions of the divider B. It features.

Description

Stable Clock Generation Circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stable clock generation circuit, and more particularly to a jitter in a phase locked loop (PLL) circuit that produces a stable clock synchronized with an input clock for the purpose of preventing loss in signal transmission in a communication system. It is related with the clock generation circuit for making () small.

Mobile communication systems, such as Personal Communication Service (PCS) and Code Division Multiple Access (CDMA), have a number of base station transceivers serving mobile terminals (mobile stations) moving within a certain area. Subsystem: BTS, Base Station Controller (BSC), Base Station Manager System (BSM) that manages and manages multiple Base Station Controllers, Mobile Switching Center (MSC) and Location Registration System It is.

The area serviced by each base station is called a cell, and is generally divided into three sectors. This cell expands to the base station area, base station controller area, and switching center service area in order.

As described above, a communication system using one cell as a unit is called a cellular system.

A mobile station in each cell establishes a channel and communicates with a base station serving that cell. In this case, a channel formed in the direction of the mobile station from the base station is called a forward channel, and a channel formed in the direction of the base station from the mobile station is called a reverse channel.

The base station transmits the data received from the base station controller to the mobile terminal. In this case, an accurate and stable clock must be used for data transmission.

The communication system uses a phase locked loop (PLL) to receive a clock of 16.384 MHz and generate a clock of 155.52 MHz.

The phase locked loop basically includes a phase comparator, a loop filter, and a voltage controlled oscillator.

In general, a phase comparator examines the phase difference between two signals to produce an output voltage proportional to this phase difference. The loop filter adjusts the dynamic response of the phase locked loop.

A voltage controlled oscillator produces a periodic waveform with a fundamental amplitude proportional to the input voltage and of constant amplitude.

1 shows a clock generation circuit according to the prior art.

As shown, divider A (/ 32) 110; A phase comparator 120; A low pass filter 130; A voltage controlled oscillator 140; It is composed of a divider B (/ 4) 150 and a divider C (/ 1215).

An input clock f _r of 16.384 MHz is inputted to the phase comparator 120 via the divider A (/ 32) 110 and becomes a signal of 0.512 MHz (f _i ) (= 16.384 ÷ 32).

In addition, the 622.08 MHz frequency f _o generated by the voltage controlled oscillator becomes a signal of 0.512 MHz through the divider C (/ 1215) 160 and is input to the phase comparator 120.

The two 0.512 MHz signals are compared by the phase comparator 120 to pass through the low pass filter 130 to remove the high pass signal, and then input the voltage controlled oscillator 140.

The voltage controlled oscillator 140 outputs a voltage controlled oscillator output clock f _o of 622.08 MHz whose fundamental frequency is changed by the magnitude of the input voltage.

The voltage controlled oscillator output clock f _o is input to the divider B (/ 4) 150 to finally generate an output clock of 155.52 MHz.

Comparing the clock at each position in the circuit with the equation is as shown in equation (1).

f _r = f _i × 32 = (f _o ÷ 1215) × 32

f _o = f _r × (1215 ÷ 32) = f _r × (37.96875)

Therefore, the time width of the clock f _i input to the phase comparator 120 is expressed by Equation 2 below.

As shown in Equation 2, the phase comparator 120 compares the phases in a period of 2 ms.

The voltage controlled oscillator 140 is driven by an input voltage. At this time, if the period of phase comparison is large, the voltage variation rate is increased, thereby regenerating a clock having an unstable frequency.

When generating the voltage due to the period calculated in Equation (2), the voltage fluctuation rate is increased, it does not have a stable voltage value due to the minute leakage current of the circuit itself.

Therefore, the clock generation circuit according to the prior art generates a problem that a jitter whose waveform is disturbed momentarily generates a large clock.

Therefore, in order to solve the problems as described above,

It is an object of the present invention to provide a stable clock generation circuit for reproducing a clock with low jitter and improving system performance with stable operation by reducing a clock width input to a phase comparator in a phase locked loop for clock generation.

1 is a block diagram of a clock generation circuit according to the prior art;

2 is a block diagram of a clock generation circuit according to the present invention;

<Description of the code | symbol about the principal part of drawing>

110: divider A (/ 32) 120: phase comparator

130: low pass filter 140: voltage controlled oscillator

150: frequency divider B (/ 4) 160: frequency divider C (/ 1215)

210: phase comparator 220: low pass filter

230: voltage controlled oscillator 240: divider A (/ 4)

250: Divider B (/ 38, / 37) 260: Divider C (/ 32)

The present invention was created to achieve the above object,

A phase comparator for receiving an input clock f _r and a comparison clock f _i and comparing phases of two signals; A low pass filter for low pass filtering the output of the phase comparator; A voltage controlled oscillator for varying a fundamental frequency and outputting the output of the low pass filter; A divider A for generating a final clock by inputting the output f _o of the voltage controlled oscillator; And a divider B for dividing the output f _o of the voltage controlled oscillator to generate a comparison clock f _i input to the phase comparator, and a divider C for determining the number of divisions of the divider B. It features.

The present invention constitutes a circuit in which a high frequency input clock is input directly to a phase comparator without going through a divider and uses a two stage divider for the output of the voltage controlled oscillator to provide a comparison clock like the input clock.

That is, in order to reproduce the stable clock, the input clock f _r of 16.384 MHz is input directly to the phase comparator by reducing the time width input to the phase comparator.

In addition, another input of the phase comparator, the comparison clock (f _i ) performed a two-stage division of the 622.08MHz clock (f _o ) of the output of the voltage-controlled oscillator to make the frequency approximately the same as the input clock (f _r ).

2 shows a stable clock generation circuit according to the present invention.

As shown, an input phase comparator 210 for comparing the phase of the input clock f _r and the comparison clock f _{i of} 16.384 MHz; A low pass filter (220) for low pass filtering the phase compared signal; A voltage controlled oscillator (230) whose frequency is varied by the filtered signal; A divider A (/ 4) (240) for dividing the frequency of the frequency-variable output clock (f _o ) to finally generate an output clock of 155.52 MHz; Wherein the voltage frequency from the control oscillator 230, a variable output clock (f _o) the second stage to dispense cycle for generating a comparison clock (fi) that is input to the phase comparator (210) B (/ 38, / 37) ( 250); The frequency divider C (/ 32) 260 is configured to determine the frequency division number of the frequency divider B (/ 38, / 37) 250.

The input clock f _r of 16.384 MHz is not divided and is input to the phase comparator 210 as it is.

In addition, the output clock f _o of 622.08 MHz output from the voltage controlled oscillator 230 passes through the divider B 250 and the divider C 260 to become a comparison clock f _i of 16.384 MHz, thereby providing a phase comparator. Inputted at 210.

The phase comparator 210 outputs a signal obtained by comparing the phases of the input clock f _r and the comparison clock f _i , and the signal is filtered by the low pass filter 220.

The filtered signal is input to the voltage controlled oscillator 230 and controlled by an output clock f _o having a frequency of 622.08 MHz by the voltage.

The output clock f _o is divided by the divider A (/ 4) 240 and finally becomes an output clock of 155.52 MHz.

The frequency divider B (/ 38, / 37) 250 performs a total of 32 divisions by the frequency divider C (/ 32) 260, and performs a 38 frequency division operation during the first 31 cycles and the last 32 cycles. In 37 minutes. Therefore, the total frequency divided over 32 cycles is as shown in Equation 3.

(32-1) × 38 + 1 × (38-1) = 1215

Then, the average frequency divider for one cycle is as shown in Equation 4.

1215 ÷ 32 = 37.96875

That is, the division ratio consisting of the two-stage divider is expressed by Equation 5.

By dividing the output clock f _o of 622.08 MHz using the division ratio as shown in Equation 5, the comparison clock f _i , which is the output of the divider B (/ 38, / 37) 250, is input clock ( f _r ) and have the same frequency (16.384 MHz).

The relationship between the output clock f _o and the comparison clock f _i of the voltage controlled oscillator obtained through the above process is shown in Equation 6.

Therefore, the time width of the clock input to the phase comparator is represented by Equation 7, which is much smaller than 2 ms according to the prior art.

When the voltage is generated using the phase comparator according to the period, the voltage variation rate is smaller than that in the prior art, and as a result, a clock having a very small jitter component can be reproduced compared to the prior art using the phase comparator by 2 Hz.

The present invention operating as described above,

By reducing the time width of the clock input to the phase comparator, a clock with small jitter can be reproduced even with a minute change in the input clock, thereby preventing data corruption during signal transmission between units and devices, thereby realizing improved system operation.

In addition, the ASIC can be achieved by miniaturizing the clock circuit and making the work more efficient.

Claims (8)

A clock generation circuit for reducing jitter in a phase locked loop (PLL) circuit that generates a stable clock synchronized with an input clock for the purpose of preventing loss during signal transmission in a communication system, A phase comparator for receiving an input clock f _r and a comparison clock f _i and comparing phases of two signals; A low pass filter for low pass filtering the output of the phase comparator; A voltage controlled oscillator for varying a fundamental frequency and outputting the output of the low pass filter; A divider A for generating a final clock by inputting the output f _o of the voltage controlled oscillator; A divider B for dividing the output f _o of the voltage controlled oscillator to generate a comparison clock f _i input to the phase comparator; And a divider C for determining the divided number of the divider B. 2. The method of claim 1, And the clock generating circuit generates a clock of 155.52 MHz in the divider A with a clock of 16.384 MHz as the input of the phase comparator. The method of claim 2, And the divider A performs four-division operation. The method of claim 2, And said divider C performs a 32-division operation. The method of claim 2, The divider B performs a 38-division operation during the first 31 cycles of the 32 cycles, and performs a 37-division operation during the last 32 cycles. 2. The stable clock generation circuit according to claim 1, wherein the output clock of the voltage controlled oscillator is input to the phase comparator by generating a frequency equal to an input clock using 38 and 32 dividers. 7. The stable clock generation circuit according to claim 6, wherein the divider is a two stage divider in which an output clock of a voltage controlled oscillator is fed back to the phase comparator. The stable clock generation circuit according to claim 1, wherein the phase-locked loop is ASICized.

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